1[ 2 { 3 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4 "CounterMask": "6", 5 "EventCode": "0xa3", 6 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x6" 9 }, 10 { 11 "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 12 "EventCode": "0xc3", 13 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 14 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 15 "SampleAfterValue": "100003", 16 "UMask": "0x2" 17 }, 18 { 19 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 20 "Data_LA": "1", 21 "EventCode": "0xcd", 22 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 23 "MSRIndex": "0x3F6", 24 "MSRValue": "0x80", 25 "PEBS": "2", 26 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 27 "SampleAfterValue": "1009", 28 "UMask": "0x1" 29 }, 30 { 31 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 32 "Data_LA": "1", 33 "EventCode": "0xcd", 34 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 35 "MSRIndex": "0x3F6", 36 "MSRValue": "0x10", 37 "PEBS": "2", 38 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 39 "SampleAfterValue": "20011", 40 "UMask": "0x1" 41 }, 42 { 43 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 44 "Data_LA": "1", 45 "EventCode": "0xcd", 46 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 47 "MSRIndex": "0x3F6", 48 "MSRValue": "0x100", 49 "PEBS": "2", 50 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 51 "SampleAfterValue": "503", 52 "UMask": "0x1" 53 }, 54 { 55 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 56 "Data_LA": "1", 57 "EventCode": "0xcd", 58 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 59 "MSRIndex": "0x3F6", 60 "MSRValue": "0x20", 61 "PEBS": "2", 62 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 63 "SampleAfterValue": "100007", 64 "UMask": "0x1" 65 }, 66 { 67 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 68 "Data_LA": "1", 69 "EventCode": "0xcd", 70 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 71 "MSRIndex": "0x3F6", 72 "MSRValue": "0x4", 73 "PEBS": "2", 74 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 75 "SampleAfterValue": "100003", 76 "UMask": "0x1" 77 }, 78 { 79 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 80 "Data_LA": "1", 81 "EventCode": "0xcd", 82 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 83 "MSRIndex": "0x3F6", 84 "MSRValue": "0x200", 85 "PEBS": "2", 86 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 87 "SampleAfterValue": "101", 88 "UMask": "0x1" 89 }, 90 { 91 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 92 "Data_LA": "1", 93 "EventCode": "0xcd", 94 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 95 "MSRIndex": "0x3F6", 96 "MSRValue": "0x40", 97 "PEBS": "2", 98 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 99 "SampleAfterValue": "2003", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 104 "Data_LA": "1", 105 "EventCode": "0xcd", 106 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 107 "MSRIndex": "0x3F6", 108 "MSRValue": "0x8", 109 "PEBS": "2", 110 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 111 "SampleAfterValue": "50021", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "Demand Data Read requests who miss L3 cache", 116 "EventCode": "0xb0", 117 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 118 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 119 "SampleAfterValue": "100003", 120 "UMask": "0x10" 121 }, 122 { 123 "BriefDescription": "Number of times an RTM execution aborted.", 124 "EventCode": "0xc9", 125 "EventName": "RTM_RETIRED.ABORTED", 126 "PublicDescription": "Counts the number of times RTM abort was triggered.", 127 "SampleAfterValue": "100003", 128 "UMask": "0x4" 129 }, 130 { 131 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 132 "EventCode": "0xc9", 133 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 134 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 135 "SampleAfterValue": "100003", 136 "UMask": "0x80" 137 }, 138 { 139 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 140 "EventCode": "0xc9", 141 "EventName": "RTM_RETIRED.ABORTED_MEM", 142 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 143 "SampleAfterValue": "100003", 144 "UMask": "0x8" 145 }, 146 { 147 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 148 "EventCode": "0xc9", 149 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 150 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 151 "SampleAfterValue": "100003", 152 "UMask": "0x40" 153 }, 154 { 155 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 156 "EventCode": "0xc9", 157 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 158 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 159 "SampleAfterValue": "100003", 160 "UMask": "0x20" 161 }, 162 { 163 "BriefDescription": "Number of times an RTM execution successfully committed", 164 "EventCode": "0xc9", 165 "EventName": "RTM_RETIRED.COMMIT", 166 "PublicDescription": "Counts the number of times RTM commit succeeded.", 167 "SampleAfterValue": "100003", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "Number of times an RTM execution started.", 172 "EventCode": "0xc9", 173 "EventName": "RTM_RETIRED.START", 174 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 175 "SampleAfterValue": "100003", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 180 "EventCode": "0x5d", 181 "EventName": "TX_EXEC.MISC2", 182 "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 183 "SampleAfterValue": "100003", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 188 "EventCode": "0x5d", 189 "EventName": "TX_EXEC.MISC3", 190 "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 191 "SampleAfterValue": "100003", 192 "UMask": "0x4" 193 }, 194 { 195 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 196 "EventCode": "0x54", 197 "EventName": "TX_MEM.ABORT_CAPACITY_READ", 198 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 199 "SampleAfterValue": "100003", 200 "UMask": "0x80" 201 }, 202 { 203 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 204 "EventCode": "0x54", 205 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 206 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 207 "SampleAfterValue": "100003", 208 "UMask": "0x2" 209 }, 210 { 211 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 212 "EventCode": "0x54", 213 "EventName": "TX_MEM.ABORT_CONFLICT", 214 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 215 "SampleAfterValue": "100003", 216 "UMask": "0x1" 217 } 218] 219