1[ 2 { 3 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x85", 7 "EventName": "ITLB_MISSES.STLB_HIT", 8 "SampleAfterValue": "100003", 9 "UMask": "0x20" 10 }, 11 { 12 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 13 "Counter": "0,1,2,3", 14 "CounterHTOff": "0,1,2,3,4,5,6,7", 15 "EventCode": "0x49", 16 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 17 "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", 18 "SampleAfterValue": "100003", 19 "UMask": "0x1" 20 }, 21 { 22 "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", 23 "Counter": "0,1,2,3", 24 "CounterHTOff": "0,1,2,3,4,5,6,7", 25 "EventCode": "0x49", 26 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 27 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 28 "SampleAfterValue": "100003", 29 "UMask": "0x4" 30 }, 31 { 32 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", 33 "Counter": "0,1,2,3", 34 "CounterHTOff": "0,1,2,3,4,5,6,7", 35 "EventCode": "0x85", 36 "EventName": "ITLB_MISSES.WALK_PENDING", 37 "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", 38 "SampleAfterValue": "100003", 39 "UMask": "0x10" 40 }, 41 { 42 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 43 "Counter": "0,1,2,3", 44 "CounterHTOff": "0,1,2,3,4,5,6,7", 45 "EventCode": "0x85", 46 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 47 "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", 48 "SampleAfterValue": "100003", 49 "UMask": "0x2" 50 }, 51 { 52 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 53 "Counter": "0,1,2,3", 54 "CounterHTOff": "0,1,2,3,4,5,6,7", 55 "EventCode": "0xAE", 56 "EventName": "ITLB.ITLB_FLUSH", 57 "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", 58 "SampleAfterValue": "100007", 59 "UMask": "0x1" 60 }, 61 { 62 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", 63 "Counter": "0,1,2,3", 64 "CounterHTOff": "0,1,2,3,4,5,6,7", 65 "CounterMask": "1", 66 "EventCode": "0x85", 67 "EventName": "ITLB_MISSES.WALK_ACTIVE", 68 "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.", 69 "SampleAfterValue": "100003", 70 "UMask": "0x10" 71 }, 72 { 73 "BriefDescription": "Loads that miss the DTLB and hit the STLB.", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3,4,5,6,7", 76 "EventCode": "0x08", 77 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 78 "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 79 "SampleAfterValue": "2000003", 80 "UMask": "0x20" 81 }, 82 { 83 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", 84 "Counter": "0,1,2,3", 85 "CounterHTOff": "0,1,2,3,4,5,6,7", 86 "EventCode": "0x49", 87 "EventName": "DTLB_STORE_MISSES.WALK_PENDING", 88 "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", 89 "SampleAfterValue": "2000003", 90 "UMask": "0x10" 91 }, 92 { 93 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 94 "Counter": "0,1,2,3", 95 "CounterHTOff": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xBD", 97 "EventName": "TLB_FLUSH.DTLB_THREAD", 98 "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", 99 "SampleAfterValue": "100007", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", 104 "Counter": "0,1,2,3", 105 "CounterHTOff": "0,1,2,3,4,5,6,7", 106 "EventCode": "0x08", 107 "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", 108 "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.", 109 "SampleAfterValue": "2000003", 110 "UMask": "0x10" 111 }, 112 { 113 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", 114 "Counter": "0,1,2,3", 115 "CounterHTOff": "0,1,2,3,4,5,6,7", 116 "CounterMask": "1", 117 "EventCode": "0x49", 118 "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", 119 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", 120 "SampleAfterValue": "100003", 121 "UMask": "0x10" 122 }, 123 { 124 "BriefDescription": "Misses at all ITLB levels that cause page walks", 125 "Counter": "0,1,2,3", 126 "CounterHTOff": "0,1,2,3,4,5,6,7", 127 "EventCode": "0x85", 128 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 129 "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.", 130 "SampleAfterValue": "100003", 131 "UMask": "0x1" 132 }, 133 { 134 "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 135 "Counter": "0,1,2,3", 136 "CounterHTOff": "0,1,2,3,4,5,6,7", 137 "EventCode": "0x49", 138 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 139 "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 140 "SampleAfterValue": "100003", 141 "UMask": "0x20" 142 }, 143 { 144 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", 145 "Counter": "0,1,2,3", 146 "CounterHTOff": "0,1,2,3,4,5,6,7", 147 "EventCode": "0x49", 148 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 149 "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", 150 "SampleAfterValue": "100003", 151 "UMask": "0xe" 152 }, 153 { 154 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 155 "Counter": "0,1,2,3", 156 "CounterHTOff": "0,1,2,3,4,5,6,7", 157 "EventCode": "0x08", 158 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 159 "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.", 160 "SampleAfterValue": "100003", 161 "UMask": "0xe" 162 }, 163 { 164 "BriefDescription": "Page walk completed due to a demand data store to a 4K page", 165 "Counter": "0,1,2,3", 166 "CounterHTOff": "0,1,2,3,4,5,6,7", 167 "EventCode": "0x49", 168 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 169 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 170 "SampleAfterValue": "100003", 171 "UMask": "0x2" 172 }, 173 { 174 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", 175 "Counter": "0,1,2,3", 176 "CounterHTOff": "0,1,2,3,4,5,6,7", 177 "EventCode": "0x85", 178 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 179 "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", 180 "SampleAfterValue": "100003", 181 "UMask": "0x8" 182 }, 183 { 184 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", 185 "Counter": "0,1,2,3", 186 "CounterHTOff": "0,1,2,3,4,5,6,7", 187 "EventCode": "0x85", 188 "EventName": "ITLB_MISSES.WALK_COMPLETED", 189 "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.", 190 "SampleAfterValue": "100003", 191 "UMask": "0xe" 192 }, 193 { 194 "BriefDescription": "Page walk completed due to a demand data load to a 4K page", 195 "Counter": "0,1,2,3", 196 "CounterHTOff": "0,1,2,3,4,5,6,7", 197 "EventCode": "0x08", 198 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 199 "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 200 "SampleAfterValue": "2000003", 201 "UMask": "0x2" 202 }, 203 { 204 "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", 205 "Counter": "0,1,2,3", 206 "CounterHTOff": "0,1,2,3,4,5,6,7", 207 "EventCode": "0x08", 208 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 209 "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault.", 210 "SampleAfterValue": "2000003", 211 "UMask": "0x4" 212 }, 213 { 214 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 215 "Counter": "0,1,2,3", 216 "CounterHTOff": "0,1,2,3,4,5,6,7", 217 "EventCode": "0x08", 218 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 219 "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", 220 "SampleAfterValue": "100003", 221 "UMask": "0x1" 222 }, 223 { 224 "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", 225 "Counter": "0,1,2,3", 226 "CounterHTOff": "0,1,2,3,4,5,6,7", 227 "EventCode": "0x4F", 228 "EventName": "EPT.WALK_PENDING", 229 "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.", 230 "SampleAfterValue": "2000003", 231 "UMask": "0x10" 232 }, 233 { 234 "BriefDescription": "STLB flush attempts", 235 "Counter": "0,1,2,3", 236 "CounterHTOff": "0,1,2,3,4,5,6,7", 237 "EventCode": "0xBD", 238 "EventName": "TLB_FLUSH.STLB_ANY", 239 "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", 240 "SampleAfterValue": "100007", 241 "UMask": "0x20" 242 }, 243 { 244 "BriefDescription": "Page walk completed due to a demand data load to a 1G page", 245 "Counter": "0,1,2,3", 246 "CounterHTOff": "0,1,2,3,4,5,6,7", 247 "EventCode": "0x08", 248 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 249 "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", 250 "SampleAfterValue": "2000003", 251 "UMask": "0x8" 252 }, 253 { 254 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", 255 "Counter": "0,1,2,3", 256 "CounterHTOff": "0,1,2,3,4,5,6,7", 257 "CounterMask": "1", 258 "EventCode": "0x08", 259 "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", 260 "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", 261 "SampleAfterValue": "100003", 262 "UMask": "0x10" 263 }, 264 { 265 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 266 "Counter": "0,1,2,3", 267 "CounterHTOff": "0,1,2,3,4,5,6,7", 268 "EventCode": "0x85", 269 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 270 "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", 271 "SampleAfterValue": "100003", 272 "UMask": "0x4" 273 }, 274 { 275 "BriefDescription": "Page walk completed due to a demand data store to a 1G page", 276 "Counter": "0,1,2,3", 277 "CounterHTOff": "0,1,2,3,4,5,6,7", 278 "EventCode": "0x49", 279 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 280 "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages. The page walks can end with or without a page fault.", 281 "SampleAfterValue": "100003", 282 "UMask": "0x8" 283 } 284]