1[ 2 { 3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 "EventCode": "0x28", 5 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 6 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 7 "SampleAfterValue": "200003", 8 "UMask": "0x7" 9 }, 10 { 11 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 12 "EventCode": "0x28", 13 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 14 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 15 "SampleAfterValue": "200003", 16 "UMask": "0x18" 17 }, 18 { 19 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 20 "EventCode": "0x28", 21 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 22 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", 23 "SampleAfterValue": "200003", 24 "UMask": "0x20" 25 }, 26 { 27 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 28 "EventCode": "0x28", 29 "EventName": "CORE_POWER.THROTTLE", 30 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 31 "SampleAfterValue": "200003", 32 "UMask": "0x40" 33 }, 34 { 35 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 36 "EventCode": "0xEF", 37 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 38 "SampleAfterValue": "2000003", 39 "UMask": "0x20" 40 }, 41 { 42 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 43 "EventCode": "0xEF", 44 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 45 "SampleAfterValue": "2000003", 46 "UMask": "0x10" 47 }, 48 { 49 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 50 "EventCode": "0xEF", 51 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 52 "SampleAfterValue": "2000003", 53 "UMask": "0x2" 54 }, 55 { 56 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", 57 "EventCode": "0xEF", 58 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x1" 61 }, 62 { 63 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 64 "EventCode": "0xEF", 65 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 66 "SampleAfterValue": "2000003", 67 "UMask": "0x40" 68 }, 69 { 70 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 71 "EventCode": "0xEF", 72 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 73 "SampleAfterValue": "2000003", 74 "UMask": "0x8" 75 }, 76 { 77 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 78 "EventCode": "0xEF", 79 "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 80 "SampleAfterValue": "2000003", 81 "UMask": "0x4" 82 }, 83 { 84 "BriefDescription": "Number of hardware interrupts received by the processor.", 85 "EventCode": "0xCB", 86 "EventName": "HW_INTERRUPTS.RECEIVED", 87 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 88 "SampleAfterValue": "203", 89 "UMask": "0x1" 90 }, 91 { 92 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 93 "EventCode": "0xFE", 94 "EventName": "IDI_MISC.WB_DOWNGRADE", 95 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x4" 98 }, 99 { 100 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 101 "EventCode": "0xFE", 102 "EventName": "IDI_MISC.WB_UPGRADE", 103 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 104 "SampleAfterValue": "100003", 105 "UMask": "0x2" 106 }, 107 { 108 "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 109 "EventCode": "0x09", 110 "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 111 "SampleAfterValue": "2000003", 112 "UMask": "0x1" 113 } 114] 115