1[ 2 { 3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x28", 6 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 7 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 8 "SampleAfterValue": "200003", 9 "UMask": "0x7" 10 }, 11 { 12 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x28", 15 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 16 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 17 "SampleAfterValue": "200003", 18 "UMask": "0x18" 19 }, 20 { 21 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x28", 24 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 25 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", 26 "SampleAfterValue": "200003", 27 "UMask": "0x20" 28 }, 29 { 30 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x28", 33 "EventName": "CORE_POWER.THROTTLE", 34 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 35 "SampleAfterValue": "200003", 36 "UMask": "0x40" 37 }, 38 { 39 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 40 "Counter": "0,1,2,3", 41 "EventCode": "0xEF", 42 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", 43 "SampleAfterValue": "2000003", 44 "UMask": "0x20" 45 }, 46 { 47 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 48 "Counter": "0,1,2,3", 49 "EventCode": "0xEF", 50 "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", 51 "SampleAfterValue": "2000003", 52 "UMask": "0x10" 53 }, 54 { 55 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 56 "Counter": "0,1,2,3", 57 "EventCode": "0xEF", 58 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", 59 "SampleAfterValue": "2000003", 60 "UMask": "0x2" 61 }, 62 { 63 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", 64 "Counter": "0,1,2,3", 65 "EventCode": "0xEF", 66 "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", 67 "SampleAfterValue": "2000003", 68 "UMask": "0x1" 69 }, 70 { 71 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 72 "Counter": "0,1,2,3", 73 "EventCode": "0xEF", 74 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", 75 "SampleAfterValue": "2000003", 76 "UMask": "0x40" 77 }, 78 { 79 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 80 "Counter": "0,1,2,3", 81 "EventCode": "0xEF", 82 "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", 83 "SampleAfterValue": "2000003", 84 "UMask": "0x8" 85 }, 86 { 87 "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 88 "Counter": "0,1,2,3", 89 "EventCode": "0xEF", 90 "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", 91 "SampleAfterValue": "2000003", 92 "UMask": "0x4" 93 }, 94 { 95 "BriefDescription": "Number of hardware interrupts received by the processor.", 96 "Counter": "0,1,2,3", 97 "EventCode": "0xCB", 98 "EventName": "HW_INTERRUPTS.RECEIVED", 99 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 100 "SampleAfterValue": "203", 101 "UMask": "0x1" 102 }, 103 { 104 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 105 "Counter": "0,1,2,3", 106 "EventCode": "0xFE", 107 "EventName": "IDI_MISC.WB_DOWNGRADE", 108 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 109 "SampleAfterValue": "100003", 110 "UMask": "0x4" 111 }, 112 { 113 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 114 "Counter": "0,1,2,3", 115 "EventCode": "0xFE", 116 "EventName": "IDI_MISC.WB_UPGRADE", 117 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 118 "SampleAfterValue": "100003", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 123 "Counter": "0,1,2,3", 124 "EventCode": "0x09", 125 "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", 126 "SampleAfterValue": "2000003", 127 "UMask": "0x1" 128 } 129] 130