1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterMask": "2", 6 "EventCode": "0xA3", 7 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x2" 10 }, 11 { 12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 13 "Counter": "0,1,2,3", 14 "CounterMask": "6", 15 "EventCode": "0xA3", 16 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 17 "SampleAfterValue": "2000003", 18 "UMask": "0x6" 19 }, 20 { 21 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 22 "Counter": "0,1,2,3", 23 "EventCode": "0xC8", 24 "EventName": "HLE_RETIRED.ABORTED", 25 "PEBS": "1", 26 "PublicDescription": "Number of times HLE abort was triggered.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x4" 29 }, 30 { 31 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 32 "Counter": "0,1,2,3", 33 "EventCode": "0xC8", 34 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 35 "SampleAfterValue": "2000003", 36 "UMask": "0x80" 37 }, 38 { 39 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 40 "Counter": "0,1,2,3", 41 "EventCode": "0xC8", 42 "EventName": "HLE_RETIRED.ABORTED_MEM", 43 "SampleAfterValue": "2000003", 44 "UMask": "0x8" 45 }, 46 { 47 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 48 "Counter": "0,1,2,3", 49 "EventCode": "0xC8", 50 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 51 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 52 "SampleAfterValue": "2000003", 53 "UMask": "0x40" 54 }, 55 { 56 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 57 "Counter": "0,1,2,3", 58 "EventCode": "0xC8", 59 "EventName": "HLE_RETIRED.ABORTED_TIMER", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x10" 62 }, 63 { 64 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 65 "Counter": "0,1,2,3", 66 "EventCode": "0xC8", 67 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 68 "SampleAfterValue": "2000003", 69 "UMask": "0x20" 70 }, 71 { 72 "BriefDescription": "Number of times an HLE execution successfully committed", 73 "Counter": "0,1,2,3", 74 "EventCode": "0xC8", 75 "EventName": "HLE_RETIRED.COMMIT", 76 "PublicDescription": "Number of times HLE commit succeeded.", 77 "SampleAfterValue": "2000003", 78 "UMask": "0x2" 79 }, 80 { 81 "BriefDescription": "Number of times an HLE execution started.", 82 "Counter": "0,1,2,3", 83 "EventCode": "0xC8", 84 "EventName": "HLE_RETIRED.START", 85 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x1" 88 }, 89 { 90 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 91 "Counter": "0,1,2,3", 92 "Errata": "SKL089", 93 "EventCode": "0xC3", 94 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 95 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x2" 98 }, 99 { 100 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 101 "Counter": "0,1,2,3", 102 "Data_LA": "1", 103 "EventCode": "0xcd", 104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 105 "MSRIndex": "0x3F6", 106 "MSRValue": "0x80", 107 "PEBS": "2", 108 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 109 "SampleAfterValue": "1009", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 114 "Counter": "0,1,2,3", 115 "Data_LA": "1", 116 "EventCode": "0xcd", 117 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 118 "MSRIndex": "0x3F6", 119 "MSRValue": "0x10", 120 "PEBS": "2", 121 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 122 "SampleAfterValue": "20011", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 127 "Counter": "0,1,2,3", 128 "Data_LA": "1", 129 "EventCode": "0xcd", 130 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 131 "MSRIndex": "0x3F6", 132 "MSRValue": "0x100", 133 "PEBS": "2", 134 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 135 "SampleAfterValue": "503", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 140 "Counter": "0,1,2,3", 141 "Data_LA": "1", 142 "EventCode": "0xcd", 143 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 144 "MSRIndex": "0x3F6", 145 "MSRValue": "0x20", 146 "PEBS": "2", 147 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 148 "SampleAfterValue": "100007", 149 "UMask": "0x1" 150 }, 151 { 152 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 153 "Counter": "0,1,2,3", 154 "Data_LA": "1", 155 "EventCode": "0xcd", 156 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 157 "MSRIndex": "0x3F6", 158 "MSRValue": "0x4", 159 "PEBS": "2", 160 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 161 "SampleAfterValue": "100003", 162 "UMask": "0x1" 163 }, 164 { 165 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 166 "Counter": "0,1,2,3", 167 "Data_LA": "1", 168 "EventCode": "0xcd", 169 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 170 "MSRIndex": "0x3F6", 171 "MSRValue": "0x200", 172 "PEBS": "2", 173 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 174 "SampleAfterValue": "101", 175 "UMask": "0x1" 176 }, 177 { 178 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 179 "Counter": "0,1,2,3", 180 "Data_LA": "1", 181 "EventCode": "0xcd", 182 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 183 "MSRIndex": "0x3F6", 184 "MSRValue": "0x40", 185 "PEBS": "2", 186 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 187 "SampleAfterValue": "2003", 188 "UMask": "0x1" 189 }, 190 { 191 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 192 "Counter": "0,1,2,3", 193 "Data_LA": "1", 194 "EventCode": "0xcd", 195 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 196 "MSRIndex": "0x3F6", 197 "MSRValue": "0x8", 198 "PEBS": "2", 199 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 200 "SampleAfterValue": "50021", 201 "UMask": "0x1" 202 }, 203 { 204 "BriefDescription": "Demand Data Read requests who miss L3 cache", 205 "Counter": "0,1,2,3", 206 "EventCode": "0xB0", 207 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 208 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 209 "SampleAfterValue": "100003", 210 "UMask": "0x10" 211 }, 212 { 213 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 214 "Counter": "0,1,2,3", 215 "CounterMask": "1", 216 "EventCode": "0x60", 217 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 218 "SampleAfterValue": "2000003", 219 "UMask": "0x10" 220 }, 221 { 222 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 223 "Counter": "0,1,2,3", 224 "EventCode": "0x60", 225 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 226 "SampleAfterValue": "2000003", 227 "UMask": "0x10" 228 }, 229 { 230 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 231 "Counter": "0,1,2,3", 232 "CounterMask": "6", 233 "EventCode": "0x60", 234 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 235 "SampleAfterValue": "2000003", 236 "UMask": "0x10" 237 }, 238 { 239 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.", 240 "Counter": "0,1,2,3", 241 "EventCode": "0xB7, 0xBB", 242 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", 243 "MSRIndex": "0x1a6,0x1a7", 244 "MSRValue": "0x3FBC000491", 245 "SampleAfterValue": "100003", 246 "UMask": "0x1" 247 }, 248 { 249 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 250 "Counter": "0,1,2,3", 251 "EventCode": "0xB7, 0xBB", 252 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", 253 "MSRIndex": "0x1a6,0x1a7", 254 "MSRValue": "0x103FC00491", 255 "SampleAfterValue": "100003", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xB7, 0xBB", 262 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 263 "MSRIndex": "0x1a6,0x1a7", 264 "MSRValue": "0x83FC00491", 265 "SampleAfterValue": "100003", 266 "UMask": "0x1" 267 }, 268 { 269 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 270 "Counter": "0,1,2,3", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x63FC00491", 275 "SampleAfterValue": "100003", 276 "UMask": "0x1" 277 }, 278 { 279 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.", 280 "Counter": "0,1,2,3", 281 "EventCode": "0xB7, 0xBB", 282 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 283 "MSRIndex": "0x1a6,0x1a7", 284 "MSRValue": "0x604000491", 285 "SampleAfterValue": "100003", 286 "UMask": "0x1" 287 }, 288 { 289 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.", 290 "Counter": "0,1,2,3", 291 "EventCode": "0xB7, 0xBB", 292 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 293 "MSRIndex": "0x1a6,0x1a7", 294 "MSRValue": "0x63B800491", 295 "SampleAfterValue": "100003", 296 "UMask": "0x1" 297 }, 298 { 299 "BriefDescription": "Counts all prefetch data reads that miss in the L3.", 300 "Counter": "0,1,2,3", 301 "EventCode": "0xB7, 0xBB", 302 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", 303 "MSRIndex": "0x1a6,0x1a7", 304 "MSRValue": "0x3FBC000490", 305 "SampleAfterValue": "100003", 306 "UMask": "0x1" 307 }, 308 { 309 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.", 310 "Counter": "0,1,2,3", 311 "EventCode": "0xB7, 0xBB", 312 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", 313 "MSRIndex": "0x1a6,0x1a7", 314 "MSRValue": "0x103FC00490", 315 "SampleAfterValue": "100003", 316 "UMask": "0x1" 317 }, 318 { 319 "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.", 320 "Counter": "0,1,2,3", 321 "EventCode": "0xB7, 0xBB", 322 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 323 "MSRIndex": "0x1a6,0x1a7", 324 "MSRValue": "0x83FC00490", 325 "SampleAfterValue": "100003", 326 "UMask": "0x1" 327 }, 328 { 329 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.", 330 "Counter": "0,1,2,3", 331 "EventCode": "0xB7, 0xBB", 332 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 333 "MSRIndex": "0x1a6,0x1a7", 334 "MSRValue": "0x63FC00490", 335 "SampleAfterValue": "100003", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xB7, 0xBB", 342 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 343 "MSRIndex": "0x1a6,0x1a7", 344 "MSRValue": "0x604000490", 345 "SampleAfterValue": "100003", 346 "UMask": "0x1" 347 }, 348 { 349 "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.", 350 "Counter": "0,1,2,3", 351 "EventCode": "0xB7, 0xBB", 352 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 353 "MSRIndex": "0x1a6,0x1a7", 354 "MSRValue": "0x63B800490", 355 "SampleAfterValue": "100003", 356 "UMask": "0x1" 357 }, 358 { 359 "BriefDescription": "Counts prefetch RFOs that miss in the L3.", 360 "Counter": "0,1,2,3", 361 "EventCode": "0xB7, 0xBB", 362 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", 363 "MSRIndex": "0x1a6,0x1a7", 364 "MSRValue": "0x3FBC000120", 365 "SampleAfterValue": "100003", 366 "UMask": "0x1" 367 }, 368 { 369 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 370 "Counter": "0,1,2,3", 371 "EventCode": "0xB7, 0xBB", 372 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", 373 "MSRIndex": "0x1a6,0x1a7", 374 "MSRValue": "0x103FC00120", 375 "SampleAfterValue": "100003", 376 "UMask": "0x1" 377 }, 378 { 379 "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xB7, 0xBB", 382 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", 383 "MSRIndex": "0x1a6,0x1a7", 384 "MSRValue": "0x83FC00120", 385 "SampleAfterValue": "100003", 386 "UMask": "0x1" 387 }, 388 { 389 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 390 "Counter": "0,1,2,3", 391 "EventCode": "0xB7, 0xBB", 392 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 393 "MSRIndex": "0x1a6,0x1a7", 394 "MSRValue": "0x63FC00120", 395 "SampleAfterValue": "100003", 396 "UMask": "0x1" 397 }, 398 { 399 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.", 400 "Counter": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x604000120", 405 "SampleAfterValue": "100003", 406 "UMask": "0x1" 407 }, 408 { 409 "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.", 410 "Counter": "0,1,2,3", 411 "EventCode": "0xB7, 0xBB", 412 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 413 "MSRIndex": "0x1a6,0x1a7", 414 "MSRValue": "0x63B800120", 415 "SampleAfterValue": "100003", 416 "UMask": "0x1" 417 }, 418 { 419 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xB7, 0xBB", 422 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", 423 "MSRIndex": "0x1a6,0x1a7", 424 "MSRValue": "0x3FBC000122", 425 "SampleAfterValue": "100003", 426 "UMask": "0x1" 427 }, 428 { 429 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.", 430 "Counter": "0,1,2,3", 431 "EventCode": "0xB7, 0xBB", 432 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", 433 "MSRIndex": "0x1a6,0x1a7", 434 "MSRValue": "0x103FC00122", 435 "SampleAfterValue": "100003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 440 "Counter": "0,1,2,3", 441 "EventCode": "0xB7, 0xBB", 442 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", 443 "MSRIndex": "0x1a6,0x1a7", 444 "MSRValue": "0x83FC00122", 445 "SampleAfterValue": "100003", 446 "UMask": "0x1" 447 }, 448 { 449 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.", 450 "Counter": "0,1,2,3", 451 "EventCode": "0xB7, 0xBB", 452 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 453 "MSRIndex": "0x1a6,0x1a7", 454 "MSRValue": "0x63FC00122", 455 "SampleAfterValue": "100003", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xB7, 0xBB", 462 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 463 "MSRIndex": "0x1a6,0x1a7", 464 "MSRValue": "0x604000122", 465 "SampleAfterValue": "100003", 466 "UMask": "0x1" 467 }, 468 { 469 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.", 470 "Counter": "0,1,2,3", 471 "EventCode": "0xB7, 0xBB", 472 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 473 "MSRIndex": "0x1a6,0x1a7", 474 "MSRValue": "0x63B800122", 475 "SampleAfterValue": "100003", 476 "UMask": "0x1" 477 }, 478 { 479 "BriefDescription": "Counts all demand code reads that miss in the L3.", 480 "Counter": "0,1,2,3", 481 "EventCode": "0xB7, 0xBB", 482 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 483 "MSRIndex": "0x1a6,0x1a7", 484 "MSRValue": "0x3FBC000004", 485 "SampleAfterValue": "100003", 486 "UMask": "0x1" 487 }, 488 { 489 "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.", 490 "Counter": "0,1,2,3", 491 "EventCode": "0xB7, 0xBB", 492 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", 493 "MSRIndex": "0x1a6,0x1a7", 494 "MSRValue": "0x103FC00004", 495 "SampleAfterValue": "100003", 496 "UMask": "0x1" 497 }, 498 { 499 "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.", 500 "Counter": "0,1,2,3", 501 "EventCode": "0xB7, 0xBB", 502 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", 503 "MSRIndex": "0x1a6,0x1a7", 504 "MSRValue": "0x83FC00004", 505 "SampleAfterValue": "100003", 506 "UMask": "0x1" 507 }, 508 { 509 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.", 510 "Counter": "0,1,2,3", 511 "EventCode": "0xB7, 0xBB", 512 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 513 "MSRIndex": "0x1a6,0x1a7", 514 "MSRValue": "0x63FC00004", 515 "SampleAfterValue": "100003", 516 "UMask": "0x1" 517 }, 518 { 519 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.", 520 "Counter": "0,1,2,3", 521 "EventCode": "0xB7, 0xBB", 522 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 523 "MSRIndex": "0x1a6,0x1a7", 524 "MSRValue": "0x604000004", 525 "SampleAfterValue": "100003", 526 "UMask": "0x1" 527 }, 528 { 529 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.", 530 "Counter": "0,1,2,3", 531 "EventCode": "0xB7, 0xBB", 532 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 533 "MSRIndex": "0x1a6,0x1a7", 534 "MSRValue": "0x63B800004", 535 "SampleAfterValue": "100003", 536 "UMask": "0x1" 537 }, 538 { 539 "BriefDescription": "Counts demand data reads that miss in the L3.", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xB7, 0xBB", 542 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 543 "MSRIndex": "0x1a6,0x1a7", 544 "MSRValue": "0x3FBC000001", 545 "SampleAfterValue": "100003", 546 "UMask": "0x1" 547 }, 548 { 549 "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.", 550 "Counter": "0,1,2,3", 551 "EventCode": "0xB7, 0xBB", 552 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", 553 "MSRIndex": "0x1a6,0x1a7", 554 "MSRValue": "0x103FC00001", 555 "SampleAfterValue": "100003", 556 "UMask": "0x1" 557 }, 558 { 559 "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.", 560 "Counter": "0,1,2,3", 561 "EventCode": "0xB7, 0xBB", 562 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 563 "MSRIndex": "0x1a6,0x1a7", 564 "MSRValue": "0x83FC00001", 565 "SampleAfterValue": "100003", 566 "UMask": "0x1" 567 }, 568 { 569 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.", 570 "Counter": "0,1,2,3", 571 "EventCode": "0xB7, 0xBB", 572 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 573 "MSRIndex": "0x1a6,0x1a7", 574 "MSRValue": "0x63FC00001", 575 "SampleAfterValue": "100003", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.", 580 "Counter": "0,1,2,3", 581 "EventCode": "0xB7, 0xBB", 582 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 583 "MSRIndex": "0x1a6,0x1a7", 584 "MSRValue": "0x604000001", 585 "SampleAfterValue": "100003", 586 "UMask": "0x1" 587 }, 588 { 589 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.", 590 "Counter": "0,1,2,3", 591 "EventCode": "0xB7, 0xBB", 592 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 593 "MSRIndex": "0x1a6,0x1a7", 594 "MSRValue": "0x63B800001", 595 "SampleAfterValue": "100003", 596 "UMask": "0x1" 597 }, 598 { 599 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.", 600 "Counter": "0,1,2,3", 601 "EventCode": "0xB7, 0xBB", 602 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", 603 "MSRIndex": "0x1a6,0x1a7", 604 "MSRValue": "0x3FBC000002", 605 "SampleAfterValue": "100003", 606 "UMask": "0x1" 607 }, 608 { 609 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.", 610 "Counter": "0,1,2,3", 611 "EventCode": "0xB7, 0xBB", 612 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", 613 "MSRIndex": "0x1a6,0x1a7", 614 "MSRValue": "0x103FC00002", 615 "SampleAfterValue": "100003", 616 "UMask": "0x1" 617 }, 618 { 619 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.", 620 "Counter": "0,1,2,3", 621 "EventCode": "0xB7, 0xBB", 622 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", 623 "MSRIndex": "0x1a6,0x1a7", 624 "MSRValue": "0x83FC00002", 625 "SampleAfterValue": "100003", 626 "UMask": "0x1" 627 }, 628 { 629 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.", 630 "Counter": "0,1,2,3", 631 "EventCode": "0xB7, 0xBB", 632 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 633 "MSRIndex": "0x1a6,0x1a7", 634 "MSRValue": "0x63FC00002", 635 "SampleAfterValue": "100003", 636 "UMask": "0x1" 637 }, 638 { 639 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.", 640 "Counter": "0,1,2,3", 641 "EventCode": "0xB7, 0xBB", 642 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 643 "MSRIndex": "0x1a6,0x1a7", 644 "MSRValue": "0x604000002", 645 "SampleAfterValue": "100003", 646 "UMask": "0x1" 647 }, 648 { 649 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.", 650 "Counter": "0,1,2,3", 651 "EventCode": "0xB7, 0xBB", 652 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 653 "MSRIndex": "0x1a6,0x1a7", 654 "MSRValue": "0x63B800002", 655 "SampleAfterValue": "100003", 656 "UMask": "0x1" 657 }, 658 { 659 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.", 660 "Counter": "0,1,2,3", 661 "EventCode": "0xB7, 0xBB", 662 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", 663 "MSRIndex": "0x1a6,0x1a7", 664 "MSRValue": "0x3FBC000400", 665 "SampleAfterValue": "100003", 666 "UMask": "0x1" 667 }, 668 { 669 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.", 670 "Counter": "0,1,2,3", 671 "EventCode": "0xB7, 0xBB", 672 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", 673 "MSRIndex": "0x1a6,0x1a7", 674 "MSRValue": "0x103FC00400", 675 "SampleAfterValue": "100003", 676 "UMask": "0x1" 677 }, 678 { 679 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.", 680 "Counter": "0,1,2,3", 681 "EventCode": "0xB7, 0xBB", 682 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", 683 "MSRIndex": "0x1a6,0x1a7", 684 "MSRValue": "0x83FC00400", 685 "SampleAfterValue": "100003", 686 "UMask": "0x1" 687 }, 688 { 689 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.", 690 "Counter": "0,1,2,3", 691 "EventCode": "0xB7, 0xBB", 692 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", 693 "MSRIndex": "0x1a6,0x1a7", 694 "MSRValue": "0x63FC00400", 695 "SampleAfterValue": "100003", 696 "UMask": "0x1" 697 }, 698 { 699 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.", 700 "Counter": "0,1,2,3", 701 "EventCode": "0xB7, 0xBB", 702 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 703 "MSRIndex": "0x1a6,0x1a7", 704 "MSRValue": "0x604000400", 705 "SampleAfterValue": "100003", 706 "UMask": "0x1" 707 }, 708 { 709 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.", 710 "Counter": "0,1,2,3", 711 "EventCode": "0xB7, 0xBB", 712 "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 713 "MSRIndex": "0x1a6,0x1a7", 714 "MSRValue": "0x63B800400", 715 "SampleAfterValue": "100003", 716 "UMask": "0x1" 717 }, 718 { 719 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.", 720 "Counter": "0,1,2,3", 721 "EventCode": "0xB7, 0xBB", 722 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", 723 "MSRIndex": "0x1a6,0x1a7", 724 "MSRValue": "0x3FBC000010", 725 "SampleAfterValue": "100003", 726 "UMask": "0x1" 727 }, 728 { 729 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.", 730 "Counter": "0,1,2,3", 731 "EventCode": "0xB7, 0xBB", 732 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", 733 "MSRIndex": "0x1a6,0x1a7", 734 "MSRValue": "0x103FC00010", 735 "SampleAfterValue": "100003", 736 "UMask": "0x1" 737 }, 738 { 739 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 740 "Counter": "0,1,2,3", 741 "EventCode": "0xB7, 0xBB", 742 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 743 "MSRIndex": "0x1a6,0x1a7", 744 "MSRValue": "0x83FC00010", 745 "SampleAfterValue": "100003", 746 "UMask": "0x1" 747 }, 748 { 749 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.", 750 "Counter": "0,1,2,3", 751 "EventCode": "0xB7, 0xBB", 752 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 753 "MSRIndex": "0x1a6,0x1a7", 754 "MSRValue": "0x63FC00010", 755 "SampleAfterValue": "100003", 756 "UMask": "0x1" 757 }, 758 { 759 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.", 760 "Counter": "0,1,2,3", 761 "EventCode": "0xB7, 0xBB", 762 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 763 "MSRIndex": "0x1a6,0x1a7", 764 "MSRValue": "0x604000010", 765 "SampleAfterValue": "100003", 766 "UMask": "0x1" 767 }, 768 { 769 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.", 770 "Counter": "0,1,2,3", 771 "EventCode": "0xB7, 0xBB", 772 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 773 "MSRIndex": "0x1a6,0x1a7", 774 "MSRValue": "0x63B800010", 775 "SampleAfterValue": "100003", 776 "UMask": "0x1" 777 }, 778 { 779 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.", 780 "Counter": "0,1,2,3", 781 "EventCode": "0xB7, 0xBB", 782 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", 783 "MSRIndex": "0x1a6,0x1a7", 784 "MSRValue": "0x3FBC000020", 785 "SampleAfterValue": "100003", 786 "UMask": "0x1" 787 }, 788 { 789 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.", 790 "Counter": "0,1,2,3", 791 "EventCode": "0xB7, 0xBB", 792 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", 793 "MSRIndex": "0x1a6,0x1a7", 794 "MSRValue": "0x103FC00020", 795 "SampleAfterValue": "100003", 796 "UMask": "0x1" 797 }, 798 { 799 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 800 "Counter": "0,1,2,3", 801 "EventCode": "0xB7, 0xBB", 802 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", 803 "MSRIndex": "0x1a6,0x1a7", 804 "MSRValue": "0x83FC00020", 805 "SampleAfterValue": "100003", 806 "UMask": "0x1" 807 }, 808 { 809 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.", 810 "Counter": "0,1,2,3", 811 "EventCode": "0xB7, 0xBB", 812 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 813 "MSRIndex": "0x1a6,0x1a7", 814 "MSRValue": "0x63FC00020", 815 "SampleAfterValue": "100003", 816 "UMask": "0x1" 817 }, 818 { 819 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.", 820 "Counter": "0,1,2,3", 821 "EventCode": "0xB7, 0xBB", 822 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 823 "MSRIndex": "0x1a6,0x1a7", 824 "MSRValue": "0x604000020", 825 "SampleAfterValue": "100003", 826 "UMask": "0x1" 827 }, 828 { 829 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.", 830 "Counter": "0,1,2,3", 831 "EventCode": "0xB7, 0xBB", 832 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 833 "MSRIndex": "0x1a6,0x1a7", 834 "MSRValue": "0x63B800020", 835 "SampleAfterValue": "100003", 836 "UMask": "0x1" 837 }, 838 { 839 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.", 840 "Counter": "0,1,2,3", 841 "EventCode": "0xB7, 0xBB", 842 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", 843 "MSRIndex": "0x1a6,0x1a7", 844 "MSRValue": "0x3FBC000080", 845 "SampleAfterValue": "100003", 846 "UMask": "0x1" 847 }, 848 { 849 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.", 850 "Counter": "0,1,2,3", 851 "EventCode": "0xB7, 0xBB", 852 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", 853 "MSRIndex": "0x1a6,0x1a7", 854 "MSRValue": "0x103FC00080", 855 "SampleAfterValue": "100003", 856 "UMask": "0x1" 857 }, 858 { 859 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.", 860 "Counter": "0,1,2,3", 861 "EventCode": "0xB7, 0xBB", 862 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", 863 "MSRIndex": "0x1a6,0x1a7", 864 "MSRValue": "0x83FC00080", 865 "SampleAfterValue": "100003", 866 "UMask": "0x1" 867 }, 868 { 869 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.", 870 "Counter": "0,1,2,3", 871 "EventCode": "0xB7, 0xBB", 872 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", 873 "MSRIndex": "0x1a6,0x1a7", 874 "MSRValue": "0x63FC00080", 875 "SampleAfterValue": "100003", 876 "UMask": "0x1" 877 }, 878 { 879 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.", 880 "Counter": "0,1,2,3", 881 "EventCode": "0xB7, 0xBB", 882 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 883 "MSRIndex": "0x1a6,0x1a7", 884 "MSRValue": "0x604000080", 885 "SampleAfterValue": "100003", 886 "UMask": "0x1" 887 }, 888 { 889 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.", 890 "Counter": "0,1,2,3", 891 "EventCode": "0xB7, 0xBB", 892 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 893 "MSRIndex": "0x1a6,0x1a7", 894 "MSRValue": "0x63B800080", 895 "SampleAfterValue": "100003", 896 "UMask": "0x1" 897 }, 898 { 899 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.", 900 "Counter": "0,1,2,3", 901 "EventCode": "0xB7, 0xBB", 902 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", 903 "MSRIndex": "0x1a6,0x1a7", 904 "MSRValue": "0x3FBC000100", 905 "SampleAfterValue": "100003", 906 "UMask": "0x1" 907 }, 908 { 909 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.", 910 "Counter": "0,1,2,3", 911 "EventCode": "0xB7, 0xBB", 912 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", 913 "MSRIndex": "0x1a6,0x1a7", 914 "MSRValue": "0x103FC00100", 915 "SampleAfterValue": "100003", 916 "UMask": "0x1" 917 }, 918 { 919 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.", 920 "Counter": "0,1,2,3", 921 "EventCode": "0xB7, 0xBB", 922 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", 923 "MSRIndex": "0x1a6,0x1a7", 924 "MSRValue": "0x83FC00100", 925 "SampleAfterValue": "100003", 926 "UMask": "0x1" 927 }, 928 { 929 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.", 930 "Counter": "0,1,2,3", 931 "EventCode": "0xB7, 0xBB", 932 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", 933 "MSRIndex": "0x1a6,0x1a7", 934 "MSRValue": "0x63FC00100", 935 "SampleAfterValue": "100003", 936 "UMask": "0x1" 937 }, 938 { 939 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.", 940 "Counter": "0,1,2,3", 941 "EventCode": "0xB7, 0xBB", 942 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", 943 "MSRIndex": "0x1a6,0x1a7", 944 "MSRValue": "0x604000100", 945 "SampleAfterValue": "100003", 946 "UMask": "0x1" 947 }, 948 { 949 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.", 950 "Counter": "0,1,2,3", 951 "EventCode": "0xB7, 0xBB", 952 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", 953 "MSRIndex": "0x1a6,0x1a7", 954 "MSRValue": "0x63B800100", 955 "SampleAfterValue": "100003", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 960 "Counter": "0,1,2,3", 961 "EventCode": "0xC9", 962 "EventName": "RTM_RETIRED.ABORTED", 963 "PEBS": "2", 964 "PublicDescription": "Number of times RTM abort was triggered.", 965 "SampleAfterValue": "2000003", 966 "UMask": "0x4" 967 }, 968 { 969 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 970 "Counter": "0,1,2,3", 971 "EventCode": "0xC9", 972 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 973 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 974 "SampleAfterValue": "2000003", 975 "UMask": "0x80" 976 }, 977 { 978 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 979 "Counter": "0,1,2,3", 980 "EventCode": "0xC9", 981 "EventName": "RTM_RETIRED.ABORTED_MEM", 982 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 983 "SampleAfterValue": "2000003", 984 "UMask": "0x8" 985 }, 986 { 987 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 988 "Counter": "0,1,2,3", 989 "EventCode": "0xC9", 990 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 991 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 992 "SampleAfterValue": "2000003", 993 "UMask": "0x40" 994 }, 995 { 996 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 997 "Counter": "0,1,2,3", 998 "EventCode": "0xC9", 999 "EventName": "RTM_RETIRED.ABORTED_TIMER", 1000 "SampleAfterValue": "2000003", 1001 "UMask": "0x10" 1002 }, 1003 { 1004 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 1005 "Counter": "0,1,2,3", 1006 "EventCode": "0xC9", 1007 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1008 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1009 "SampleAfterValue": "2000003", 1010 "UMask": "0x20" 1011 }, 1012 { 1013 "BriefDescription": "Number of times an RTM execution successfully committed", 1014 "Counter": "0,1,2,3", 1015 "EventCode": "0xC9", 1016 "EventName": "RTM_RETIRED.COMMIT", 1017 "PublicDescription": "Number of times RTM commit succeeded.", 1018 "SampleAfterValue": "2000003", 1019 "UMask": "0x2" 1020 }, 1021 { 1022 "BriefDescription": "Number of times an RTM execution started.", 1023 "Counter": "0,1,2,3", 1024 "EventCode": "0xC9", 1025 "EventName": "RTM_RETIRED.START", 1026 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1027 "SampleAfterValue": "2000003", 1028 "UMask": "0x1" 1029 }, 1030 { 1031 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1032 "Counter": "0,1,2,3", 1033 "EventCode": "0x5d", 1034 "EventName": "TX_EXEC.MISC1", 1035 "SampleAfterValue": "2000003", 1036 "UMask": "0x1" 1037 }, 1038 { 1039 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1040 "Counter": "0,1,2,3", 1041 "EventCode": "0x5d", 1042 "EventName": "TX_EXEC.MISC2", 1043 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 1044 "SampleAfterValue": "2000003", 1045 "UMask": "0x2" 1046 }, 1047 { 1048 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 1049 "Counter": "0,1,2,3", 1050 "EventCode": "0x5d", 1051 "EventName": "TX_EXEC.MISC3", 1052 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 1053 "SampleAfterValue": "2000003", 1054 "UMask": "0x4" 1055 }, 1056 { 1057 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 1058 "Counter": "0,1,2,3", 1059 "EventCode": "0x5d", 1060 "EventName": "TX_EXEC.MISC4", 1061 "PublicDescription": "RTM region detected inside HLE.", 1062 "SampleAfterValue": "2000003", 1063 "UMask": "0x8" 1064 }, 1065 { 1066 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 1067 "Counter": "0,1,2,3", 1068 "EventCode": "0x5d", 1069 "EventName": "TX_EXEC.MISC5", 1070 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 1071 "SampleAfterValue": "2000003", 1072 "UMask": "0x10" 1073 }, 1074 { 1075 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1076 "Counter": "0,1,2,3", 1077 "EventCode": "0x54", 1078 "EventName": "TX_MEM.ABORT_CAPACITY", 1079 "SampleAfterValue": "2000003", 1080 "UMask": "0x2" 1081 }, 1082 { 1083 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 1084 "Counter": "0,1,2,3", 1085 "EventCode": "0x54", 1086 "EventName": "TX_MEM.ABORT_CONFLICT", 1087 "PublicDescription": "Number of times a TSX line had a cache conflict.", 1088 "SampleAfterValue": "2000003", 1089 "UMask": "0x1" 1090 }, 1091 { 1092 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1093 "Counter": "0,1,2,3", 1094 "EventCode": "0x54", 1095 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1096 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1097 "SampleAfterValue": "2000003", 1098 "UMask": "0x10" 1099 }, 1100 { 1101 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 1102 "Counter": "0,1,2,3", 1103 "EventCode": "0x54", 1104 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 1105 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 1106 "SampleAfterValue": "2000003", 1107 "UMask": "0x8" 1108 }, 1109 { 1110 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1111 "Counter": "0,1,2,3", 1112 "EventCode": "0x54", 1113 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1114 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1115 "SampleAfterValue": "2000003", 1116 "UMask": "0x20" 1117 }, 1118 { 1119 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1120 "Counter": "0,1,2,3", 1121 "EventCode": "0x54", 1122 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1123 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1124 "SampleAfterValue": "2000003", 1125 "UMask": "0x4" 1126 }, 1127 { 1128 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1129 "Counter": "0,1,2,3", 1130 "EventCode": "0x54", 1131 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1132 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1133 "SampleAfterValue": "2000003", 1134 "UMask": "0x40" 1135 } 1136] 1137