1[ 2 { 3 "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterMask": "2", 6 "EventCode": "0xA3", 7 "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x2" 10 }, 11 { 12 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 13 "Counter": "0,1,2,3", 14 "CounterMask": "6", 15 "EventCode": "0xA3", 16 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 17 "SampleAfterValue": "2000003", 18 "UMask": "0x6" 19 }, 20 { 21 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 22 "Counter": "0,1,2,3", 23 "EventCode": "0xC8", 24 "EventName": "HLE_RETIRED.ABORTED", 25 "PEBS": "1", 26 "PublicDescription": "Number of times HLE abort was triggered.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x4" 29 }, 30 { 31 "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 32 "Counter": "0,1,2,3", 33 "EventCode": "0xC8", 34 "EventName": "HLE_RETIRED.ABORTED_EVENTS", 35 "SampleAfterValue": "2000003", 36 "UMask": "0x80" 37 }, 38 { 39 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 40 "Counter": "0,1,2,3", 41 "EventCode": "0xC8", 42 "EventName": "HLE_RETIRED.ABORTED_MEM", 43 "SampleAfterValue": "2000003", 44 "UMask": "0x8" 45 }, 46 { 47 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 48 "Counter": "0,1,2,3", 49 "EventCode": "0xC8", 50 "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", 51 "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 52 "SampleAfterValue": "2000003", 53 "UMask": "0x40" 54 }, 55 { 56 "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", 57 "Counter": "0,1,2,3", 58 "EventCode": "0xC8", 59 "EventName": "HLE_RETIRED.ABORTED_TIMER", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x10" 62 }, 63 { 64 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 65 "Counter": "0,1,2,3", 66 "EventCode": "0xC8", 67 "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 68 "SampleAfterValue": "2000003", 69 "UMask": "0x20" 70 }, 71 { 72 "BriefDescription": "Number of times an HLE execution successfully committed", 73 "Counter": "0,1,2,3", 74 "EventCode": "0xC8", 75 "EventName": "HLE_RETIRED.COMMIT", 76 "PublicDescription": "Number of times HLE commit succeeded.", 77 "SampleAfterValue": "2000003", 78 "UMask": "0x2" 79 }, 80 { 81 "BriefDescription": "Number of times an HLE execution started.", 82 "Counter": "0,1,2,3", 83 "EventCode": "0xC8", 84 "EventName": "HLE_RETIRED.START", 85 "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", 86 "SampleAfterValue": "2000003", 87 "UMask": "0x1" 88 }, 89 { 90 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 91 "Counter": "0,1,2,3", 92 "Errata": "SKL089", 93 "EventCode": "0xC3", 94 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 95 "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x2" 98 }, 99 { 100 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 101 "Counter": "0,1,2,3", 102 "Data_LA": "1", 103 "EventCode": "0xcd", 104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 105 "MSRIndex": "0x3F6", 106 "MSRValue": "0x80", 107 "PEBS": "2", 108 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 109 "SampleAfterValue": "1009", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 114 "Counter": "0,1,2,3", 115 "Data_LA": "1", 116 "EventCode": "0xcd", 117 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 118 "MSRIndex": "0x3F6", 119 "MSRValue": "0x10", 120 "PEBS": "2", 121 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 122 "SampleAfterValue": "20011", 123 "UMask": "0x1" 124 }, 125 { 126 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 127 "Counter": "0,1,2,3", 128 "Data_LA": "1", 129 "EventCode": "0xcd", 130 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 131 "MSRIndex": "0x3F6", 132 "MSRValue": "0x100", 133 "PEBS": "2", 134 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 135 "SampleAfterValue": "503", 136 "UMask": "0x1" 137 }, 138 { 139 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 140 "Counter": "0,1,2,3", 141 "Data_LA": "1", 142 "EventCode": "0xcd", 143 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 144 "MSRIndex": "0x3F6", 145 "MSRValue": "0x20", 146 "PEBS": "2", 147 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 148 "SampleAfterValue": "100007", 149 "UMask": "0x1" 150 }, 151 { 152 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 153 "Counter": "0,1,2,3", 154 "Data_LA": "1", 155 "EventCode": "0xcd", 156 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 157 "MSRIndex": "0x3F6", 158 "MSRValue": "0x4", 159 "PEBS": "2", 160 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 161 "SampleAfterValue": "100003", 162 "UMask": "0x1" 163 }, 164 { 165 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 166 "Counter": "0,1,2,3", 167 "Data_LA": "1", 168 "EventCode": "0xcd", 169 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 170 "MSRIndex": "0x3F6", 171 "MSRValue": "0x200", 172 "PEBS": "2", 173 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 174 "SampleAfterValue": "101", 175 "UMask": "0x1" 176 }, 177 { 178 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 179 "Counter": "0,1,2,3", 180 "Data_LA": "1", 181 "EventCode": "0xcd", 182 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 183 "MSRIndex": "0x3F6", 184 "MSRValue": "0x40", 185 "PEBS": "2", 186 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 187 "SampleAfterValue": "2003", 188 "UMask": "0x1" 189 }, 190 { 191 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 192 "Counter": "0,1,2,3", 193 "Data_LA": "1", 194 "EventCode": "0xcd", 195 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 196 "MSRIndex": "0x3F6", 197 "MSRValue": "0x8", 198 "PEBS": "2", 199 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 200 "SampleAfterValue": "50021", 201 "UMask": "0x1" 202 }, 203 { 204 "BriefDescription": "Demand Data Read requests who miss L3 cache", 205 "Counter": "0,1,2,3", 206 "EventCode": "0xB0", 207 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 208 "PublicDescription": "Demand Data Read requests who miss L3 cache.", 209 "SampleAfterValue": "100003", 210 "UMask": "0x10" 211 }, 212 { 213 "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", 214 "Counter": "0,1,2,3", 215 "CounterMask": "1", 216 "EventCode": "0x60", 217 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 218 "SampleAfterValue": "2000003", 219 "UMask": "0x10" 220 }, 221 { 222 "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", 223 "Counter": "0,1,2,3", 224 "EventCode": "0x60", 225 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 226 "SampleAfterValue": "2000003", 227 "UMask": "0x10" 228 }, 229 { 230 "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", 231 "Counter": "0,1,2,3", 232 "CounterMask": "6", 233 "EventCode": "0x60", 234 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", 235 "SampleAfterValue": "2000003", 236 "UMask": "0x10" 237 }, 238 { 239 "BriefDescription": "Counts all demand code reads", 240 "Counter": "0,1,2,3", 241 "EventCode": "0xB7, 0xBB", 242 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", 243 "MSRIndex": "0x1a6,0x1a7", 244 "MSRValue": "0x20001C0004", 245 "SampleAfterValue": "100003", 246 "UMask": "0x1" 247 }, 248 { 249 "BriefDescription": "Counts all demand code reads", 250 "Counter": "0,1,2,3", 251 "EventCode": "0xB7, 0xBB", 252 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", 253 "MSRIndex": "0x1a6,0x1a7", 254 "MSRValue": "0x2000080004", 255 "SampleAfterValue": "100003", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "Counts all demand code reads", 260 "Counter": "0,1,2,3", 261 "EventCode": "0xB7, 0xBB", 262 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", 263 "MSRIndex": "0x1a6,0x1a7", 264 "MSRValue": "0x2000040004", 265 "SampleAfterValue": "100003", 266 "UMask": "0x1" 267 }, 268 { 269 "BriefDescription": "Counts all demand code reads", 270 "Counter": "0,1,2,3", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x2000100004", 275 "SampleAfterValue": "100003", 276 "UMask": "0x1" 277 }, 278 { 279 "BriefDescription": "Counts all demand code reads", 280 "Counter": "0,1,2,3", 281 "EventCode": "0xB7, 0xBB", 282 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", 283 "MSRIndex": "0x1a6,0x1a7", 284 "MSRValue": "0x3FFC400004", 285 "SampleAfterValue": "100003", 286 "UMask": "0x1" 287 }, 288 { 289 "BriefDescription": "Counts all demand code reads", 290 "Counter": "0,1,2,3", 291 "EventCode": "0xB7, 0xBB", 292 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", 293 "MSRIndex": "0x1a6,0x1a7", 294 "MSRValue": "0x103C400004", 295 "SampleAfterValue": "100003", 296 "UMask": "0x1" 297 }, 298 { 299 "BriefDescription": "Counts all demand code reads", 300 "Counter": "0,1,2,3", 301 "EventCode": "0xB7, 0xBB", 302 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", 303 "MSRIndex": "0x1a6,0x1a7", 304 "MSRValue": "0x43C400004", 305 "SampleAfterValue": "100003", 306 "UMask": "0x1" 307 }, 308 { 309 "BriefDescription": "Counts all demand code reads", 310 "Counter": "0,1,2,3", 311 "EventCode": "0xB7, 0xBB", 312 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", 313 "MSRIndex": "0x1a6,0x1a7", 314 "MSRValue": "0x23C400004", 315 "SampleAfterValue": "100003", 316 "UMask": "0x1" 317 }, 318 { 319 "BriefDescription": "Counts all demand code reads", 320 "Counter": "0,1,2,3", 321 "EventCode": "0xB7, 0xBB", 322 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", 323 "MSRIndex": "0x1a6,0x1a7", 324 "MSRValue": "0xBC400004", 325 "SampleAfterValue": "100003", 326 "UMask": "0x1" 327 }, 328 { 329 "BriefDescription": "Counts all demand code reads", 330 "Counter": "0,1,2,3", 331 "EventCode": "0xB7, 0xBB", 332 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", 333 "MSRIndex": "0x1a6,0x1a7", 334 "MSRValue": "0x203C400004", 335 "SampleAfterValue": "100003", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "Counts all demand code reads", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xB7, 0xBB", 342 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", 343 "MSRIndex": "0x1a6,0x1a7", 344 "MSRValue": "0x13C400004", 345 "SampleAfterValue": "100003", 346 "UMask": "0x1" 347 }, 348 { 349 "BriefDescription": "Counts all demand code reads", 350 "Counter": "0,1,2,3", 351 "EventCode": "0xB7, 0xBB", 352 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", 353 "MSRIndex": "0x1a6,0x1a7", 354 "MSRValue": "0x7C400004", 355 "SampleAfterValue": "100003", 356 "UMask": "0x1" 357 }, 358 { 359 "BriefDescription": "Counts all demand code reads", 360 "Counter": "0,1,2,3", 361 "EventCode": "0xB7, 0xBB", 362 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 363 "MSRIndex": "0x1a6,0x1a7", 364 "MSRValue": "0x3FC4000004", 365 "SampleAfterValue": "100003", 366 "UMask": "0x1" 367 }, 368 { 369 "BriefDescription": "Counts all demand code reads", 370 "Counter": "0,1,2,3", 371 "EventCode": "0xB7, 0xBB", 372 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 373 "MSRIndex": "0x1a6,0x1a7", 374 "MSRValue": "0x1004000004", 375 "SampleAfterValue": "100003", 376 "UMask": "0x1" 377 }, 378 { 379 "BriefDescription": "Counts all demand code reads", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xB7, 0xBB", 382 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 383 "MSRIndex": "0x1a6,0x1a7", 384 "MSRValue": "0x404000004", 385 "SampleAfterValue": "100003", 386 "UMask": "0x1" 387 }, 388 { 389 "BriefDescription": "Counts all demand code reads", 390 "Counter": "0,1,2,3", 391 "EventCode": "0xB7, 0xBB", 392 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 393 "MSRIndex": "0x1a6,0x1a7", 394 "MSRValue": "0x204000004", 395 "SampleAfterValue": "100003", 396 "UMask": "0x1" 397 }, 398 { 399 "BriefDescription": "Counts all demand code reads", 400 "Counter": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x84000004", 405 "SampleAfterValue": "100003", 406 "UMask": "0x1" 407 }, 408 { 409 "BriefDescription": "Counts all demand code reads", 410 "Counter": "0,1,2,3", 411 "EventCode": "0xB7, 0xBB", 412 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 413 "MSRIndex": "0x1a6,0x1a7", 414 "MSRValue": "0x2004000004", 415 "SampleAfterValue": "100003", 416 "UMask": "0x1" 417 }, 418 { 419 "BriefDescription": "Counts all demand code reads", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xB7, 0xBB", 422 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 423 "MSRIndex": "0x1a6,0x1a7", 424 "MSRValue": "0x104000004", 425 "SampleAfterValue": "100003", 426 "UMask": "0x1" 427 }, 428 { 429 "BriefDescription": "Counts all demand code reads", 430 "Counter": "0,1,2,3", 431 "EventCode": "0xB7, 0xBB", 432 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", 433 "MSRIndex": "0x1a6,0x1a7", 434 "MSRValue": "0x44000004", 435 "SampleAfterValue": "100003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "Counts all demand code reads", 440 "Counter": "0,1,2,3", 441 "EventCode": "0xB7, 0xBB", 442 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 443 "MSRIndex": "0x1a6,0x1a7", 444 "MSRValue": "0x2000400004", 445 "SampleAfterValue": "100003", 446 "UMask": "0x1" 447 }, 448 { 449 "BriefDescription": "Counts all demand code reads", 450 "Counter": "0,1,2,3", 451 "EventCode": "0xB7, 0xBB", 452 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", 453 "MSRIndex": "0x1a6,0x1a7", 454 "MSRValue": "0x2000020004", 455 "SampleAfterValue": "100003", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "Counts demand data reads", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xB7, 0xBB", 462 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", 463 "MSRIndex": "0x1a6,0x1a7", 464 "MSRValue": "0x20001C0001", 465 "SampleAfterValue": "100003", 466 "UMask": "0x1" 467 }, 468 { 469 "BriefDescription": "Counts demand data reads", 470 "Counter": "0,1,2,3", 471 "EventCode": "0xB7, 0xBB", 472 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", 473 "MSRIndex": "0x1a6,0x1a7", 474 "MSRValue": "0x2000080001", 475 "SampleAfterValue": "100003", 476 "UMask": "0x1" 477 }, 478 { 479 "BriefDescription": "Counts demand data reads", 480 "Counter": "0,1,2,3", 481 "EventCode": "0xB7, 0xBB", 482 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", 483 "MSRIndex": "0x1a6,0x1a7", 484 "MSRValue": "0x2000040001", 485 "SampleAfterValue": "100003", 486 "UMask": "0x1" 487 }, 488 { 489 "BriefDescription": "Counts demand data reads", 490 "Counter": "0,1,2,3", 491 "EventCode": "0xB7, 0xBB", 492 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", 493 "MSRIndex": "0x1a6,0x1a7", 494 "MSRValue": "0x2000100001", 495 "SampleAfterValue": "100003", 496 "UMask": "0x1" 497 }, 498 { 499 "BriefDescription": "Counts demand data reads", 500 "Counter": "0,1,2,3", 501 "EventCode": "0xB7, 0xBB", 502 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", 503 "MSRIndex": "0x1a6,0x1a7", 504 "MSRValue": "0x3FFC400001", 505 "SampleAfterValue": "100003", 506 "UMask": "0x1" 507 }, 508 { 509 "BriefDescription": "Counts demand data reads", 510 "Counter": "0,1,2,3", 511 "EventCode": "0xB7, 0xBB", 512 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", 513 "MSRIndex": "0x1a6,0x1a7", 514 "MSRValue": "0x103C400001", 515 "SampleAfterValue": "100003", 516 "UMask": "0x1" 517 }, 518 { 519 "BriefDescription": "Counts demand data reads", 520 "Counter": "0,1,2,3", 521 "EventCode": "0xB7, 0xBB", 522 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", 523 "MSRIndex": "0x1a6,0x1a7", 524 "MSRValue": "0x43C400001", 525 "SampleAfterValue": "100003", 526 "UMask": "0x1" 527 }, 528 { 529 "BriefDescription": "Counts demand data reads", 530 "Counter": "0,1,2,3", 531 "EventCode": "0xB7, 0xBB", 532 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", 533 "MSRIndex": "0x1a6,0x1a7", 534 "MSRValue": "0x23C400001", 535 "SampleAfterValue": "100003", 536 "UMask": "0x1" 537 }, 538 { 539 "BriefDescription": "Counts demand data reads", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xB7, 0xBB", 542 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", 543 "MSRIndex": "0x1a6,0x1a7", 544 "MSRValue": "0xBC400001", 545 "SampleAfterValue": "100003", 546 "UMask": "0x1" 547 }, 548 { 549 "BriefDescription": "Counts demand data reads", 550 "Counter": "0,1,2,3", 551 "EventCode": "0xB7, 0xBB", 552 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", 553 "MSRIndex": "0x1a6,0x1a7", 554 "MSRValue": "0x203C400001", 555 "SampleAfterValue": "100003", 556 "UMask": "0x1" 557 }, 558 { 559 "BriefDescription": "Counts demand data reads", 560 "Counter": "0,1,2,3", 561 "EventCode": "0xB7, 0xBB", 562 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", 563 "MSRIndex": "0x1a6,0x1a7", 564 "MSRValue": "0x13C400001", 565 "SampleAfterValue": "100003", 566 "UMask": "0x1" 567 }, 568 { 569 "BriefDescription": "Counts demand data reads", 570 "Counter": "0,1,2,3", 571 "EventCode": "0xB7, 0xBB", 572 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", 573 "MSRIndex": "0x1a6,0x1a7", 574 "MSRValue": "0x7C400001", 575 "SampleAfterValue": "100003", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "Counts demand data reads", 580 "Counter": "0,1,2,3", 581 "EventCode": "0xB7, 0xBB", 582 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", 583 "MSRIndex": "0x1a6,0x1a7", 584 "MSRValue": "0x3FC4000001", 585 "SampleAfterValue": "100003", 586 "UMask": "0x1" 587 }, 588 { 589 "BriefDescription": "Counts demand data reads", 590 "Counter": "0,1,2,3", 591 "EventCode": "0xB7, 0xBB", 592 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 593 "MSRIndex": "0x1a6,0x1a7", 594 "MSRValue": "0x1004000001", 595 "SampleAfterValue": "100003", 596 "UMask": "0x1" 597 }, 598 { 599 "BriefDescription": "Counts demand data reads", 600 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"OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", 1033 "MSRIndex": "0x1a6,0x1a7", 1034 "MSRValue": "0x1004008000", 1035 "SampleAfterValue": "100003", 1036 "UMask": "0x1" 1037 }, 1038 { 1039 "BriefDescription": "Counts any other requests", 1040 "Counter": "0,1,2,3", 1041 "EventCode": "0xB7, 0xBB", 1042 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", 1043 "MSRIndex": "0x1a6,0x1a7", 1044 "MSRValue": "0x404008000", 1045 "SampleAfterValue": "100003", 1046 "UMask": "0x1" 1047 }, 1048 { 1049 "BriefDescription": "Counts any other requests", 1050 "Counter": "0,1,2,3", 1051 "EventCode": "0xB7, 0xBB", 1052 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", 1053 "MSRIndex": "0x1a6,0x1a7", 1054 "MSRValue": "0x204008000", 1055 "SampleAfterValue": "100003", 1056 "UMask": "0x1" 1057 }, 1058 { 1059 "BriefDescription": "Counts any other requests", 1060 "Counter": "0,1,2,3", 1061 "EventCode": "0xB7, 0xBB", 1062 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", 1063 "MSRIndex": "0x1a6,0x1a7", 1064 "MSRValue": "0x84008000", 1065 "SampleAfterValue": "100003", 1066 "UMask": "0x1" 1067 }, 1068 { 1069 "BriefDescription": "Counts any other requests", 1070 "Counter": "0,1,2,3", 1071 "EventCode": "0xB7, 0xBB", 1072 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", 1073 "MSRIndex": "0x1a6,0x1a7", 1074 "MSRValue": "0x2004008000", 1075 "SampleAfterValue": "100003", 1076 "UMask": "0x1" 1077 }, 1078 { 1079 "BriefDescription": "Counts any other requests", 1080 "Counter": "0,1,2,3", 1081 "EventCode": "0xB7, 0xBB", 1082 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", 1083 "MSRIndex": "0x1a6,0x1a7", 1084 "MSRValue": "0x104008000", 1085 "SampleAfterValue": "100003", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "Counts any other requests", 1090 "Counter": "0,1,2,3", 1091 "EventCode": "0xB7, 0xBB", 1092 "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", 1093 "MSRIndex": "0x1a6,0x1a7", 1094 "MSRValue": "0x44008000", 1095 "SampleAfterValue": "100003", 1096 "UMask": "0x1" 1097 }, 1098 { 1099 "BriefDescription": "Counts any other requests", 1100 "Counter": "0,1,2,3", 1101 "EventCode": "0xB7, 0xBB", 1102 "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", 1103 "MSRIndex": "0x1a6,0x1a7", 1104 "MSRValue": "0x2000408000", 1105 "SampleAfterValue": "100003", 1106 "UMask": "0x1" 1107 }, 1108 { 1109 "BriefDescription": "Counts any other requests", 1110 "Counter": "0,1,2,3", 1111 "EventCode": "0xB7, 0xBB", 1112 "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", 1113 "MSRIndex": "0x1a6,0x1a7", 1114 "MSRValue": "0x2000028000", 1115 "SampleAfterValue": "100003", 1116 "UMask": "0x1" 1117 }, 1118 { 1119 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 1120 "Counter": "0,1,2,3", 1121 "EventCode": "0xC9", 1122 "EventName": "RTM_RETIRED.ABORTED", 1123 "PEBS": "2", 1124 "PublicDescription": "Number of times RTM abort was triggered.", 1125 "SampleAfterValue": "2000003", 1126 "UMask": "0x4" 1127 }, 1128 { 1129 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 1130 "Counter": "0,1,2,3", 1131 "EventCode": "0xC9", 1132 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 1133 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 1134 "SampleAfterValue": "2000003", 1135 "UMask": "0x80" 1136 }, 1137 { 1138 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 1139 "Counter": "0,1,2,3", 1140 "EventCode": "0xC9", 1141 "EventName": "RTM_RETIRED.ABORTED_MEM", 1142 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 1143 "SampleAfterValue": "2000003", 1144 "UMask": "0x8" 1145 }, 1146 { 1147 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 1148 "Counter": "0,1,2,3", 1149 "EventCode": "0xC9", 1150 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 1151 "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 1152 "SampleAfterValue": "2000003", 1153 "UMask": "0x40" 1154 }, 1155 { 1156 "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", 1157 "Counter": "0,1,2,3", 1158 "EventCode": "0xC9", 1159 "EventName": "RTM_RETIRED.ABORTED_TIMER", 1160 "SampleAfterValue": "2000003", 1161 "UMask": "0x10" 1162 }, 1163 { 1164 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 1165 "Counter": "0,1,2,3", 1166 "EventCode": "0xC9", 1167 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 1168 "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 1169 "SampleAfterValue": "2000003", 1170 "UMask": "0x20" 1171 }, 1172 { 1173 "BriefDescription": "Number of times an RTM execution successfully committed", 1174 "Counter": "0,1,2,3", 1175 "EventCode": "0xC9", 1176 "EventName": "RTM_RETIRED.COMMIT", 1177 "PublicDescription": "Number of times RTM commit succeeded.", 1178 "SampleAfterValue": "2000003", 1179 "UMask": "0x2" 1180 }, 1181 { 1182 "BriefDescription": "Number of times an RTM execution started.", 1183 "Counter": "0,1,2,3", 1184 "EventCode": "0xC9", 1185 "EventName": "RTM_RETIRED.START", 1186 "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", 1187 "SampleAfterValue": "2000003", 1188 "UMask": "0x1" 1189 }, 1190 { 1191 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 1192 "Counter": "0,1,2,3", 1193 "EventCode": "0x5d", 1194 "EventName": "TX_EXEC.MISC1", 1195 "SampleAfterValue": "2000003", 1196 "UMask": "0x1" 1197 }, 1198 { 1199 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 1200 "Counter": "0,1,2,3", 1201 "EventCode": "0x5d", 1202 "EventName": "TX_EXEC.MISC2", 1203 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 1204 "SampleAfterValue": "2000003", 1205 "UMask": "0x2" 1206 }, 1207 { 1208 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 1209 "Counter": "0,1,2,3", 1210 "EventCode": "0x5d", 1211 "EventName": "TX_EXEC.MISC3", 1212 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 1213 "SampleAfterValue": "2000003", 1214 "UMask": "0x4" 1215 }, 1216 { 1217 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 1218 "Counter": "0,1,2,3", 1219 "EventCode": "0x5d", 1220 "EventName": "TX_EXEC.MISC4", 1221 "PublicDescription": "RTM region detected inside HLE.", 1222 "SampleAfterValue": "2000003", 1223 "UMask": "0x8" 1224 }, 1225 { 1226 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", 1227 "Counter": "0,1,2,3", 1228 "EventCode": "0x5d", 1229 "EventName": "TX_EXEC.MISC5", 1230 "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 1231 "SampleAfterValue": "2000003", 1232 "UMask": "0x10" 1233 }, 1234 { 1235 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", 1236 "Counter": "0,1,2,3", 1237 "EventCode": "0x54", 1238 "EventName": "TX_MEM.ABORT_CAPACITY", 1239 "SampleAfterValue": "2000003", 1240 "UMask": "0x2" 1241 }, 1242 { 1243 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 1244 "Counter": "0,1,2,3", 1245 "EventCode": "0x54", 1246 "EventName": "TX_MEM.ABORT_CONFLICT", 1247 "PublicDescription": "Number of times a TSX line had a cache conflict.", 1248 "SampleAfterValue": "2000003", 1249 "UMask": "0x1" 1250 }, 1251 { 1252 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 1253 "Counter": "0,1,2,3", 1254 "EventCode": "0x54", 1255 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 1256 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 1257 "SampleAfterValue": "2000003", 1258 "UMask": "0x10" 1259 }, 1260 { 1261 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 1262 "Counter": "0,1,2,3", 1263 "EventCode": "0x54", 1264 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 1265 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 1266 "SampleAfterValue": "2000003", 1267 "UMask": "0x8" 1268 }, 1269 { 1270 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 1271 "Counter": "0,1,2,3", 1272 "EventCode": "0x54", 1273 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 1274 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 1275 "SampleAfterValue": "2000003", 1276 "UMask": "0x20" 1277 }, 1278 { 1279 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 1280 "Counter": "0,1,2,3", 1281 "EventCode": "0x54", 1282 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 1283 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 1284 "SampleAfterValue": "2000003", 1285 "UMask": "0x4" 1286 }, 1287 { 1288 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 1289 "Counter": "0,1,2,3", 1290 "EventCode": "0x54", 1291 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 1292 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 1293 "SampleAfterValue": "2000003", 1294 "UMask": "0x40" 1295 } 1296] 1297