1[ 2 { 3 "PEBS": "1", 4 "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", 5 "EventCode": "0x04", 6 "Counter": "0,1", 7 "UMask": "0x8", 8 "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 9 "SampleAfterValue": "200003", 10 "BriefDescription": "Loads missed DTLB" 11 }, 12 { 13 "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 14 "EventCode": "0x05", 15 "Counter": "0,1", 16 "UMask": "0x1", 17 "EventName": "PAGE_WALKS.D_SIDE_WALKS", 18 "SampleAfterValue": "100003", 19 "BriefDescription": "D-side page-walks", 20 "EdgeDetect": "1" 21 }, 22 { 23 "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 24 "EventCode": "0x05", 25 "Counter": "0,1", 26 "UMask": "0x1", 27 "EventName": "PAGE_WALKS.D_SIDE_CYCLES", 28 "SampleAfterValue": "200003", 29 "BriefDescription": "Duration of D-side page-walks in core cycles" 30 }, 31 { 32 "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 33 "EventCode": "0x05", 34 "Counter": "0,1", 35 "UMask": "0x2", 36 "EventName": "PAGE_WALKS.I_SIDE_WALKS", 37 "SampleAfterValue": "100003", 38 "BriefDescription": "I-side page-walks", 39 "EdgeDetect": "1" 40 }, 41 { 42 "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 43 "EventCode": "0x05", 44 "Counter": "0,1", 45 "UMask": "0x2", 46 "EventName": "PAGE_WALKS.I_SIDE_CYCLES", 47 "SampleAfterValue": "200003", 48 "BriefDescription": "Duration of I-side page-walks in core cycles" 49 }, 50 { 51 "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 52 "EventCode": "0x05", 53 "Counter": "0,1", 54 "UMask": "0x3", 55 "EventName": "PAGE_WALKS.WALKS", 56 "SampleAfterValue": "100003", 57 "BriefDescription": "Total page walks that are completed (I-side and D-side)", 58 "EdgeDetect": "1" 59 }, 60 { 61 "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", 62 "EventCode": "0x05", 63 "Counter": "0,1", 64 "UMask": "0x3", 65 "EventName": "PAGE_WALKS.CYCLES", 66 "SampleAfterValue": "200003", 67 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)" 68 } 69]