1[ 2 { 3 "BriefDescription": "Loads missed DTLB", 4 "Counter": "0,1", 5 "EventCode": "0x04", 6 "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 7 "PEBS": "1", 8 "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", 9 "SampleAfterValue": "200003", 10 "UMask": "0x8" 11 }, 12 { 13 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", 14 "Counter": "0,1", 15 "EventCode": "0x05", 16 "EventName": "PAGE_WALKS.CYCLES", 17 "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", 18 "SampleAfterValue": "200003", 19 "UMask": "0x3" 20 }, 21 { 22 "BriefDescription": "Duration of D-side page-walks in core cycles", 23 "Counter": "0,1", 24 "EventCode": "0x05", 25 "EventName": "PAGE_WALKS.D_SIDE_CYCLES", 26 "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 27 "SampleAfterValue": "200003", 28 "UMask": "0x1" 29 }, 30 { 31 "BriefDescription": "D-side page-walks", 32 "Counter": "0,1", 33 "EdgeDetect": "1", 34 "EventCode": "0x05", 35 "EventName": "PAGE_WALKS.D_SIDE_WALKS", 36 "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 37 "SampleAfterValue": "100003", 38 "UMask": "0x1" 39 }, 40 { 41 "BriefDescription": "Duration of I-side page-walks in core cycles", 42 "Counter": "0,1", 43 "EventCode": "0x05", 44 "EventName": "PAGE_WALKS.I_SIDE_CYCLES", 45 "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 46 "SampleAfterValue": "200003", 47 "UMask": "0x2" 48 }, 49 { 50 "BriefDescription": "I-side page-walks", 51 "Counter": "0,1", 52 "EdgeDetect": "1", 53 "EventCode": "0x05", 54 "EventName": "PAGE_WALKS.I_SIDE_WALKS", 55 "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 56 "SampleAfterValue": "100003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "Total page walks that are completed (I-side and D-side)", 61 "Counter": "0,1", 62 "EdgeDetect": "1", 63 "EventCode": "0x05", 64 "EventName": "PAGE_WALKS.WALKS", 65 "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 66 "SampleAfterValue": "100003", 67 "UMask": "0x3" 68 } 69] 70