1[ 2 { 3 "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 4 "EventCode": "0xc4", 5 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 6 "PEBS": "1", 7 "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", 8 "SampleAfterValue": "200003" 9 }, 10 { 11 "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", 12 "EventCode": "0xc5", 13 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 14 "PEBS": "1", 15 "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", 16 "SampleAfterValue": "200003" 17 }, 18 { 19 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 20 "EventName": "CPU_CLK_UNHALTED.CORE", 21 "SampleAfterValue": "2000003", 22 "UMask": "0x2" 23 }, 24 { 25 "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", 26 "EventCode": "0x3c", 27 "EventName": "CPU_CLK_UNHALTED.CORE_P", 28 "SampleAfterValue": "2000003" 29 }, 30 { 31 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 32 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 33 "SampleAfterValue": "2000003", 34 "UMask": "0x3" 35 }, 36 { 37 "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", 38 "EventCode": "0x3c", 39 "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", 40 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", 41 "SampleAfterValue": "2000003", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 46 "EventName": "CPU_CLK_UNHALTED.THREAD", 47 "SampleAfterValue": "2000003", 48 "UMask": "0x2" 49 }, 50 { 51 "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", 52 "EventCode": "0x3c", 53 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 54 "SampleAfterValue": "2000003" 55 }, 56 { 57 "BriefDescription": "Fixed Counter: Counts the number of instructions retired", 58 "EventName": "INST_RETIRED.ANY", 59 "PEBS": "1", 60 "SampleAfterValue": "2000003", 61 "UMask": "0x1" 62 }, 63 { 64 "BriefDescription": "Counts the number of instructions retired", 65 "EventCode": "0xc0", 66 "EventName": "INST_RETIRED.ANY_P", 67 "PEBS": "1", 68 "SampleAfterValue": "2000003" 69 }, 70 { 71 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", 72 "EventCode": "0x73", 73 "EventName": "TOPDOWN_BAD_SPECULATION.ALL", 74 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", 75 "SampleAfterValue": "1000003" 76 }, 77 { 78 "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", 79 "EventCode": "0x74", 80 "EventName": "TOPDOWN_BE_BOUND.ALL", 81 "SampleAfterValue": "1000003" 82 }, 83 { 84 "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", 85 "EventCode": "0x71", 86 "EventName": "TOPDOWN_FE_BOUND.ALL", 87 "SampleAfterValue": "1000003" 88 }, 89 { 90 "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL", 91 "EventCode": "0x72", 92 "EventName": "TOPDOWN_RETIRING.ALL", 93 "PEBS": "1", 94 "SampleAfterValue": "1000003" 95 } 96] 97