1[ 2 { 3 "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", 4 "Counter": "0,1,2,3,4,5,6,7", 5 "EventCode": "0x2e", 6 "EventName": "LONGEST_LAT_CACHE.MISS", 7 "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 8 "SampleAfterValue": "200003", 9 "UMask": "0x41" 10 }, 11 { 12 "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", 13 "Counter": "0,1,2,3,4,5,6,7", 14 "EventCode": "0x2e", 15 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 16 "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", 17 "SampleAfterValue": "200003", 18 "UMask": "0x4f" 19 }, 20 { 21 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", 22 "Counter": "0,1,2,3,4,5,6,7", 23 "EventCode": "0x35", 24 "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", 25 "SampleAfterValue": "1000003", 26 "UMask": "0x7f" 27 }, 28 { 29 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 30 "Counter": "0,1,2,3,4,5,6,7", 31 "EventCode": "0x35", 32 "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", 33 "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 34 "SampleAfterValue": "1000003", 35 "UMask": "0x1" 36 }, 37 { 38 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC.", 39 "Counter": "0,1,2,3,4,5,6,7", 40 "EventCode": "0x35", 41 "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", 42 "SampleAfterValue": "1000003", 43 "UMask": "0x6" 44 }, 45 { 46 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.", 47 "Counter": "0,1,2,3,4,5,6,7", 48 "EventCode": "0x35", 49 "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", 50 "SampleAfterValue": "1000003", 51 "UMask": "0x78" 52 }, 53 { 54 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.", 55 "Counter": "0,1,2,3,4,5,6,7", 56 "EventCode": "0x34", 57 "EventName": "MEM_BOUND_STALLS_LOAD.ALL", 58 "SampleAfterValue": "1000003", 59 "UMask": "0x7f" 60 }, 61 { 62 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 63 "Counter": "0,1,2,3,4,5,6,7", 64 "EventCode": "0x34", 65 "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", 66 "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", 67 "SampleAfterValue": "1000003", 68 "UMask": "0x1" 69 }, 70 { 71 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.", 72 "Counter": "0,1,2,3,4,5,6,7", 73 "EventCode": "0x34", 74 "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", 75 "SampleAfterValue": "1000003", 76 "UMask": "0x6" 77 }, 78 { 79 "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.", 80 "Counter": "0,1,2,3,4,5,6,7", 81 "EventCode": "0x34", 82 "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", 83 "SampleAfterValue": "1000003", 84 "UMask": "0x78" 85 }, 86 { 87 "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", 88 "Counter": "0,1,2,3,4,5,6,7", 89 "EventCode": "0xd3", 90 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 91 "SampleAfterValue": "1000003", 92 "UMask": "0x1" 93 }, 94 { 95 "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.", 96 "Counter": "0,1,2,3,4,5,6,7", 97 "EventCode": "0xd1", 98 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 99 "SampleAfterValue": "200003", 100 "UMask": "0x1" 101 }, 102 { 103 "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.", 104 "Counter": "0,1,2,3,4,5,6,7", 105 "EventCode": "0xd1", 106 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 107 "SampleAfterValue": "200003", 108 "UMask": "0x40" 109 }, 110 { 111 "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", 112 "Counter": "0,1,2,3,4,5,6,7", 113 "EventCode": "0xd1", 114 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 115 "SampleAfterValue": "200003", 116 "UMask": "0x2" 117 }, 118 { 119 "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.", 120 "Counter": "0,1,2,3,4,5,6,7", 121 "EventCode": "0xd1", 122 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 123 "SampleAfterValue": "200003", 124 "UMask": "0x80" 125 }, 126 { 127 "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", 128 "Counter": "0,1,2,3,4,5,6,7", 129 "EventCode": "0xd1", 130 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 131 "SampleAfterValue": "200003", 132 "UMask": "0x1c" 133 }, 134 { 135 "BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.", 136 "Counter": "0,1,2,3,4,5,6,7", 137 "EventCode": "0xd1", 138 "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", 139 "SampleAfterValue": "200003", 140 "UMask": "0x20" 141 }, 142 { 143 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 144 "Counter": "0,1,2,3,4,5,6,7", 145 "EventCode": "0x04", 146 "EventName": "MEM_SCHEDULER_BLOCK.ALL", 147 "SampleAfterValue": "20003", 148 "UMask": "0x7" 149 }, 150 { 151 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 152 "Counter": "0,1,2,3,4,5,6,7", 153 "EventCode": "0x04", 154 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 155 "SampleAfterValue": "20003", 156 "UMask": "0x2" 157 }, 158 { 159 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 160 "Counter": "0,1,2,3,4,5,6,7", 161 "EventCode": "0x04", 162 "EventName": "MEM_SCHEDULER_BLOCK.RSV", 163 "SampleAfterValue": "20003", 164 "UMask": "0x4" 165 }, 166 { 167 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 168 "Counter": "0,1,2,3,4,5,6,7", 169 "EventCode": "0x04", 170 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 171 "SampleAfterValue": "20003", 172 "UMask": "0x1" 173 }, 174 { 175 "BriefDescription": "Counts the number of load ops retired.", 176 "Counter": "0,1,2,3,4,5,6,7", 177 "Data_LA": "1", 178 "EventCode": "0xd0", 179 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 180 "SampleAfterValue": "200003", 181 "UMask": "0x81" 182 }, 183 { 184 "BriefDescription": "Counts the number of store ops retired.", 185 "Counter": "0,1,2,3,4,5,6,7", 186 "Data_LA": "1", 187 "EventCode": "0xd0", 188 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 189 "SampleAfterValue": "200003", 190 "UMask": "0x82" 191 }, 192 { 193 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 194 "Counter": "0,1", 195 "Data_LA": "1", 196 "EventCode": "0xd0", 197 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", 198 "MSRIndex": "0x3F6", 199 "MSRValue": "0x400", 200 "SampleAfterValue": "1000003", 201 "UMask": "0x5" 202 }, 203 { 204 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 205 "Counter": "0,1", 206 "Data_LA": "1", 207 "EventCode": "0xd0", 208 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 209 "MSRIndex": "0x3F6", 210 "MSRValue": "0x80", 211 "SampleAfterValue": "1000003", 212 "UMask": "0x5" 213 }, 214 { 215 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 216 "Counter": "0,1", 217 "Data_LA": "1", 218 "EventCode": "0xd0", 219 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 220 "MSRIndex": "0x3F6", 221 "MSRValue": "0x10", 222 "SampleAfterValue": "1000003", 223 "UMask": "0x5" 224 }, 225 { 226 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 227 "Counter": "0,1", 228 "Data_LA": "1", 229 "EventCode": "0xd0", 230 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", 231 "MSRIndex": "0x3F6", 232 "MSRValue": "0x800", 233 "SampleAfterValue": "1000003", 234 "UMask": "0x5" 235 }, 236 { 237 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 238 "Counter": "0,1", 239 "Data_LA": "1", 240 "EventCode": "0xd0", 241 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", 242 "MSRIndex": "0x3F6", 243 "MSRValue": "0x100", 244 "SampleAfterValue": "1000003", 245 "UMask": "0x5" 246 }, 247 { 248 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 249 "Counter": "0,1", 250 "Data_LA": "1", 251 "EventCode": "0xd0", 252 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", 253 "MSRIndex": "0x3F6", 254 "MSRValue": "0x20", 255 "SampleAfterValue": "1000003", 256 "UMask": "0x5" 257 }, 258 { 259 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 260 "Counter": "0,1", 261 "Data_LA": "1", 262 "EventCode": "0xd0", 263 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", 264 "MSRIndex": "0x3F6", 265 "MSRValue": "0x4", 266 "SampleAfterValue": "1000003", 267 "UMask": "0x5" 268 }, 269 { 270 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 271 "Counter": "0,1", 272 "Data_LA": "1", 273 "EventCode": "0xd0", 274 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", 275 "MSRIndex": "0x3F6", 276 "MSRValue": "0x200", 277 "SampleAfterValue": "1000003", 278 "UMask": "0x5" 279 }, 280 { 281 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 282 "Counter": "0,1", 283 "Data_LA": "1", 284 "EventCode": "0xd0", 285 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", 286 "MSRIndex": "0x3F6", 287 "MSRValue": "0x40", 288 "SampleAfterValue": "1000003", 289 "UMask": "0x5" 290 }, 291 { 292 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 293 "Counter": "0,1", 294 "Data_LA": "1", 295 "EventCode": "0xd0", 296 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", 297 "MSRIndex": "0x3F6", 298 "MSRValue": "0x8", 299 "SampleAfterValue": "1000003", 300 "UMask": "0x5" 301 }, 302 { 303 "BriefDescription": "Counts the number of load uops retired that performed one or more locks", 304 "Counter": "0,1,2,3,4,5,6,7", 305 "Data_LA": "1", 306 "EventCode": "0xd0", 307 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 308 "SampleAfterValue": "200003", 309 "UMask": "0x21" 310 }, 311 { 312 "BriefDescription": "Counts the number of memory uops retired that were splits.", 313 "Counter": "0,1,2,3,4,5,6,7", 314 "Data_LA": "1", 315 "EventCode": "0xd0", 316 "EventName": "MEM_UOPS_RETIRED.SPLIT", 317 "SampleAfterValue": "200003", 318 "UMask": "0x43" 319 }, 320 { 321 "BriefDescription": "Counts the number of retired split load uops.", 322 "Counter": "0,1,2,3,4,5,6,7", 323 "Data_LA": "1", 324 "EventCode": "0xd0", 325 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 326 "SampleAfterValue": "200003", 327 "UMask": "0x41" 328 }, 329 { 330 "BriefDescription": "Counts the number of retired split store uops.", 331 "Counter": "0,1,2,3,4,5,6,7", 332 "Data_LA": "1", 333 "EventCode": "0xd0", 334 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 335 "SampleAfterValue": "200003", 336 "UMask": "0x42" 337 }, 338 { 339 "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", 340 "Counter": "0,1,2,3,4,5,6,7", 341 "Data_LA": "1", 342 "EventCode": "0xd0", 343 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", 344 "SampleAfterValue": "1000003", 345 "UMask": "0x6" 346 }, 347 { 348 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 349 "Counter": "0,1,2,3,4,5,6,7", 350 "EventCode": "0xB7", 351 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 352 "MSRIndex": "0x1a6,0x1a7", 353 "MSRValue": "0x10003C0001", 354 "SampleAfterValue": "100003", 355 "UMask": "0x1" 356 }, 357 { 358 "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 359 "Counter": "0,1,2,3,4,5,6,7", 360 "EventCode": "0xB7", 361 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 362 "MSRIndex": "0x1a6,0x1a7", 363 "MSRValue": "0x8003C0001", 364 "SampleAfterValue": "100003", 365 "UMask": "0x1" 366 }, 367 { 368 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 369 "Counter": "0,1,2,3,4,5,6,7", 370 "EventCode": "0xB7", 371 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 372 "MSRIndex": "0x1a6,0x1a7", 373 "MSRValue": "0x10003C0002", 374 "SampleAfterValue": "100003", 375 "UMask": "0x1" 376 }, 377 { 378 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", 379 "Counter": "0,1,2,3,4,5,6,7", 380 "EventCode": "0x71", 381 "EventName": "TOPDOWN_FE_BOUND.ICACHE", 382 "SampleAfterValue": "1000003", 383 "UMask": "0x20" 384 } 385] 386