1[ 2 { 3 "BriefDescription": "ARITH.FPDIV_ACTIVE", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5,6,7", 6 "CounterMask": "1", 7 "EventCode": "0xb0", 8 "EventName": "ARITH.FPDIV_ACTIVE", 9 "PEBScounters": "0,1,2,3,4,5,6,7", 10 "SampleAfterValue": "1000003", 11 "Speculative": "1", 12 "UMask": "0x1" 13 }, 14 { 15 "BriefDescription": "Counts all microcode FP assists.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3,4,5,6,7", 18 "EventCode": "0xc1", 19 "EventName": "ASSISTS.FP", 20 "PEBScounters": "0,1,2,3,4,5,6,7", 21 "PublicDescription": "Counts all microcode Floating Point assists.", 22 "SampleAfterValue": "100003", 23 "Speculative": "1", 24 "UMask": "0x2" 25 }, 26 { 27 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3,4,5,6,7", 30 "EventCode": "0xc1", 31 "EventName": "ASSISTS.SSE_AVX_MIX", 32 "PEBScounters": "0,1,2,3,4,5,6,7", 33 "SampleAfterValue": "1000003", 34 "Speculative": "1", 35 "UMask": "0x10" 36 }, 37 { 38 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 39 "CollectPEBSRecord": "2", 40 "Counter": "0,1,2,3,4,5,6,7", 41 "EventCode": "0xb3", 42 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 43 "PEBScounters": "0,1,2,3,4,5,6,7", 44 "SampleAfterValue": "2000003", 45 "Speculative": "1", 46 "UMask": "0x1" 47 }, 48 { 49 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 50 "CollectPEBSRecord": "2", 51 "Counter": "0,1,2,3,4,5,6,7", 52 "EventCode": "0xb3", 53 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 54 "PEBScounters": "0,1,2,3,4,5,6,7", 55 "SampleAfterValue": "2000003", 56 "Speculative": "1", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 61 "CollectPEBSRecord": "2", 62 "Counter": "0,1,2,3,4,5,6,7", 63 "EventCode": "0xb3", 64 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 65 "PEBScounters": "0,1,2,3,4,5,6,7", 66 "SampleAfterValue": "2000003", 67 "Speculative": "1", 68 "UMask": "0x4" 69 }, 70 { 71 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 72 "CollectPEBSRecord": "2", 73 "Counter": "0,1,2,3,4,5,6,7", 74 "EventCode": "0xc7", 75 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 76 "PEBScounters": "0,1,2,3,4,5,6,7", 77 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 78 "SampleAfterValue": "100003", 79 "UMask": "0x4" 80 }, 81 { 82 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 83 "CollectPEBSRecord": "2", 84 "Counter": "0,1,2,3,4,5,6,7", 85 "EventCode": "0xc7", 86 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 87 "PEBScounters": "0,1,2,3,4,5,6,7", 88 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 89 "SampleAfterValue": "100003", 90 "UMask": "0x8" 91 }, 92 { 93 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 94 "CollectPEBSRecord": "2", 95 "Counter": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xc7", 97 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 98 "PEBScounters": "0,1,2,3,4,5,6,7", 99 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 100 "SampleAfterValue": "100003", 101 "UMask": "0x10" 102 }, 103 { 104 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 105 "CollectPEBSRecord": "2", 106 "Counter": "0,1,2,3,4,5,6,7", 107 "EventCode": "0xc7", 108 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 109 "PEBScounters": "0,1,2,3,4,5,6,7", 110 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 111 "SampleAfterValue": "100003", 112 "UMask": "0x20" 113 }, 114 { 115 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 116 "CollectPEBSRecord": "2", 117 "Counter": "0,1,2,3,4,5,6,7", 118 "EventCode": "0xc7", 119 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 120 "PEBScounters": "0,1,2,3,4,5,6,7", 121 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 122 "SampleAfterValue": "100003", 123 "UMask": "0x40" 124 }, 125 { 126 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 127 "CollectPEBSRecord": "2", 128 "Counter": "0,1,2,3,4,5,6,7", 129 "EventCode": "0xc7", 130 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 131 "PEBScounters": "0,1,2,3,4,5,6,7", 132 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 133 "SampleAfterValue": "100003", 134 "UMask": "0x80" 135 }, 136 { 137 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 138 "CollectPEBSRecord": "2", 139 "Counter": "0,1,2,3,4,5,6,7", 140 "EventCode": "0xc7", 141 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 142 "PEBScounters": "0,1,2,3,4,5,6,7", 143 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 144 "SampleAfterValue": "100003", 145 "UMask": "0x1" 146 }, 147 { 148 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 149 "CollectPEBSRecord": "2", 150 "Counter": "0,1,2,3,4,5,6,7", 151 "EventCode": "0xc7", 152 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 153 "PEBScounters": "0,1,2,3,4,5,6,7", 154 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 155 "SampleAfterValue": "100003", 156 "UMask": "0x2" 157 }, 158 { 159 "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 160 "Counter": "0,1,2,3,4,5,6,7", 161 "EventCode": "0xcf", 162 "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 163 "PEBScounters": "0,1,2,3,4,5,6,7", 164 "SampleAfterValue": "100003", 165 "UMask": "0x4" 166 }, 167 { 168 "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 169 "Counter": "0,1,2,3,4,5,6,7", 170 "EventCode": "0xcf", 171 "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 172 "PEBScounters": "0,1,2,3,4,5,6,7", 173 "SampleAfterValue": "100003", 174 "UMask": "0x8" 175 }, 176 { 177 "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 178 "CollectPEBSRecord": "2", 179 "Counter": "0,1,2,3,4,5,6,7", 180 "EventCode": "0xcf", 181 "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 182 "PEBScounters": "0,1,2,3,4,5,6,7", 183 "SampleAfterValue": "100003", 184 "UMask": "0x10" 185 }, 186 { 187 "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 188 "Counter": "0,1,2,3,4,5,6,7", 189 "EventCode": "0xcf", 190 "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 191 "PEBScounters": "0,1,2,3,4,5,6,7", 192 "SampleAfterValue": "100003", 193 "UMask": "0x2" 194 }, 195 { 196 "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 197 "Counter": "0,1,2,3,4,5,6,7", 198 "EventCode": "0xcf", 199 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 200 "PEBScounters": "0,1,2,3,4,5,6,7", 201 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", 202 "SampleAfterValue": "100003", 203 "UMask": "0x3" 204 }, 205 { 206 "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 207 "Counter": "0,1,2,3,4,5,6,7", 208 "EventCode": "0xcf", 209 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 210 "PEBScounters": "0,1,2,3,4,5,6,7", 211 "SampleAfterValue": "100003", 212 "UMask": "0x1" 213 }, 214 { 215 "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 216 "Counter": "0,1,2,3,4,5,6,7", 217 "EventCode": "0xcf", 218 "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 219 "PEBScounters": "0,1,2,3,4,5,6,7", 220 "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", 221 "SampleAfterValue": "100003", 222 "UMask": "0x1c" 223 } 224] 225