1[ 2 { 3 "BriefDescription": "ARITH.FPDIV_ACTIVE", 4 "CounterMask": "1", 5 "EventCode": "0xb0", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "Counts all microcode FP assists.", 12 "EventCode": "0xc1", 13 "EventName": "ASSISTS.FP", 14 "PublicDescription": "Counts all microcode Floating Point assists.", 15 "SampleAfterValue": "100003", 16 "UMask": "0x2" 17 }, 18 { 19 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 20 "EventCode": "0xc1", 21 "EventName": "ASSISTS.SSE_AVX_MIX", 22 "SampleAfterValue": "1000003", 23 "UMask": "0x10" 24 }, 25 { 26 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", 27 "EventCode": "0xb3", 28 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", 34 "EventCode": "0xb3", 35 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x2" 38 }, 39 { 40 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", 41 "EventCode": "0xb3", 42 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 43 "SampleAfterValue": "2000003", 44 "UMask": "0x4" 45 }, 46 { 47 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", 48 "EventCode": "0xb3", 49 "EventName": "FP_ARITH_DISPATCHED.V0", 50 "SampleAfterValue": "2000003", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", 55 "EventCode": "0xb3", 56 "EventName": "FP_ARITH_DISPATCHED.V1", 57 "SampleAfterValue": "2000003", 58 "UMask": "0x2" 59 }, 60 { 61 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", 62 "EventCode": "0xb3", 63 "EventName": "FP_ARITH_DISPATCHED.V2", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x4" 66 }, 67 { 68 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 69 "EventCode": "0xc7", 70 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 71 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 72 "SampleAfterValue": "100003", 73 "UMask": "0x4" 74 }, 75 { 76 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 77 "EventCode": "0xc7", 78 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 79 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 80 "SampleAfterValue": "100003", 81 "UMask": "0x8" 82 }, 83 { 84 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 85 "EventCode": "0xc7", 86 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 87 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 88 "SampleAfterValue": "100003", 89 "UMask": "0x10" 90 }, 91 { 92 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 93 "EventCode": "0xc7", 94 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 95 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x20" 98 }, 99 { 100 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 101 "EventCode": "0xc7", 102 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 103 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 104 "SampleAfterValue": "100003", 105 "UMask": "0x18" 106 }, 107 { 108 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 109 "EventCode": "0xc7", 110 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 111 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 112 "SampleAfterValue": "100003", 113 "UMask": "0x40" 114 }, 115 { 116 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 117 "EventCode": "0xc7", 118 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 119 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 120 "SampleAfterValue": "100003", 121 "UMask": "0x80" 122 }, 123 { 124 "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 125 "EventCode": "0xc7", 126 "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", 127 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 128 "SampleAfterValue": "100003", 129 "UMask": "0x60" 130 }, 131 { 132 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 133 "EventCode": "0xc7", 134 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 135 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 136 "SampleAfterValue": "1000003", 137 "UMask": "0x3" 138 }, 139 { 140 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 141 "EventCode": "0xc7", 142 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 143 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 144 "SampleAfterValue": "100003", 145 "UMask": "0x1" 146 }, 147 { 148 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 149 "EventCode": "0xc7", 150 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 151 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 152 "SampleAfterValue": "100003", 153 "UMask": "0x2" 154 }, 155 { 156 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 157 "EventCode": "0xc7", 158 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 159 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 160 "SampleAfterValue": "1000003", 161 "UMask": "0xfc" 162 }, 163 { 164 "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 165 "EventCode": "0xcf", 166 "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 167 "SampleAfterValue": "100003", 168 "UMask": "0x4" 169 }, 170 { 171 "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 172 "EventCode": "0xcf", 173 "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 174 "SampleAfterValue": "100003", 175 "UMask": "0x8" 176 }, 177 { 178 "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 179 "EventCode": "0xcf", 180 "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 181 "SampleAfterValue": "100003", 182 "UMask": "0x10" 183 }, 184 { 185 "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 186 "EventCode": "0xcf", 187 "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 188 "SampleAfterValue": "100003", 189 "UMask": "0x2" 190 }, 191 { 192 "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 193 "EventCode": "0xcf", 194 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 195 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", 196 "SampleAfterValue": "100003", 197 "UMask": "0x3" 198 }, 199 { 200 "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 201 "EventCode": "0xcf", 202 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 203 "SampleAfterValue": "100003", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 208 "EventCode": "0xcf", 209 "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 210 "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", 211 "SampleAfterValue": "100003", 212 "UMask": "0x1c" 213 } 214] 215