1[ 2 { 3 "BriefDescription": "ARITH.FPDIV_ACTIVE", 4 "CounterMask": "1", 5 "EventCode": "0xb0", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "Counts all microcode FP assists.", 12 "EventCode": "0xc1", 13 "EventName": "ASSISTS.FP", 14 "PublicDescription": "Counts all microcode Floating Point assists.", 15 "SampleAfterValue": "100003", 16 "UMask": "0x2" 17 }, 18 { 19 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 20 "EventCode": "0xc1", 21 "EventName": "ASSISTS.SSE_AVX_MIX", 22 "SampleAfterValue": "1000003", 23 "UMask": "0x10" 24 }, 25 { 26 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 27 "EventCode": "0xb3", 28 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 29 "SampleAfterValue": "2000003", 30 "UMask": "0x1" 31 }, 32 { 33 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 34 "EventCode": "0xb3", 35 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x2" 38 }, 39 { 40 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5", 41 "EventCode": "0xb3", 42 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 43 "SampleAfterValue": "2000003", 44 "UMask": "0x4" 45 }, 46 { 47 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 48 "EventCode": "0xc7", 49 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 50 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 51 "SampleAfterValue": "100003", 52 "UMask": "0x4" 53 }, 54 { 55 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 56 "EventCode": "0xc7", 57 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 58 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 59 "SampleAfterValue": "100003", 60 "UMask": "0x8" 61 }, 62 { 63 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 64 "EventCode": "0xc7", 65 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 66 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 67 "SampleAfterValue": "100003", 68 "UMask": "0x10" 69 }, 70 { 71 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 72 "EventCode": "0xc7", 73 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 74 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 75 "SampleAfterValue": "100003", 76 "UMask": "0x20" 77 }, 78 { 79 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 80 "EventCode": "0xc7", 81 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 82 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 83 "SampleAfterValue": "100003", 84 "UMask": "0x18" 85 }, 86 { 87 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 88 "EventCode": "0xc7", 89 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 90 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 91 "SampleAfterValue": "100003", 92 "UMask": "0x40" 93 }, 94 { 95 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 96 "EventCode": "0xc7", 97 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 98 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x80" 101 }, 102 { 103 "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 104 "EventCode": "0xc7", 105 "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", 106 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 107 "SampleAfterValue": "100003", 108 "UMask": "0x60" 109 }, 110 { 111 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 112 "EventCode": "0xc7", 113 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 114 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 115 "SampleAfterValue": "1000003", 116 "UMask": "0x3" 117 }, 118 { 119 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 120 "EventCode": "0xc7", 121 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 122 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 123 "SampleAfterValue": "100003", 124 "UMask": "0x1" 125 }, 126 { 127 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 128 "EventCode": "0xc7", 129 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 130 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 131 "SampleAfterValue": "100003", 132 "UMask": "0x2" 133 }, 134 { 135 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 136 "EventCode": "0xc7", 137 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 138 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 139 "SampleAfterValue": "1000003", 140 "UMask": "0xfc" 141 }, 142 { 143 "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 144 "EventCode": "0xcf", 145 "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 146 "SampleAfterValue": "100003", 147 "UMask": "0x4" 148 }, 149 { 150 "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 151 "EventCode": "0xcf", 152 "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 153 "SampleAfterValue": "100003", 154 "UMask": "0x8" 155 }, 156 { 157 "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 158 "EventCode": "0xcf", 159 "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 160 "SampleAfterValue": "100003", 161 "UMask": "0x10" 162 }, 163 { 164 "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 165 "EventCode": "0xcf", 166 "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 167 "SampleAfterValue": "100003", 168 "UMask": "0x2" 169 }, 170 { 171 "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 172 "EventCode": "0xcf", 173 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 174 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", 175 "SampleAfterValue": "100003", 176 "UMask": "0x3" 177 }, 178 { 179 "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 180 "EventCode": "0xcf", 181 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 182 "SampleAfterValue": "100003", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 187 "EventCode": "0xcf", 188 "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 189 "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", 190 "SampleAfterValue": "100003", 191 "UMask": "0x1c" 192 } 193] 194