xref: /linux/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) 
1[
2    {
3        "BriefDescription": "Cycles the divider is busy",
4        "EventCode": "0x14",
5        "EventName": "ARITH.CYCLES_DIV_BUSY",
6        "SampleAfterValue": "2000000",
7        "UMask": "0x1"
8    },
9    {
10        "BriefDescription": "Divide Operations executed",
11        "CounterMask": "1",
12        "EdgeDetect": "1",
13        "EventCode": "0x14",
14        "EventName": "ARITH.DIV",
15        "Invert": "1",
16        "SampleAfterValue": "2000000",
17        "UMask": "0x1"
18    },
19    {
20        "BriefDescription": "Multiply operations executed",
21        "EventCode": "0x14",
22        "EventName": "ARITH.MUL",
23        "SampleAfterValue": "2000000",
24        "UMask": "0x2"
25    },
26    {
27        "BriefDescription": "BACLEAR asserted with bad target address",
28        "EventCode": "0xE6",
29        "EventName": "BACLEAR.BAD_TARGET",
30        "SampleAfterValue": "2000000",
31        "UMask": "0x2"
32    },
33    {
34        "BriefDescription": "BACLEAR asserted, regardless of cause",
35        "EventCode": "0xE6",
36        "EventName": "BACLEAR.CLEAR",
37        "SampleAfterValue": "2000000",
38        "UMask": "0x1"
39    },
40    {
41        "BriefDescription": "Instruction queue forced BACLEAR",
42        "EventCode": "0xA7",
43        "EventName": "BACLEAR_FORCE_IQ",
44        "SampleAfterValue": "2000000",
45        "UMask": "0x1"
46    },
47    {
48        "BriefDescription": "Early Branch Prediciton Unit clears",
49        "EventCode": "0xE8",
50        "EventName": "BPU_CLEARS.EARLY",
51        "SampleAfterValue": "2000000",
52        "UMask": "0x1"
53    },
54    {
55        "BriefDescription": "Late Branch Prediction Unit clears",
56        "EventCode": "0xE8",
57        "EventName": "BPU_CLEARS.LATE",
58        "SampleAfterValue": "2000000",
59        "UMask": "0x2"
60    },
61    {
62        "BriefDescription": "Branch prediction unit missed call or return",
63        "EventCode": "0xE5",
64        "EventName": "BPU_MISSED_CALL_RET",
65        "SampleAfterValue": "2000000",
66        "UMask": "0x1"
67    },
68    {
69        "BriefDescription": "Branch instructions decoded",
70        "EventCode": "0xE0",
71        "EventName": "BR_INST_DECODED",
72        "SampleAfterValue": "2000000",
73        "UMask": "0x1"
74    },
75    {
76        "BriefDescription": "Branch instructions executed",
77        "EventCode": "0x88",
78        "EventName": "BR_INST_EXEC.ANY",
79        "SampleAfterValue": "200000",
80        "UMask": "0x7f"
81    },
82    {
83        "BriefDescription": "Conditional branch instructions executed",
84        "EventCode": "0x88",
85        "EventName": "BR_INST_EXEC.COND",
86        "SampleAfterValue": "200000",
87        "UMask": "0x1"
88    },
89    {
90        "BriefDescription": "Unconditional branches executed",
91        "EventCode": "0x88",
92        "EventName": "BR_INST_EXEC.DIRECT",
93        "SampleAfterValue": "200000",
94        "UMask": "0x2"
95    },
96    {
97        "BriefDescription": "Unconditional call branches executed",
98        "EventCode": "0x88",
99        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
100        "SampleAfterValue": "20000",
101        "UMask": "0x10"
102    },
103    {
104        "BriefDescription": "Indirect call branches executed",
105        "EventCode": "0x88",
106        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
107        "SampleAfterValue": "20000",
108        "UMask": "0x20"
109    },
110    {
111        "BriefDescription": "Indirect non call branches executed",
112        "EventCode": "0x88",
113        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
114        "SampleAfterValue": "20000",
115        "UMask": "0x4"
116    },
117    {
118        "BriefDescription": "Call branches executed",
119        "EventCode": "0x88",
120        "EventName": "BR_INST_EXEC.NEAR_CALLS",
121        "SampleAfterValue": "20000",
122        "UMask": "0x30"
123    },
124    {
125        "BriefDescription": "All non call branches executed",
126        "EventCode": "0x88",
127        "EventName": "BR_INST_EXEC.NON_CALLS",
128        "SampleAfterValue": "200000",
129        "UMask": "0x7"
130    },
131    {
132        "BriefDescription": "Indirect return branches executed",
133        "EventCode": "0x88",
134        "EventName": "BR_INST_EXEC.RETURN_NEAR",
135        "SampleAfterValue": "20000",
136        "UMask": "0x8"
137    },
138    {
139        "BriefDescription": "Taken branches executed",
140        "EventCode": "0x88",
141        "EventName": "BR_INST_EXEC.TAKEN",
142        "SampleAfterValue": "200000",
143        "UMask": "0x40"
144    },
145    {
146        "BriefDescription": "Retired branch instructions (Precise Event)",
147        "EventCode": "0xC4",
148        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
149        "PEBS": "1",
150        "SampleAfterValue": "200000",
151        "UMask": "0x4"
152    },
153    {
154        "BriefDescription": "Retired conditional branch instructions (Precise Event)",
155        "EventCode": "0xC4",
156        "EventName": "BR_INST_RETIRED.CONDITIONAL",
157        "PEBS": "1",
158        "SampleAfterValue": "200000",
159        "UMask": "0x1"
160    },
161    {
162        "BriefDescription": "Retired near call instructions (Precise Event)",
163        "EventCode": "0xC4",
164        "EventName": "BR_INST_RETIRED.NEAR_CALL",
165        "PEBS": "1",
166        "SampleAfterValue": "20000",
167        "UMask": "0x2"
168    },
169    {
170        "BriefDescription": "Mispredicted branches executed",
171        "EventCode": "0x89",
172        "EventName": "BR_MISP_EXEC.ANY",
173        "SampleAfterValue": "20000",
174        "UMask": "0x7f"
175    },
176    {
177        "BriefDescription": "Mispredicted conditional branches executed",
178        "EventCode": "0x89",
179        "EventName": "BR_MISP_EXEC.COND",
180        "SampleAfterValue": "20000",
181        "UMask": "0x1"
182    },
183    {
184        "BriefDescription": "Mispredicted unconditional branches executed",
185        "EventCode": "0x89",
186        "EventName": "BR_MISP_EXEC.DIRECT",
187        "SampleAfterValue": "20000",
188        "UMask": "0x2"
189    },
190    {
191        "BriefDescription": "Mispredicted non call branches executed",
192        "EventCode": "0x89",
193        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
194        "SampleAfterValue": "2000",
195        "UMask": "0x10"
196    },
197    {
198        "BriefDescription": "Mispredicted indirect call branches executed",
199        "EventCode": "0x89",
200        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
201        "SampleAfterValue": "2000",
202        "UMask": "0x20"
203    },
204    {
205        "BriefDescription": "Mispredicted indirect non call branches executed",
206        "EventCode": "0x89",
207        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
208        "SampleAfterValue": "2000",
209        "UMask": "0x4"
210    },
211    {
212        "BriefDescription": "Mispredicted call branches executed",
213        "EventCode": "0x89",
214        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
215        "SampleAfterValue": "2000",
216        "UMask": "0x30"
217    },
218    {
219        "BriefDescription": "Mispredicted non call branches executed",
220        "EventCode": "0x89",
221        "EventName": "BR_MISP_EXEC.NON_CALLS",
222        "SampleAfterValue": "20000",
223        "UMask": "0x7"
224    },
225    {
226        "BriefDescription": "Mispredicted return branches executed",
227        "EventCode": "0x89",
228        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
229        "SampleAfterValue": "2000",
230        "UMask": "0x8"
231    },
232    {
233        "BriefDescription": "Mispredicted taken branches executed",
234        "EventCode": "0x89",
235        "EventName": "BR_MISP_EXEC.TAKEN",
236        "SampleAfterValue": "20000",
237        "UMask": "0x40"
238    },
239    {
240        "BriefDescription": "Mispredicted near retired calls (Precise Event)",
241        "EventCode": "0xC5",
242        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
243        "PEBS": "1",
244        "SampleAfterValue": "2000",
245        "UMask": "0x2"
246    },
247    {
248        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
249        "EventName": "CPU_CLK_UNHALTED.REF",
250        "SampleAfterValue": "2000000"
251    },
252    {
253        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
254        "EventCode": "0x3C",
255        "EventName": "CPU_CLK_UNHALTED.REF_P",
256        "SampleAfterValue": "100000",
257        "UMask": "0x1"
258    },
259    {
260        "BriefDescription": "Cycles when thread is not halted (fixed counter)",
261        "EventName": "CPU_CLK_UNHALTED.THREAD",
262        "SampleAfterValue": "2000000"
263    },
264    {
265        "BriefDescription": "Cycles when thread is not halted (programmable counter)",
266        "EventCode": "0x3C",
267        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
268        "SampleAfterValue": "2000000"
269    },
270    {
271        "BriefDescription": "Total CPU cycles",
272        "CounterMask": "2",
273        "EventCode": "0x3C",
274        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
275        "Invert": "1",
276        "SampleAfterValue": "2000000"
277    },
278    {
279        "BriefDescription": "Any Instruction Length Decoder stall cycles",
280        "EventCode": "0x87",
281        "EventName": "ILD_STALL.ANY",
282        "SampleAfterValue": "2000000",
283        "UMask": "0xf"
284    },
285    {
286        "BriefDescription": "Instruction Queue full stall cycles",
287        "EventCode": "0x87",
288        "EventName": "ILD_STALL.IQ_FULL",
289        "SampleAfterValue": "2000000",
290        "UMask": "0x4"
291    },
292    {
293        "BriefDescription": "Length Change Prefix stall cycles",
294        "EventCode": "0x87",
295        "EventName": "ILD_STALL.LCP",
296        "SampleAfterValue": "2000000",
297        "UMask": "0x1"
298    },
299    {
300        "BriefDescription": "Stall cycles due to BPU MRU bypass",
301        "EventCode": "0x87",
302        "EventName": "ILD_STALL.MRU",
303        "SampleAfterValue": "2000000",
304        "UMask": "0x2"
305    },
306    {
307        "BriefDescription": "Regen stall cycles",
308        "EventCode": "0x87",
309        "EventName": "ILD_STALL.REGEN",
310        "SampleAfterValue": "2000000",
311        "UMask": "0x8"
312    },
313    {
314        "BriefDescription": "Instructions that must be decoded by decoder 0",
315        "EventCode": "0x18",
316        "EventName": "INST_DECODED.DEC0",
317        "SampleAfterValue": "2000000",
318        "UMask": "0x1"
319    },
320    {
321        "BriefDescription": "Instructions written to instruction queue.",
322        "EventCode": "0x17",
323        "EventName": "INST_QUEUE_WRITES",
324        "SampleAfterValue": "2000000",
325        "UMask": "0x1"
326    },
327    {
328        "BriefDescription": "Cycles instructions are written to the instruction queue",
329        "EventCode": "0x1E",
330        "EventName": "INST_QUEUE_WRITE_CYCLES",
331        "SampleAfterValue": "2000000",
332        "UMask": "0x1"
333    },
334    {
335        "BriefDescription": "Instructions retired (fixed counter)",
336        "EventName": "INST_RETIRED.ANY",
337        "SampleAfterValue": "2000000"
338    },
339    {
340        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
341        "EventCode": "0xC0",
342        "EventName": "INST_RETIRED.ANY_P",
343        "PEBS": "1",
344        "SampleAfterValue": "2000000",
345        "UMask": "0x1"
346    },
347    {
348        "BriefDescription": "Retired MMX instructions (Precise Event)",
349        "EventCode": "0xC0",
350        "EventName": "INST_RETIRED.MMX",
351        "PEBS": "1",
352        "SampleAfterValue": "2000000",
353        "UMask": "0x4"
354    },
355    {
356        "BriefDescription": "Total cycles (Precise Event)",
357        "CounterMask": "16",
358        "EventCode": "0xC0",
359        "EventName": "INST_RETIRED.TOTAL_CYCLES",
360        "Invert": "1",
361        "PEBS": "1",
362        "SampleAfterValue": "2000000",
363        "UMask": "0x1"
364    },
365    {
366        "BriefDescription": "Total cycles (Precise Event)",
367        "CounterMask": "16",
368        "EventCode": "0xC0",
369        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
370        "Invert": "1",
371        "PEBS": "2",
372        "SampleAfterValue": "2000000",
373        "UMask": "0x1"
374    },
375    {
376        "BriefDescription": "Retired floating-point operations (Precise Event)",
377        "EventCode": "0xC0",
378        "EventName": "INST_RETIRED.X87",
379        "PEBS": "1",
380        "SampleAfterValue": "2000000",
381        "UMask": "0x2"
382    },
383    {
384        "BriefDescription": "Load operations conflicting with software prefetches",
385        "EventCode": "0x4C",
386        "EventName": "LOAD_HIT_PRE",
387        "SampleAfterValue": "200000",
388        "UMask": "0x1"
389    },
390    {
391        "BriefDescription": "Cycles when uops were delivered by the LSD",
392        "CounterMask": "1",
393        "EventCode": "0xA8",
394        "EventName": "LSD.ACTIVE",
395        "SampleAfterValue": "2000000",
396        "UMask": "0x1"
397    },
398    {
399        "BriefDescription": "Cycles no uops were delivered by the LSD",
400        "CounterMask": "1",
401        "EventCode": "0xA8",
402        "EventName": "LSD.INACTIVE",
403        "Invert": "1",
404        "SampleAfterValue": "2000000",
405        "UMask": "0x1"
406    },
407    {
408        "BriefDescription": "Loops that can't stream from the instruction queue",
409        "EventCode": "0x20",
410        "EventName": "LSD_OVERFLOW",
411        "SampleAfterValue": "2000000",
412        "UMask": "0x1"
413    },
414    {
415        "BriefDescription": "Cycles machine clear asserted",
416        "EventCode": "0xC3",
417        "EventName": "MACHINE_CLEARS.CYCLES",
418        "SampleAfterValue": "20000",
419        "UMask": "0x1"
420    },
421    {
422        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
423        "EventCode": "0xC3",
424        "EventName": "MACHINE_CLEARS.MEM_ORDER",
425        "SampleAfterValue": "20000",
426        "UMask": "0x2"
427    },
428    {
429        "BriefDescription": "Self-Modifying Code detected",
430        "EventCode": "0xC3",
431        "EventName": "MACHINE_CLEARS.SMC",
432        "SampleAfterValue": "20000",
433        "UMask": "0x4"
434    },
435    {
436        "BriefDescription": "All RAT stall cycles",
437        "EventCode": "0xD2",
438        "EventName": "RAT_STALLS.ANY",
439        "SampleAfterValue": "2000000",
440        "UMask": "0xf"
441    },
442    {
443        "BriefDescription": "Flag stall cycles",
444        "EventCode": "0xD2",
445        "EventName": "RAT_STALLS.FLAGS",
446        "SampleAfterValue": "2000000",
447        "UMask": "0x1"
448    },
449    {
450        "BriefDescription": "Partial register stall cycles",
451        "EventCode": "0xD2",
452        "EventName": "RAT_STALLS.REGISTERS",
453        "SampleAfterValue": "2000000",
454        "UMask": "0x2"
455    },
456    {
457        "BriefDescription": "ROB read port stalls cycles",
458        "EventCode": "0xD2",
459        "EventName": "RAT_STALLS.ROB_READ_PORT",
460        "SampleAfterValue": "2000000",
461        "UMask": "0x4"
462    },
463    {
464        "BriefDescription": "Scoreboard stall cycles",
465        "EventCode": "0xD2",
466        "EventName": "RAT_STALLS.SCOREBOARD",
467        "SampleAfterValue": "2000000",
468        "UMask": "0x8"
469    },
470    {
471        "BriefDescription": "Resource related stall cycles",
472        "EventCode": "0xA2",
473        "EventName": "RESOURCE_STALLS.ANY",
474        "SampleAfterValue": "2000000",
475        "UMask": "0x1"
476    },
477    {
478        "BriefDescription": "FPU control word write stall cycles",
479        "EventCode": "0xA2",
480        "EventName": "RESOURCE_STALLS.FPCW",
481        "SampleAfterValue": "2000000",
482        "UMask": "0x20"
483    },
484    {
485        "BriefDescription": "Load buffer stall cycles",
486        "EventCode": "0xA2",
487        "EventName": "RESOURCE_STALLS.LOAD",
488        "SampleAfterValue": "2000000",
489        "UMask": "0x2"
490    },
491    {
492        "BriefDescription": "MXCSR rename stall cycles",
493        "EventCode": "0xA2",
494        "EventName": "RESOURCE_STALLS.MXCSR",
495        "SampleAfterValue": "2000000",
496        "UMask": "0x40"
497    },
498    {
499        "BriefDescription": "Other Resource related stall cycles",
500        "EventCode": "0xA2",
501        "EventName": "RESOURCE_STALLS.OTHER",
502        "SampleAfterValue": "2000000",
503        "UMask": "0x80"
504    },
505    {
506        "BriefDescription": "ROB full stall cycles",
507        "EventCode": "0xA2",
508        "EventName": "RESOURCE_STALLS.ROB_FULL",
509        "SampleAfterValue": "2000000",
510        "UMask": "0x10"
511    },
512    {
513        "BriefDescription": "Reservation Station full stall cycles",
514        "EventCode": "0xA2",
515        "EventName": "RESOURCE_STALLS.RS_FULL",
516        "SampleAfterValue": "2000000",
517        "UMask": "0x4"
518    },
519    {
520        "BriefDescription": "Store buffer stall cycles",
521        "EventCode": "0xA2",
522        "EventName": "RESOURCE_STALLS.STORE",
523        "SampleAfterValue": "2000000",
524        "UMask": "0x8"
525    },
526    {
527        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
528        "EventCode": "0xC7",
529        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
530        "PEBS": "1",
531        "SampleAfterValue": "200000",
532        "UMask": "0x4"
533    },
534    {
535        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
536        "EventCode": "0xC7",
537        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
538        "PEBS": "1",
539        "SampleAfterValue": "200000",
540        "UMask": "0x1"
541    },
542    {
543        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
544        "EventCode": "0xC7",
545        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
546        "PEBS": "1",
547        "SampleAfterValue": "200000",
548        "UMask": "0x8"
549    },
550    {
551        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
552        "EventCode": "0xC7",
553        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
554        "PEBS": "1",
555        "SampleAfterValue": "200000",
556        "UMask": "0x2"
557    },
558    {
559        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
560        "EventCode": "0xC7",
561        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
562        "PEBS": "1",
563        "SampleAfterValue": "200000",
564        "UMask": "0x10"
565    },
566    {
567        "BriefDescription": "Stack pointer instructions decoded",
568        "EventCode": "0xD1",
569        "EventName": "UOPS_DECODED.ESP_FOLDING",
570        "SampleAfterValue": "2000000",
571        "UMask": "0x4"
572    },
573    {
574        "BriefDescription": "Stack pointer sync operations",
575        "EventCode": "0xD1",
576        "EventName": "UOPS_DECODED.ESP_SYNC",
577        "SampleAfterValue": "2000000",
578        "UMask": "0x8"
579    },
580    {
581        "BriefDescription": "Uops decoded by Microcode Sequencer",
582        "CounterMask": "1",
583        "EventCode": "0xD1",
584        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
585        "SampleAfterValue": "2000000",
586        "UMask": "0x2"
587    },
588    {
589        "BriefDescription": "Cycles no Uops are decoded",
590        "CounterMask": "1",
591        "EventCode": "0xD1",
592        "EventName": "UOPS_DECODED.STALL_CYCLES",
593        "Invert": "1",
594        "SampleAfterValue": "2000000",
595        "UMask": "0x1"
596    },
597    {
598        "AnyThread": "1",
599        "BriefDescription": "Cycles Uops executed on any port (core count)",
600        "CounterMask": "1",
601        "EventCode": "0xB1",
602        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
603        "SampleAfterValue": "2000000",
604        "UMask": "0x3f"
605    },
606    {
607        "AnyThread": "1",
608        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
609        "CounterMask": "1",
610        "EventCode": "0xB1",
611        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
612        "SampleAfterValue": "2000000",
613        "UMask": "0x1f"
614    },
615    {
616        "AnyThread": "1",
617        "BriefDescription": "Uops executed on any port (core count)",
618        "CounterMask": "1",
619        "EdgeDetect": "1",
620        "EventCode": "0xB1",
621        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
622        "Invert": "1",
623        "SampleAfterValue": "2000000",
624        "UMask": "0x3f"
625    },
626    {
627        "AnyThread": "1",
628        "BriefDescription": "Uops executed on ports 0-4 (core count)",
629        "CounterMask": "1",
630        "EdgeDetect": "1",
631        "EventCode": "0xB1",
632        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
633        "Invert": "1",
634        "SampleAfterValue": "2000000",
635        "UMask": "0x1f"
636    },
637    {
638        "AnyThread": "1",
639        "BriefDescription": "Cycles no Uops issued on any port (core count)",
640        "CounterMask": "1",
641        "EventCode": "0xB1",
642        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
643        "Invert": "1",
644        "SampleAfterValue": "2000000",
645        "UMask": "0x3f"
646    },
647    {
648        "AnyThread": "1",
649        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
650        "CounterMask": "1",
651        "EventCode": "0xB1",
652        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
653        "Invert": "1",
654        "SampleAfterValue": "2000000",
655        "UMask": "0x1f"
656    },
657    {
658        "BriefDescription": "Uops executed on port 0",
659        "EventCode": "0xB1",
660        "EventName": "UOPS_EXECUTED.PORT0",
661        "SampleAfterValue": "2000000",
662        "UMask": "0x1"
663    },
664    {
665        "BriefDescription": "Uops issued on ports 0, 1 or 5",
666        "EventCode": "0xB1",
667        "EventName": "UOPS_EXECUTED.PORT015",
668        "SampleAfterValue": "2000000",
669        "UMask": "0x40"
670    },
671    {
672        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
673        "CounterMask": "1",
674        "EventCode": "0xB1",
675        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
676        "Invert": "1",
677        "SampleAfterValue": "2000000",
678        "UMask": "0x40"
679    },
680    {
681        "BriefDescription": "Uops executed on port 1",
682        "EventCode": "0xB1",
683        "EventName": "UOPS_EXECUTED.PORT1",
684        "SampleAfterValue": "2000000",
685        "UMask": "0x2"
686    },
687    {
688        "AnyThread": "1",
689        "BriefDescription": "Uops issued on ports 2, 3 or 4",
690        "EventCode": "0xB1",
691        "EventName": "UOPS_EXECUTED.PORT234_CORE",
692        "SampleAfterValue": "2000000",
693        "UMask": "0x80"
694    },
695    {
696        "AnyThread": "1",
697        "BriefDescription": "Uops executed on port 2 (core count)",
698        "EventCode": "0xB1",
699        "EventName": "UOPS_EXECUTED.PORT2_CORE",
700        "SampleAfterValue": "2000000",
701        "UMask": "0x4"
702    },
703    {
704        "AnyThread": "1",
705        "BriefDescription": "Uops executed on port 3 (core count)",
706        "EventCode": "0xB1",
707        "EventName": "UOPS_EXECUTED.PORT3_CORE",
708        "SampleAfterValue": "2000000",
709        "UMask": "0x8"
710    },
711    {
712        "AnyThread": "1",
713        "BriefDescription": "Uops executed on port 4 (core count)",
714        "EventCode": "0xB1",
715        "EventName": "UOPS_EXECUTED.PORT4_CORE",
716        "SampleAfterValue": "2000000",
717        "UMask": "0x10"
718    },
719    {
720        "BriefDescription": "Uops executed on port 5",
721        "EventCode": "0xB1",
722        "EventName": "UOPS_EXECUTED.PORT5",
723        "SampleAfterValue": "2000000",
724        "UMask": "0x20"
725    },
726    {
727        "BriefDescription": "Uops issued",
728        "EventCode": "0xE",
729        "EventName": "UOPS_ISSUED.ANY",
730        "SampleAfterValue": "2000000",
731        "UMask": "0x1"
732    },
733    {
734        "AnyThread": "1",
735        "BriefDescription": "Cycles no Uops were issued on any thread",
736        "CounterMask": "1",
737        "EventCode": "0xE",
738        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
739        "Invert": "1",
740        "SampleAfterValue": "2000000",
741        "UMask": "0x1"
742    },
743    {
744        "AnyThread": "1",
745        "BriefDescription": "Cycles Uops were issued on either thread",
746        "CounterMask": "1",
747        "EventCode": "0xE",
748        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
749        "SampleAfterValue": "2000000",
750        "UMask": "0x1"
751    },
752    {
753        "BriefDescription": "Fused Uops issued",
754        "EventCode": "0xE",
755        "EventName": "UOPS_ISSUED.FUSED",
756        "SampleAfterValue": "2000000",
757        "UMask": "0x2"
758    },
759    {
760        "BriefDescription": "Cycles no Uops were issued",
761        "CounterMask": "1",
762        "EventCode": "0xE",
763        "EventName": "UOPS_ISSUED.STALL_CYCLES",
764        "Invert": "1",
765        "SampleAfterValue": "2000000",
766        "UMask": "0x1"
767    },
768    {
769        "BriefDescription": "Cycles Uops are being retired",
770        "CounterMask": "1",
771        "EventCode": "0xC2",
772        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
773        "PEBS": "1",
774        "SampleAfterValue": "2000000",
775        "UMask": "0x1"
776    },
777    {
778        "BriefDescription": "Uops retired (Precise Event)",
779        "EventCode": "0xC2",
780        "EventName": "UOPS_RETIRED.ANY",
781        "PEBS": "1",
782        "SampleAfterValue": "2000000",
783        "UMask": "0x1"
784    },
785    {
786        "BriefDescription": "Macro-fused Uops retired (Precise Event)",
787        "EventCode": "0xC2",
788        "EventName": "UOPS_RETIRED.MACRO_FUSED",
789        "PEBS": "1",
790        "SampleAfterValue": "2000000",
791        "UMask": "0x4"
792    },
793    {
794        "BriefDescription": "Retirement slots used (Precise Event)",
795        "EventCode": "0xC2",
796        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
797        "PEBS": "1",
798        "SampleAfterValue": "2000000",
799        "UMask": "0x2"
800    },
801    {
802        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
803        "CounterMask": "1",
804        "EventCode": "0xC2",
805        "EventName": "UOPS_RETIRED.STALL_CYCLES",
806        "Invert": "1",
807        "PEBS": "1",
808        "SampleAfterValue": "2000000",
809        "UMask": "0x1"
810    },
811    {
812        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
813        "CounterMask": "16",
814        "EventCode": "0xC2",
815        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
816        "Invert": "1",
817        "PEBS": "1",
818        "SampleAfterValue": "2000000",
819        "UMask": "0x1"
820    },
821    {
822        "BriefDescription": "Uop unfusions due to FP exceptions",
823        "EventCode": "0xDB",
824        "EventName": "UOP_UNFUSION",
825        "SampleAfterValue": "2000000",
826        "UMask": "0x1"
827    }
828]
829