xref: /linux/tools/perf/pmu-events/arch/x86/nehalemex/other.json (revision 96ac6d435100450f0565708d9b885ea2a7400e0a) 
1[
2    {
3        "EventCode": "0xE8",
4        "Counter": "0,1,2,3",
5        "UMask": "0x1",
6        "EventName": "BPU_CLEARS.EARLY",
7        "SampleAfterValue": "2000000",
8        "BriefDescription": "Early Branch Prediciton Unit clears"
9    },
10    {
11        "EventCode": "0xE8",
12        "Counter": "0,1,2,3",
13        "UMask": "0x2",
14        "EventName": "BPU_CLEARS.LATE",
15        "SampleAfterValue": "2000000",
16        "BriefDescription": "Late Branch Prediction Unit clears"
17    },
18    {
19        "EventCode": "0xE5",
20        "Counter": "0,1,2,3",
21        "UMask": "0x1",
22        "EventName": "BPU_MISSED_CALL_RET",
23        "SampleAfterValue": "2000000",
24        "BriefDescription": "Branch prediction unit missed call or return"
25    },
26    {
27        "EventCode": "0xD5",
28        "Counter": "0,1,2,3",
29        "UMask": "0x1",
30        "EventName": "ES_REG_RENAMES",
31        "SampleAfterValue": "2000000",
32        "BriefDescription": "ES segment renames"
33    },
34    {
35        "EventCode": "0x6C",
36        "Counter": "0,1,2,3",
37        "UMask": "0x1",
38        "EventName": "IO_TRANSACTIONS",
39        "SampleAfterValue": "2000000",
40        "BriefDescription": "I/O transactions"
41    },
42    {
43        "EventCode": "0x80",
44        "Counter": "0,1,2,3",
45        "UMask": "0x4",
46        "EventName": "L1I.CYCLES_STALLED",
47        "SampleAfterValue": "2000000",
48        "BriefDescription": "L1I instruction fetch stall cycles"
49    },
50    {
51        "EventCode": "0x80",
52        "Counter": "0,1,2,3",
53        "UMask": "0x1",
54        "EventName": "L1I.HITS",
55        "SampleAfterValue": "2000000",
56        "BriefDescription": "L1I instruction fetch hits"
57    },
58    {
59        "EventCode": "0x80",
60        "Counter": "0,1,2,3",
61        "UMask": "0x2",
62        "EventName": "L1I.MISSES",
63        "SampleAfterValue": "2000000",
64        "BriefDescription": "L1I instruction fetch misses"
65    },
66    {
67        "EventCode": "0x80",
68        "Counter": "0,1,2,3",
69        "UMask": "0x3",
70        "EventName": "L1I.READS",
71        "SampleAfterValue": "2000000",
72        "BriefDescription": "L1I Instruction fetches"
73    },
74    {
75        "EventCode": "0x82",
76        "Counter": "0,1,2,3",
77        "UMask": "0x1",
78        "EventName": "LARGE_ITLB.HIT",
79        "SampleAfterValue": "200000",
80        "BriefDescription": "Large ITLB hit"
81    },
82    {
83        "EventCode": "0x13",
84        "Counter": "0,1,2,3",
85        "UMask": "0x7",
86        "EventName": "LOAD_DISPATCH.ANY",
87        "SampleAfterValue": "2000000",
88        "BriefDescription": "All loads dispatched"
89    },
90    {
91        "EventCode": "0x13",
92        "Counter": "0,1,2,3",
93        "UMask": "0x4",
94        "EventName": "LOAD_DISPATCH.MOB",
95        "SampleAfterValue": "2000000",
96        "BriefDescription": "Loads dispatched from the MOB"
97    },
98    {
99        "EventCode": "0x13",
100        "Counter": "0,1,2,3",
101        "UMask": "0x1",
102        "EventName": "LOAD_DISPATCH.RS",
103        "SampleAfterValue": "2000000",
104        "BriefDescription": "Loads dispatched that bypass the MOB"
105    },
106    {
107        "EventCode": "0x13",
108        "Counter": "0,1,2,3",
109        "UMask": "0x2",
110        "EventName": "LOAD_DISPATCH.RS_DELAYED",
111        "SampleAfterValue": "2000000",
112        "BriefDescription": "Loads dispatched from stage 305"
113    },
114    {
115        "EventCode": "0x7",
116        "Counter": "0,1,2,3",
117        "UMask": "0x1",
118        "EventName": "PARTIAL_ADDRESS_ALIAS",
119        "SampleAfterValue": "200000",
120        "BriefDescription": "False dependencies due to partial address aliasing"
121    },
122    {
123        "EventCode": "0xD2",
124        "Counter": "0,1,2,3",
125        "UMask": "0xf",
126        "EventName": "RAT_STALLS.ANY",
127        "SampleAfterValue": "2000000",
128        "BriefDescription": "All RAT stall cycles"
129    },
130    {
131        "EventCode": "0xD2",
132        "Counter": "0,1,2,3",
133        "UMask": "0x1",
134        "EventName": "RAT_STALLS.FLAGS",
135        "SampleAfterValue": "2000000",
136        "BriefDescription": "Flag stall cycles"
137    },
138    {
139        "EventCode": "0xD2",
140        "Counter": "0,1,2,3",
141        "UMask": "0x2",
142        "EventName": "RAT_STALLS.REGISTERS",
143        "SampleAfterValue": "2000000",
144        "BriefDescription": "Partial register stall cycles"
145    },
146    {
147        "EventCode": "0xD2",
148        "Counter": "0,1,2,3",
149        "UMask": "0x4",
150        "EventName": "RAT_STALLS.ROB_READ_PORT",
151        "SampleAfterValue": "2000000",
152        "BriefDescription": "ROB read port stalls cycles"
153    },
154    {
155        "EventCode": "0xD2",
156        "Counter": "0,1,2,3",
157        "UMask": "0x8",
158        "EventName": "RAT_STALLS.SCOREBOARD",
159        "SampleAfterValue": "2000000",
160        "BriefDescription": "Scoreboard stall cycles"
161    },
162    {
163        "EventCode": "0x4",
164        "Counter": "0,1,2,3",
165        "UMask": "0x7",
166        "EventName": "SB_DRAIN.ANY",
167        "SampleAfterValue": "200000",
168        "BriefDescription": "All Store buffer stall cycles"
169    },
170    {
171        "EventCode": "0xD4",
172        "Counter": "0,1,2,3",
173        "UMask": "0x1",
174        "EventName": "SEG_RENAME_STALLS",
175        "SampleAfterValue": "2000000",
176        "BriefDescription": "Segment rename stall cycles"
177    },
178    {
179        "EventCode": "0xB8",
180        "Counter": "0,1,2,3",
181        "UMask": "0x1",
182        "EventName": "SNOOP_RESPONSE.HIT",
183        "SampleAfterValue": "100000",
184        "BriefDescription": "Thread responded HIT to snoop"
185    },
186    {
187        "EventCode": "0xB8",
188        "Counter": "0,1,2,3",
189        "UMask": "0x2",
190        "EventName": "SNOOP_RESPONSE.HITE",
191        "SampleAfterValue": "100000",
192        "BriefDescription": "Thread responded HITE to snoop"
193    },
194    {
195        "EventCode": "0xB8",
196        "Counter": "0,1,2,3",
197        "UMask": "0x4",
198        "EventName": "SNOOP_RESPONSE.HITM",
199        "SampleAfterValue": "100000",
200        "BriefDescription": "Thread responded HITM to snoop"
201    },
202    {
203        "EventCode": "0xF6",
204        "Counter": "0,1,2,3",
205        "UMask": "0x1",
206        "EventName": "SQ_FULL_STALL_CYCLES",
207        "SampleAfterValue": "2000000",
208        "BriefDescription": "Super Queue full stall cycles"
209    }
210]