1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "All references to the L1 data cache", 52 "Counter": "0,1", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.ANY", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1 data cacheable reads and writes", 60 "Counter": "0,1", 61 "EventCode": "0x43", 62 "EventName": "L1D_ALL_REF.CACHEABLE", 63 "SampleAfterValue": "2000000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1 data cache read in E state", 68 "Counter": "0,1", 69 "EventCode": "0x40", 70 "EventName": "L1D_CACHE_LD.E_STATE", 71 "SampleAfterValue": "2000000", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "L1 data cache read in I state (misses)", 76 "Counter": "0,1", 77 "EventCode": "0x40", 78 "EventName": "L1D_CACHE_LD.I_STATE", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "L1 data cache reads", 84 "Counter": "0,1", 85 "EventCode": "0x40", 86 "EventName": "L1D_CACHE_LD.MESI", 87 "SampleAfterValue": "2000000", 88 "UMask": "0xf" 89 }, 90 { 91 "BriefDescription": "L1 data cache read in M state", 92 "Counter": "0,1", 93 "EventCode": "0x40", 94 "EventName": "L1D_CACHE_LD.M_STATE", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x8" 97 }, 98 { 99 "BriefDescription": "L1 data cache read in S state", 100 "Counter": "0,1", 101 "EventCode": "0x40", 102 "EventName": "L1D_CACHE_LD.S_STATE", 103 "SampleAfterValue": "2000000", 104 "UMask": "0x2" 105 }, 106 { 107 "BriefDescription": "L1 data cache load locks in E state", 108 "Counter": "0,1", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.E_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x4" 113 }, 114 { 115 "BriefDescription": "L1 data cache load lock hits", 116 "Counter": "0,1", 117 "EventCode": "0x42", 118 "EventName": "L1D_CACHE_LOCK.HIT", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "L1 data cache load locks in M state", 124 "Counter": "0,1", 125 "EventCode": "0x42", 126 "EventName": "L1D_CACHE_LOCK.M_STATE", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x8" 129 }, 130 { 131 "BriefDescription": "L1 data cache load locks in S state", 132 "Counter": "0,1", 133 "EventCode": "0x42", 134 "EventName": "L1D_CACHE_LOCK.S_STATE", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x2" 137 }, 138 { 139 "BriefDescription": "L1D load lock accepted in fill buffer", 140 "Counter": "0,1", 141 "EventCode": "0x53", 142 "EventName": "L1D_CACHE_LOCK_FB_HIT", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 148 "Counter": "0,1", 149 "EventCode": "0x52", 150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "L1 data cache stores in E state", 156 "Counter": "0,1", 157 "EventCode": "0x41", 158 "EventName": "L1D_CACHE_ST.E_STATE", 159 "SampleAfterValue": "2000000", 160 "UMask": "0x4" 161 }, 162 { 163 "BriefDescription": "L1 data cache stores in M state", 164 "Counter": "0,1", 165 "EventCode": "0x41", 166 "EventName": "L1D_CACHE_ST.M_STATE", 167 "SampleAfterValue": "2000000", 168 "UMask": "0x8" 169 }, 170 { 171 "BriefDescription": "L1 data cache stores in S state", 172 "Counter": "0,1", 173 "EventCode": "0x41", 174 "EventName": "L1D_CACHE_ST.S_STATE", 175 "SampleAfterValue": "2000000", 176 "UMask": "0x2" 177 }, 178 { 179 "BriefDescription": "L1D hardware prefetch misses", 180 "Counter": "0,1", 181 "EventCode": "0x4E", 182 "EventName": "L1D_PREFETCH.MISS", 183 "SampleAfterValue": "200000", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "L1D hardware prefetch requests", 188 "Counter": "0,1", 189 "EventCode": "0x4E", 190 "EventName": "L1D_PREFETCH.REQUESTS", 191 "SampleAfterValue": "200000", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "L1D hardware prefetch requests triggered", 196 "Counter": "0,1", 197 "EventCode": "0x4E", 198 "EventName": "L1D_PREFETCH.TRIGGERS", 199 "SampleAfterValue": "200000", 200 "UMask": "0x4" 201 }, 202 { 203 "BriefDescription": "L1 writebacks to L2 in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x28", 206 "EventName": "L1D_WB_L2.E_STATE", 207 "SampleAfterValue": "100000", 208 "UMask": "0x4" 209 }, 210 { 211 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x28", 214 "EventName": "L1D_WB_L2.I_STATE", 215 "SampleAfterValue": "100000", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "All L1 writebacks to L2", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x28", 222 "EventName": "L1D_WB_L2.MESI", 223 "SampleAfterValue": "100000", 224 "UMask": "0xf" 225 }, 226 { 227 "BriefDescription": "L1 writebacks to L2 in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x28", 230 "EventName": "L1D_WB_L2.M_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x8" 233 }, 234 { 235 "BriefDescription": "L1 writebacks to L2 in S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x28", 238 "EventName": "L1D_WB_L2.S_STATE", 239 "SampleAfterValue": "100000", 240 "UMask": "0x2" 241 }, 242 { 243 "BriefDescription": "L1I instruction fetch stall cycles", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x80", 246 "EventName": "L1I.CYCLES_STALLED", 247 "SampleAfterValue": "2000000", 248 "UMask": "0x4" 249 }, 250 { 251 "BriefDescription": "L1I instruction fetch hits", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x80", 254 "EventName": "L1I.HITS", 255 "SampleAfterValue": "2000000", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "L1I instruction fetch misses", 260 "Counter": "0,1,2,3", 261 "EventCode": "0x80", 262 "EventName": "L1I.MISSES", 263 "SampleAfterValue": "2000000", 264 "UMask": "0x2" 265 }, 266 { 267 "BriefDescription": "L1I Instruction fetches", 268 "Counter": "0,1,2,3", 269 "EventCode": "0x80", 270 "EventName": "L1I.READS", 271 "SampleAfterValue": "2000000", 272 "UMask": "0x3" 273 }, 274 { 275 "BriefDescription": "All L2 data requests", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.ANY", 279 "SampleAfterValue": "200000", 280 "UMask": "0xff" 281 }, 282 { 283 "BriefDescription": "L2 data demand loads in E state", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x26", 286 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 287 "SampleAfterValue": "200000", 288 "UMask": "0x4" 289 }, 290 { 291 "BriefDescription": "L2 data demand loads in I state (misses)", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x26", 294 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 295 "SampleAfterValue": "200000", 296 "UMask": "0x1" 297 }, 298 { 299 "BriefDescription": "L2 data demand requests", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x26", 302 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 303 "SampleAfterValue": "200000", 304 "UMask": "0xf" 305 }, 306 { 307 "BriefDescription": "L2 data demand loads in M state", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x26", 310 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 311 "SampleAfterValue": "200000", 312 "UMask": "0x8" 313 }, 314 { 315 "BriefDescription": "L2 data demand loads in S state", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x26", 318 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 319 "SampleAfterValue": "200000", 320 "UMask": "0x2" 321 }, 322 { 323 "BriefDescription": "L2 data prefetches in E state", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x26", 326 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 327 "SampleAfterValue": "200000", 328 "UMask": "0x40" 329 }, 330 { 331 "BriefDescription": "L2 data prefetches in the I state (misses)", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x26", 334 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 335 "SampleAfterValue": "200000", 336 "UMask": "0x10" 337 }, 338 { 339 "BriefDescription": "All L2 data prefetches", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x26", 342 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 343 "SampleAfterValue": "200000", 344 "UMask": "0xf0" 345 }, 346 { 347 "BriefDescription": "L2 data prefetches in M state", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x26", 350 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "L2 data prefetches in the S state", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x26", 358 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 359 "SampleAfterValue": "200000", 360 "UMask": "0x20" 361 }, 362 { 363 "BriefDescription": "L2 lines allocated", 364 "Counter": "0,1,2,3", 365 "EventCode": "0xF1", 366 "EventName": "L2_LINES_IN.ANY", 367 "SampleAfterValue": "100000", 368 "UMask": "0x7" 369 }, 370 { 371 "BriefDescription": "L2 lines allocated in the E state", 372 "Counter": "0,1,2,3", 373 "EventCode": "0xF1", 374 "EventName": "L2_LINES_IN.E_STATE", 375 "SampleAfterValue": "100000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 lines allocated in the S state", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xF1", 382 "EventName": "L2_LINES_IN.S_STATE", 383 "SampleAfterValue": "100000", 384 "UMask": "0x2" 385 }, 386 { 387 "BriefDescription": "L2 lines evicted", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF2", 390 "EventName": "L2_LINES_OUT.ANY", 391 "SampleAfterValue": "100000", 392 "UMask": "0xf" 393 }, 394 { 395 "BriefDescription": "L2 lines evicted by a demand request", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF2", 398 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 399 "SampleAfterValue": "100000", 400 "UMask": "0x1" 401 }, 402 { 403 "BriefDescription": "L2 modified lines evicted by a demand request", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF2", 406 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 407 "SampleAfterValue": "100000", 408 "UMask": "0x2" 409 }, 410 { 411 "BriefDescription": "L2 lines evicted by a prefetch request", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF2", 414 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 415 "SampleAfterValue": "100000", 416 "UMask": "0x4" 417 }, 418 { 419 "BriefDescription": "L2 modified lines evicted by a prefetch request", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF2", 422 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 423 "SampleAfterValue": "100000", 424 "UMask": "0x8" 425 }, 426 { 427 "BriefDescription": "L2 instruction fetches", 428 "Counter": "0,1,2,3", 429 "EventCode": "0x24", 430 "EventName": "L2_RQSTS.IFETCHES", 431 "SampleAfterValue": "200000", 432 "UMask": "0x30" 433 }, 434 { 435 "BriefDescription": "L2 instruction fetch hits", 436 "Counter": "0,1,2,3", 437 "EventCode": "0x24", 438 "EventName": "L2_RQSTS.IFETCH_HIT", 439 "SampleAfterValue": "200000", 440 "UMask": "0x10" 441 }, 442 { 443 "BriefDescription": "L2 instruction fetch misses", 444 "Counter": "0,1,2,3", 445 "EventCode": "0x24", 446 "EventName": "L2_RQSTS.IFETCH_MISS", 447 "SampleAfterValue": "200000", 448 "UMask": "0x20" 449 }, 450 { 451 "BriefDescription": "L2 load hits", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x24", 454 "EventName": "L2_RQSTS.LD_HIT", 455 "SampleAfterValue": "200000", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "L2 load misses", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x24", 462 "EventName": "L2_RQSTS.LD_MISS", 463 "SampleAfterValue": "200000", 464 "UMask": "0x2" 465 }, 466 { 467 "BriefDescription": "L2 requests", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x24", 470 "EventName": "L2_RQSTS.LOADS", 471 "SampleAfterValue": "200000", 472 "UMask": "0x3" 473 }, 474 { 475 "BriefDescription": "All L2 misses", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x24", 478 "EventName": "L2_RQSTS.MISS", 479 "SampleAfterValue": "200000", 480 "UMask": "0xaa" 481 }, 482 { 483 "BriefDescription": "All L2 prefetches", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x24", 486 "EventName": "L2_RQSTS.PREFETCHES", 487 "SampleAfterValue": "200000", 488 "UMask": "0xc0" 489 }, 490 { 491 "BriefDescription": "L2 prefetch hits", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x24", 494 "EventName": "L2_RQSTS.PREFETCH_HIT", 495 "SampleAfterValue": "200000", 496 "UMask": "0x40" 497 }, 498 { 499 "BriefDescription": "L2 prefetch misses", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x24", 502 "EventName": "L2_RQSTS.PREFETCH_MISS", 503 "SampleAfterValue": "200000", 504 "UMask": "0x80" 505 }, 506 { 507 "BriefDescription": "All L2 requests", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x24", 510 "EventName": "L2_RQSTS.REFERENCES", 511 "SampleAfterValue": "200000", 512 "UMask": "0xff" 513 }, 514 { 515 "BriefDescription": "L2 RFO requests", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x24", 518 "EventName": "L2_RQSTS.RFOS", 519 "SampleAfterValue": "200000", 520 "UMask": "0xc" 521 }, 522 { 523 "BriefDescription": "L2 RFO hits", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x24", 526 "EventName": "L2_RQSTS.RFO_HIT", 527 "SampleAfterValue": "200000", 528 "UMask": "0x4" 529 }, 530 { 531 "BriefDescription": "L2 RFO misses", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x24", 534 "EventName": "L2_RQSTS.RFO_MISS", 535 "SampleAfterValue": "200000", 536 "UMask": "0x8" 537 }, 538 { 539 "BriefDescription": "All L2 transactions", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xF0", 542 "EventName": "L2_TRANSACTIONS.ANY", 543 "SampleAfterValue": "200000", 544 "UMask": "0x80" 545 }, 546 { 547 "BriefDescription": "L2 fill transactions", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xF0", 550 "EventName": "L2_TRANSACTIONS.FILL", 551 "SampleAfterValue": "200000", 552 "UMask": "0x20" 553 }, 554 { 555 "BriefDescription": "L2 instruction fetch transactions", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xF0", 558 "EventName": "L2_TRANSACTIONS.IFETCH", 559 "SampleAfterValue": "200000", 560 "UMask": "0x4" 561 }, 562 { 563 "BriefDescription": "L1D writeback to L2 transactions", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xF0", 566 "EventName": "L2_TRANSACTIONS.L1D_WB", 567 "SampleAfterValue": "200000", 568 "UMask": "0x10" 569 }, 570 { 571 "BriefDescription": "L2 Load transactions", 572 "Counter": "0,1,2,3", 573 "EventCode": "0xF0", 574 "EventName": "L2_TRANSACTIONS.LOAD", 575 "SampleAfterValue": "200000", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "L2 prefetch transactions", 580 "Counter": "0,1,2,3", 581 "EventCode": "0xF0", 582 "EventName": "L2_TRANSACTIONS.PREFETCH", 583 "SampleAfterValue": "200000", 584 "UMask": "0x8" 585 }, 586 { 587 "BriefDescription": "L2 RFO transactions", 588 "Counter": "0,1,2,3", 589 "EventCode": "0xF0", 590 "EventName": "L2_TRANSACTIONS.RFO", 591 "SampleAfterValue": "200000", 592 "UMask": "0x2" 593 }, 594 { 595 "BriefDescription": "L2 writeback to LLC transactions", 596 "Counter": "0,1,2,3", 597 "EventCode": "0xF0", 598 "EventName": "L2_TRANSACTIONS.WB", 599 "SampleAfterValue": "200000", 600 "UMask": "0x40" 601 }, 602 { 603 "BriefDescription": "L2 demand lock RFOs in E state", 604 "Counter": "0,1,2,3", 605 "EventCode": "0x27", 606 "EventName": "L2_WRITE.LOCK.E_STATE", 607 "SampleAfterValue": "100000", 608 "UMask": "0x40" 609 }, 610 { 611 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 612 "Counter": "0,1,2,3", 613 "EventCode": "0x27", 614 "EventName": "L2_WRITE.LOCK.HIT", 615 "SampleAfterValue": "100000", 616 "UMask": "0xe0" 617 }, 618 { 619 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 620 "Counter": "0,1,2,3", 621 "EventCode": "0x27", 622 "EventName": "L2_WRITE.LOCK.I_STATE", 623 "SampleAfterValue": "100000", 624 "UMask": "0x10" 625 }, 626 { 627 "BriefDescription": "All demand L2 lock RFOs", 628 "Counter": "0,1,2,3", 629 "EventCode": "0x27", 630 "EventName": "L2_WRITE.LOCK.MESI", 631 "SampleAfterValue": "100000", 632 "UMask": "0xf0" 633 }, 634 { 635 "BriefDescription": "L2 demand lock RFOs in M state", 636 "Counter": "0,1,2,3", 637 "EventCode": "0x27", 638 "EventName": "L2_WRITE.LOCK.M_STATE", 639 "SampleAfterValue": "100000", 640 "UMask": "0x80" 641 }, 642 { 643 "BriefDescription": "L2 demand lock RFOs in S state", 644 "Counter": "0,1,2,3", 645 "EventCode": "0x27", 646 "EventName": "L2_WRITE.LOCK.S_STATE", 647 "SampleAfterValue": "100000", 648 "UMask": "0x20" 649 }, 650 { 651 "BriefDescription": "All L2 demand store RFOs that hit the cache", 652 "Counter": "0,1,2,3", 653 "EventCode": "0x27", 654 "EventName": "L2_WRITE.RFO.HIT", 655 "SampleAfterValue": "100000", 656 "UMask": "0xe" 657 }, 658 { 659 "BriefDescription": "L2 demand store RFOs in I state (misses)", 660 "Counter": "0,1,2,3", 661 "EventCode": "0x27", 662 "EventName": "L2_WRITE.RFO.I_STATE", 663 "SampleAfterValue": "100000", 664 "UMask": "0x1" 665 }, 666 { 667 "BriefDescription": "All L2 demand store RFOs", 668 "Counter": "0,1,2,3", 669 "EventCode": "0x27", 670 "EventName": "L2_WRITE.RFO.MESI", 671 "SampleAfterValue": "100000", 672 "UMask": "0xf" 673 }, 674 { 675 "BriefDescription": "L2 demand store RFOs in M state", 676 "Counter": "0,1,2,3", 677 "EventCode": "0x27", 678 "EventName": "L2_WRITE.RFO.M_STATE", 679 "SampleAfterValue": "100000", 680 "UMask": "0x8" 681 }, 682 { 683 "BriefDescription": "L2 demand store RFOs in S state", 684 "Counter": "0,1,2,3", 685 "EventCode": "0x27", 686 "EventName": "L2_WRITE.RFO.S_STATE", 687 "SampleAfterValue": "100000", 688 "UMask": "0x2" 689 }, 690 { 691 "BriefDescription": "Longest latency cache miss", 692 "Counter": "0,1,2,3", 693 "EventCode": "0x2E", 694 "EventName": "LONGEST_LAT_CACHE.MISS", 695 "SampleAfterValue": "100000", 696 "UMask": "0x41" 697 }, 698 { 699 "BriefDescription": "Longest latency cache reference", 700 "Counter": "0,1,2,3", 701 "EventCode": "0x2E", 702 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 703 "SampleAfterValue": "200000", 704 "UMask": "0x4f" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 711 "MSRIndex": "0x3F6", 712 "PEBS": "2", 713 "SampleAfterValue": "2000000", 714 "UMask": "0x10" 715 }, 716 { 717 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 718 "Counter": "3", 719 "EventCode": "0xB", 720 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 721 "MSRIndex": "0x3F6", 722 "MSRValue": "0x400", 723 "PEBS": "2", 724 "SampleAfterValue": "100", 725 "UMask": "0x10" 726 }, 727 { 728 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 729 "Counter": "3", 730 "EventCode": "0xB", 731 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 732 "MSRIndex": "0x3F6", 733 "MSRValue": "0x80", 734 "PEBS": "2", 735 "SampleAfterValue": "1000", 736 "UMask": "0x10" 737 }, 738 { 739 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 740 "Counter": "3", 741 "EventCode": "0xB", 742 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 743 "MSRIndex": "0x3F6", 744 "MSRValue": "0x10", 745 "PEBS": "2", 746 "SampleAfterValue": "10000", 747 "UMask": "0x10" 748 }, 749 { 750 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 751 "Counter": "3", 752 "EventCode": "0xB", 753 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 754 "MSRIndex": "0x3F6", 755 "MSRValue": "0x4000", 756 "PEBS": "2", 757 "SampleAfterValue": "5", 758 "UMask": "0x10" 759 }, 760 { 761 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 762 "Counter": "3", 763 "EventCode": "0xB", 764 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 765 "MSRIndex": "0x3F6", 766 "MSRValue": "0x800", 767 "PEBS": "2", 768 "SampleAfterValue": "50", 769 "UMask": "0x10" 770 }, 771 { 772 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 773 "Counter": "3", 774 "EventCode": "0xB", 775 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 776 "MSRIndex": "0x3F6", 777 "MSRValue": "0x100", 778 "PEBS": "2", 779 "SampleAfterValue": "500", 780 "UMask": "0x10" 781 }, 782 { 783 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 784 "Counter": "3", 785 "EventCode": "0xB", 786 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 787 "MSRIndex": "0x3F6", 788 "MSRValue": "0x20", 789 "PEBS": "2", 790 "SampleAfterValue": "5000", 791 "UMask": "0x10" 792 }, 793 { 794 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 795 "Counter": "3", 796 "EventCode": "0xB", 797 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 798 "MSRIndex": "0x3F6", 799 "MSRValue": "0x8000", 800 "PEBS": "2", 801 "SampleAfterValue": "3", 802 "UMask": "0x10" 803 }, 804 { 805 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 806 "Counter": "3", 807 "EventCode": "0xB", 808 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 809 "MSRIndex": "0x3F6", 810 "MSRValue": "0x4", 811 "PEBS": "2", 812 "SampleAfterValue": "50000", 813 "UMask": "0x10" 814 }, 815 { 816 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 817 "Counter": "3", 818 "EventCode": "0xB", 819 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 820 "MSRIndex": "0x3F6", 821 "MSRValue": "0x1000", 822 "PEBS": "2", 823 "SampleAfterValue": "20", 824 "UMask": "0x10" 825 }, 826 { 827 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 828 "Counter": "3", 829 "EventCode": "0xB", 830 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 831 "MSRIndex": "0x3F6", 832 "MSRValue": "0x200", 833 "PEBS": "2", 834 "SampleAfterValue": "200", 835 "UMask": "0x10" 836 }, 837 { 838 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 839 "Counter": "3", 840 "EventCode": "0xB", 841 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 842 "MSRIndex": "0x3F6", 843 "MSRValue": "0x40", 844 "PEBS": "2", 845 "SampleAfterValue": "2000", 846 "UMask": "0x10" 847 }, 848 { 849 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 850 "Counter": "3", 851 "EventCode": "0xB", 852 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 853 "MSRIndex": "0x3F6", 854 "MSRValue": "0x8", 855 "PEBS": "2", 856 "SampleAfterValue": "20000", 857 "UMask": "0x10" 858 }, 859 { 860 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 861 "Counter": "3", 862 "EventCode": "0xB", 863 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 864 "MSRIndex": "0x3F6", 865 "MSRValue": "0x2000", 866 "PEBS": "2", 867 "SampleAfterValue": "10", 868 "UMask": "0x10" 869 }, 870 { 871 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 872 "Counter": "0,1,2,3", 873 "EventCode": "0xB", 874 "EventName": "MEM_INST_RETIRED.LOADS", 875 "PEBS": "1", 876 "SampleAfterValue": "2000000", 877 "UMask": "0x1" 878 }, 879 { 880 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 881 "Counter": "0,1,2,3", 882 "EventCode": "0xB", 883 "EventName": "MEM_INST_RETIRED.STORES", 884 "PEBS": "1", 885 "SampleAfterValue": "2000000", 886 "UMask": "0x2" 887 }, 888 { 889 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 890 "Counter": "0,1,2,3", 891 "EventCode": "0xCB", 892 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 893 "PEBS": "1", 894 "SampleAfterValue": "200000", 895 "UMask": "0x40" 896 }, 897 { 898 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 899 "Counter": "0,1,2,3", 900 "EventCode": "0xCB", 901 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 902 "PEBS": "1", 903 "SampleAfterValue": "2000000", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 908 "Counter": "0,1,2,3", 909 "EventCode": "0xCB", 910 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 911 "PEBS": "1", 912 "SampleAfterValue": "200000", 913 "UMask": "0x2" 914 }, 915 { 916 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 917 "Counter": "0,1,2,3", 918 "EventCode": "0xCB", 919 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 920 "PEBS": "1", 921 "SampleAfterValue": "10000", 922 "UMask": "0x10" 923 }, 924 { 925 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 926 "Counter": "0,1,2,3", 927 "EventCode": "0xCB", 928 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 929 "PEBS": "1", 930 "SampleAfterValue": "40000", 931 "UMask": "0x4" 932 }, 933 { 934 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 935 "Counter": "0,1,2,3", 936 "EventCode": "0xCB", 937 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 938 "PEBS": "1", 939 "SampleAfterValue": "40000", 940 "UMask": "0x8" 941 }, 942 { 943 "BriefDescription": "Offcore L1 data cache writebacks", 944 "Counter": "0,1,2,3", 945 "EventCode": "0xB0", 946 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 947 "SampleAfterValue": "100000", 948 "UMask": "0x40" 949 }, 950 { 951 "BriefDescription": "Offcore requests blocked due to Super Queue full", 952 "Counter": "0,1,2,3", 953 "EventCode": "0xB2", 954 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 955 "SampleAfterValue": "100000", 956 "UMask": "0x1" 957 }, 958 { 959 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 960 "Counter": "2", 961 "EventCode": "0xB7", 962 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 963 "MSRIndex": "0x1A6", 964 "MSRValue": "0x7F11", 965 "SampleAfterValue": "100000", 966 "UMask": "0x1" 967 }, 968 { 969 "BriefDescription": "All offcore data reads", 970 "Counter": "2", 971 "EventCode": "0xB7", 972 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 973 "MSRIndex": "0x1A6", 974 "MSRValue": "0xFF11", 975 "SampleAfterValue": "100000", 976 "UMask": "0x1" 977 }, 978 { 979 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 980 "Counter": "2", 981 "EventCode": "0xB7", 982 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 983 "MSRIndex": "0x1A6", 984 "MSRValue": "0x8011", 985 "SampleAfterValue": "100000", 986 "UMask": "0x1" 987 }, 988 { 989 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 990 "Counter": "2", 991 "EventCode": "0xB7", 992 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 993 "MSRIndex": "0x1A6", 994 "MSRValue": "0x111", 995 "SampleAfterValue": "100000", 996 "UMask": "0x1" 997 }, 998 { 999 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1000 "Counter": "2", 1001 "EventCode": "0xB7", 1002 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1003 "MSRIndex": "0x1A6", 1004 "MSRValue": "0x211", 1005 "SampleAfterValue": "100000", 1006 "UMask": "0x1" 1007 }, 1008 { 1009 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1010 "Counter": "2", 1011 "EventCode": "0xB7", 1012 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1013 "MSRIndex": "0x1A6", 1014 "MSRValue": "0x411", 1015 "SampleAfterValue": "100000", 1016 "UMask": "0x1" 1017 }, 1018 { 1019 "BriefDescription": "Offcore data reads satisfied by the LLC", 1020 "Counter": "2", 1021 "EventCode": "0xB7", 1022 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1023 "MSRIndex": "0x1A6", 1024 "MSRValue": "0x711", 1025 "SampleAfterValue": "100000", 1026 "UMask": "0x1" 1027 }, 1028 { 1029 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1030 "Counter": "2", 1031 "EventCode": "0xB7", 1032 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1033 "MSRIndex": "0x1A6", 1034 "MSRValue": "0x4711", 1035 "SampleAfterValue": "100000", 1036 "UMask": "0x1" 1037 }, 1038 { 1039 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1040 "Counter": "2", 1041 "EventCode": "0xB7", 1042 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1043 "MSRIndex": "0x1A6", 1044 "MSRValue": "0x1811", 1045 "SampleAfterValue": "100000", 1046 "UMask": "0x1" 1047 }, 1048 { 1049 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1050 "Counter": "2", 1051 "EventCode": "0xB7", 1052 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1053 "MSRIndex": "0x1A6", 1054 "MSRValue": "0x3811", 1055 "SampleAfterValue": "100000", 1056 "UMask": "0x1" 1057 }, 1058 { 1059 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1060 "Counter": "2", 1061 "EventCode": "0xB7", 1062 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1063 "MSRIndex": "0x1A6", 1064 "MSRValue": "0x1011", 1065 "SampleAfterValue": "100000", 1066 "UMask": "0x1" 1067 }, 1068 { 1069 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1070 "Counter": "2", 1071 "EventCode": "0xB7", 1072 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1073 "MSRIndex": "0x1A6", 1074 "MSRValue": "0x811", 1075 "SampleAfterValue": "100000", 1076 "UMask": "0x1" 1077 }, 1078 { 1079 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1080 "Counter": "2", 1081 "EventCode": "0xB7", 1082 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1083 "MSRIndex": "0x1A6", 1084 "MSRValue": "0x7F44", 1085 "SampleAfterValue": "100000", 1086 "UMask": "0x1" 1087 }, 1088 { 1089 "BriefDescription": "All offcore code reads", 1090 "Counter": "2", 1091 "EventCode": "0xB7", 1092 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1093 "MSRIndex": "0x1A6", 1094 "MSRValue": "0xFF44", 1095 "SampleAfterValue": "100000", 1096 "UMask": "0x1" 1097 }, 1098 { 1099 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1100 "Counter": "2", 1101 "EventCode": "0xB7", 1102 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1103 "MSRIndex": "0x1A6", 1104 "MSRValue": "0x8044", 1105 "SampleAfterValue": "100000", 1106 "UMask": "0x1" 1107 }, 1108 { 1109 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1110 "Counter": "2", 1111 "EventCode": "0xB7", 1112 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1113 "MSRIndex": "0x1A6", 1114 "MSRValue": "0x144", 1115 "SampleAfterValue": "100000", 1116 "UMask": "0x1" 1117 }, 1118 { 1119 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1120 "Counter": "2", 1121 "EventCode": "0xB7", 1122 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1123 "MSRIndex": "0x1A6", 1124 "MSRValue": "0x244", 1125 "SampleAfterValue": "100000", 1126 "UMask": "0x1" 1127 }, 1128 { 1129 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1130 "Counter": "2", 1131 "EventCode": "0xB7", 1132 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1133 "MSRIndex": "0x1A6", 1134 "MSRValue": "0x444", 1135 "SampleAfterValue": "100000", 1136 "UMask": "0x1" 1137 }, 1138 { 1139 "BriefDescription": "Offcore code reads satisfied by the LLC", 1140 "Counter": "2", 1141 "EventCode": "0xB7", 1142 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1143 "MSRIndex": "0x1A6", 1144 "MSRValue": "0x744", 1145 "SampleAfterValue": "100000", 1146 "UMask": "0x1" 1147 }, 1148 { 1149 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1150 "Counter": "2", 1151 "EventCode": "0xB7", 1152 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1153 "MSRIndex": "0x1A6", 1154 "MSRValue": "0x4744", 1155 "SampleAfterValue": "100000", 1156 "UMask": "0x1" 1157 }, 1158 { 1159 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1160 "Counter": "2", 1161 "EventCode": "0xB7", 1162 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1163 "MSRIndex": "0x1A6", 1164 "MSRValue": "0x1844", 1165 "SampleAfterValue": "100000", 1166 "UMask": "0x1" 1167 }, 1168 { 1169 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1170 "Counter": "2", 1171 "EventCode": "0xB7", 1172 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1173 "MSRIndex": "0x1A6", 1174 "MSRValue": "0x3844", 1175 "SampleAfterValue": "100000", 1176 "UMask": "0x1" 1177 }, 1178 { 1179 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1180 "Counter": "2", 1181 "EventCode": "0xB7", 1182 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1183 "MSRIndex": "0x1A6", 1184 "MSRValue": "0x1044", 1185 "SampleAfterValue": "100000", 1186 "UMask": "0x1" 1187 }, 1188 { 1189 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1190 "Counter": "2", 1191 "EventCode": "0xB7", 1192 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1193 "MSRIndex": "0x1A6", 1194 "MSRValue": "0x844", 1195 "SampleAfterValue": "100000", 1196 "UMask": "0x1" 1197 }, 1198 { 1199 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1200 "Counter": "2", 1201 "EventCode": "0xB7", 1202 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1203 "MSRIndex": "0x1A6", 1204 "MSRValue": "0x7FFF", 1205 "SampleAfterValue": "100000", 1206 "UMask": "0x1" 1207 }, 1208 { 1209 "BriefDescription": "All offcore requests", 1210 "Counter": "2", 1211 "EventCode": "0xB7", 1212 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1213 "MSRIndex": "0x1A6", 1214 "MSRValue": "0xFFFF", 1215 "SampleAfterValue": "100000", 1216 "UMask": "0x1" 1217 }, 1218 { 1219 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1220 "Counter": "2", 1221 "EventCode": "0xB7", 1222 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1223 "MSRIndex": "0x1A6", 1224 "MSRValue": "0x80FF", 1225 "SampleAfterValue": "100000", 1226 "UMask": "0x1" 1227 }, 1228 { 1229 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1230 "Counter": "2", 1231 "EventCode": "0xB7", 1232 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1233 "MSRIndex": "0x1A6", 1234 "MSRValue": "0x1FF", 1235 "SampleAfterValue": "100000", 1236 "UMask": "0x1" 1237 }, 1238 { 1239 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1240 "Counter": "2", 1241 "EventCode": "0xB7", 1242 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1243 "MSRIndex": "0x1A6", 1244 "MSRValue": "0x2FF", 1245 "SampleAfterValue": "100000", 1246 "UMask": "0x1" 1247 }, 1248 { 1249 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1250 "Counter": "2", 1251 "EventCode": "0xB7", 1252 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1253 "MSRIndex": "0x1A6", 1254 "MSRValue": "0x4FF", 1255 "SampleAfterValue": "100000", 1256 "UMask": "0x1" 1257 }, 1258 { 1259 "BriefDescription": "Offcore requests satisfied by the LLC", 1260 "Counter": "2", 1261 "EventCode": "0xB7", 1262 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1263 "MSRIndex": "0x1A6", 1264 "MSRValue": "0x7FF", 1265 "SampleAfterValue": "100000", 1266 "UMask": "0x1" 1267 }, 1268 { 1269 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1270 "Counter": "2", 1271 "EventCode": "0xB7", 1272 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1273 "MSRIndex": "0x1A6", 1274 "MSRValue": "0x47FF", 1275 "SampleAfterValue": "100000", 1276 "UMask": "0x1" 1277 }, 1278 { 1279 "BriefDescription": "Offcore requests satisfied by a remote cache", 1280 "Counter": "2", 1281 "EventCode": "0xB7", 1282 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1283 "MSRIndex": "0x1A6", 1284 "MSRValue": "0x18FF", 1285 "SampleAfterValue": "100000", 1286 "UMask": "0x1" 1287 }, 1288 { 1289 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1290 "Counter": "2", 1291 "EventCode": "0xB7", 1292 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1293 "MSRIndex": "0x1A6", 1294 "MSRValue": "0x38FF", 1295 "SampleAfterValue": "100000", 1296 "UMask": "0x1" 1297 }, 1298 { 1299 "BriefDescription": "Offcore requests that HIT in a remote cache", 1300 "Counter": "2", 1301 "EventCode": "0xB7", 1302 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1303 "MSRIndex": "0x1A6", 1304 "MSRValue": "0x10FF", 1305 "SampleAfterValue": "100000", 1306 "UMask": "0x1" 1307 }, 1308 { 1309 "BriefDescription": "Offcore requests that HITM in a remote cache", 1310 "Counter": "2", 1311 "EventCode": "0xB7", 1312 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1313 "MSRIndex": "0x1A6", 1314 "MSRValue": "0x8FF", 1315 "SampleAfterValue": "100000", 1316 "UMask": "0x1" 1317 }, 1318 { 1319 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1320 "Counter": "2", 1321 "EventCode": "0xB7", 1322 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1323 "MSRIndex": "0x1A6", 1324 "MSRValue": "0x7F22", 1325 "SampleAfterValue": "100000", 1326 "UMask": "0x1" 1327 }, 1328 { 1329 "BriefDescription": "All offcore RFO requests", 1330 "Counter": "2", 1331 "EventCode": "0xB7", 1332 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1333 "MSRIndex": "0x1A6", 1334 "MSRValue": "0xFF22", 1335 "SampleAfterValue": "100000", 1336 "UMask": "0x1" 1337 }, 1338 { 1339 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1340 "Counter": "2", 1341 "EventCode": "0xB7", 1342 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1343 "MSRIndex": "0x1A6", 1344 "MSRValue": "0x8022", 1345 "SampleAfterValue": "100000", 1346 "UMask": "0x1" 1347 }, 1348 { 1349 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1350 "Counter": "2", 1351 "EventCode": "0xB7", 1352 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1353 "MSRIndex": "0x1A6", 1354 "MSRValue": "0x122", 1355 "SampleAfterValue": "100000", 1356 "UMask": "0x1" 1357 }, 1358 { 1359 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1360 "Counter": "2", 1361 "EventCode": "0xB7", 1362 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1363 "MSRIndex": "0x1A6", 1364 "MSRValue": "0x222", 1365 "SampleAfterValue": "100000", 1366 "UMask": "0x1" 1367 }, 1368 { 1369 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1370 "Counter": "2", 1371 "EventCode": "0xB7", 1372 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1373 "MSRIndex": "0x1A6", 1374 "MSRValue": "0x422", 1375 "SampleAfterValue": "100000", 1376 "UMask": "0x1" 1377 }, 1378 { 1379 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1380 "Counter": "2", 1381 "EventCode": "0xB7", 1382 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1383 "MSRIndex": "0x1A6", 1384 "MSRValue": "0x722", 1385 "SampleAfterValue": "100000", 1386 "UMask": "0x1" 1387 }, 1388 { 1389 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1390 "Counter": "2", 1391 "EventCode": "0xB7", 1392 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1393 "MSRIndex": "0x1A6", 1394 "MSRValue": "0x4722", 1395 "SampleAfterValue": "100000", 1396 "UMask": "0x1" 1397 }, 1398 { 1399 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1400 "Counter": "2", 1401 "EventCode": "0xB7", 1402 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1403 "MSRIndex": "0x1A6", 1404 "MSRValue": "0x1822", 1405 "SampleAfterValue": "100000", 1406 "UMask": "0x1" 1407 }, 1408 { 1409 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1410 "Counter": "2", 1411 "EventCode": "0xB7", 1412 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1413 "MSRIndex": "0x1A6", 1414 "MSRValue": "0x3822", 1415 "SampleAfterValue": "100000", 1416 "UMask": "0x1" 1417 }, 1418 { 1419 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1420 "Counter": "2", 1421 "EventCode": "0xB7", 1422 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1423 "MSRIndex": "0x1A6", 1424 "MSRValue": "0x1022", 1425 "SampleAfterValue": "100000", 1426 "UMask": "0x1" 1427 }, 1428 { 1429 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1430 "Counter": "2", 1431 "EventCode": "0xB7", 1432 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1433 "MSRIndex": "0x1A6", 1434 "MSRValue": "0x822", 1435 "SampleAfterValue": "100000", 1436 "UMask": "0x1" 1437 }, 1438 { 1439 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1440 "Counter": "2", 1441 "EventCode": "0xB7", 1442 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1443 "MSRIndex": "0x1A6", 1444 "MSRValue": "0x7F08", 1445 "SampleAfterValue": "100000", 1446 "UMask": "0x1" 1447 }, 1448 { 1449 "BriefDescription": "All offcore writebacks", 1450 "Counter": "2", 1451 "EventCode": "0xB7", 1452 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1453 "MSRIndex": "0x1A6", 1454 "MSRValue": "0xFF08", 1455 "SampleAfterValue": "100000", 1456 "UMask": "0x1" 1457 }, 1458 { 1459 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1460 "Counter": "2", 1461 "EventCode": "0xB7", 1462 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1463 "MSRIndex": "0x1A6", 1464 "MSRValue": "0x8008", 1465 "SampleAfterValue": "100000", 1466 "UMask": "0x1" 1467 }, 1468 { 1469 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1470 "Counter": "2", 1471 "EventCode": "0xB7", 1472 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1473 "MSRIndex": "0x1A6", 1474 "MSRValue": "0x108", 1475 "SampleAfterValue": "100000", 1476 "UMask": "0x1" 1477 }, 1478 { 1479 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1480 "Counter": "2", 1481 "EventCode": "0xB7", 1482 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1483 "MSRIndex": "0x1A6", 1484 "MSRValue": "0x408", 1485 "SampleAfterValue": "100000", 1486 "UMask": "0x1" 1487 }, 1488 { 1489 "BriefDescription": "Offcore writebacks to the LLC", 1490 "Counter": "2", 1491 "EventCode": "0xB7", 1492 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1493 "MSRIndex": "0x1A6", 1494 "MSRValue": "0x708", 1495 "SampleAfterValue": "100000", 1496 "UMask": "0x1" 1497 }, 1498 { 1499 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1500 "Counter": "2", 1501 "EventCode": "0xB7", 1502 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1503 "MSRIndex": "0x1A6", 1504 "MSRValue": "0x4708", 1505 "SampleAfterValue": "100000", 1506 "UMask": "0x1" 1507 }, 1508 { 1509 "BriefDescription": "Offcore writebacks to a remote cache", 1510 "Counter": "2", 1511 "EventCode": "0xB7", 1512 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1513 "MSRIndex": "0x1A6", 1514 "MSRValue": "0x1808", 1515 "SampleAfterValue": "100000", 1516 "UMask": "0x1" 1517 }, 1518 { 1519 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1520 "Counter": "2", 1521 "EventCode": "0xB7", 1522 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1523 "MSRIndex": "0x1A6", 1524 "MSRValue": "0x3808", 1525 "SampleAfterValue": "100000", 1526 "UMask": "0x1" 1527 }, 1528 { 1529 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1530 "Counter": "2", 1531 "EventCode": "0xB7", 1532 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1533 "MSRIndex": "0x1A6", 1534 "MSRValue": "0x1008", 1535 "SampleAfterValue": "100000", 1536 "UMask": "0x1" 1537 }, 1538 { 1539 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1540 "Counter": "2", 1541 "EventCode": "0xB7", 1542 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1543 "MSRIndex": "0x1A6", 1544 "MSRValue": "0x808", 1545 "SampleAfterValue": "100000", 1546 "UMask": "0x1" 1547 }, 1548 { 1549 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1550 "Counter": "2", 1551 "EventCode": "0xB7", 1552 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1553 "MSRIndex": "0x1A6", 1554 "MSRValue": "0x7F77", 1555 "SampleAfterValue": "100000", 1556 "UMask": "0x1" 1557 }, 1558 { 1559 "BriefDescription": "All offcore code or data read requests", 1560 "Counter": "2", 1561 "EventCode": "0xB7", 1562 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1563 "MSRIndex": "0x1A6", 1564 "MSRValue": "0xFF77", 1565 "SampleAfterValue": "100000", 1566 "UMask": "0x1" 1567 }, 1568 { 1569 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1570 "Counter": "2", 1571 "EventCode": "0xB7", 1572 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1573 "MSRIndex": "0x1A6", 1574 "MSRValue": "0x8077", 1575 "SampleAfterValue": "100000", 1576 "UMask": "0x1" 1577 }, 1578 { 1579 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1580 "Counter": "2", 1581 "EventCode": "0xB7", 1582 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1583 "MSRIndex": "0x1A6", 1584 "MSRValue": "0x177", 1585 "SampleAfterValue": "100000", 1586 "UMask": "0x1" 1587 }, 1588 { 1589 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1590 "Counter": "2", 1591 "EventCode": "0xB7", 1592 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1593 "MSRIndex": "0x1A6", 1594 "MSRValue": "0x277", 1595 "SampleAfterValue": "100000", 1596 "UMask": "0x1" 1597 }, 1598 { 1599 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1600 "Counter": "2", 1601 "EventCode": "0xB7", 1602 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1603 "MSRIndex": "0x1A6", 1604 "MSRValue": "0x477", 1605 "SampleAfterValue": "100000", 1606 "UMask": "0x1" 1607 }, 1608 { 1609 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1610 "Counter": "2", 1611 "EventCode": "0xB7", 1612 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1613 "MSRIndex": "0x1A6", 1614 "MSRValue": "0x777", 1615 "SampleAfterValue": "100000", 1616 "UMask": "0x1" 1617 }, 1618 { 1619 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1620 "Counter": "2", 1621 "EventCode": "0xB7", 1622 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1623 "MSRIndex": "0x1A6", 1624 "MSRValue": "0x4777", 1625 "SampleAfterValue": "100000", 1626 "UMask": "0x1" 1627 }, 1628 { 1629 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1630 "Counter": "2", 1631 "EventCode": "0xB7", 1632 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1633 "MSRIndex": "0x1A6", 1634 "MSRValue": "0x1877", 1635 "SampleAfterValue": "100000", 1636 "UMask": "0x1" 1637 }, 1638 { 1639 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1640 "Counter": "2", 1641 "EventCode": "0xB7", 1642 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1643 "MSRIndex": "0x1A6", 1644 "MSRValue": "0x3877", 1645 "SampleAfterValue": "100000", 1646 "UMask": "0x1" 1647 }, 1648 { 1649 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1650 "Counter": "2", 1651 "EventCode": "0xB7", 1652 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1653 "MSRIndex": "0x1A6", 1654 "MSRValue": "0x1077", 1655 "SampleAfterValue": "100000", 1656 "UMask": "0x1" 1657 }, 1658 { 1659 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1660 "Counter": "2", 1661 "EventCode": "0xB7", 1662 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1663 "MSRIndex": "0x1A6", 1664 "MSRValue": "0x877", 1665 "SampleAfterValue": "100000", 1666 "UMask": "0x1" 1667 }, 1668 { 1669 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1670 "Counter": "2", 1671 "EventCode": "0xB7", 1672 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1673 "MSRIndex": "0x1A6", 1674 "MSRValue": "0x7F33", 1675 "SampleAfterValue": "100000", 1676 "UMask": "0x1" 1677 }, 1678 { 1679 "BriefDescription": "Offcore request = all data, response = any location", 1680 "Counter": "2", 1681 "EventCode": "0xB7", 1682 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1683 "MSRIndex": "0x1A6", 1684 "MSRValue": "0xFF33", 1685 "SampleAfterValue": "100000", 1686 "UMask": "0x1" 1687 }, 1688 { 1689 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1690 "Counter": "2", 1691 "EventCode": "0xB7", 1692 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1693 "MSRIndex": "0x1A6", 1694 "MSRValue": "0x8033", 1695 "SampleAfterValue": "100000", 1696 "UMask": "0x1" 1697 }, 1698 { 1699 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1700 "Counter": "2", 1701 "EventCode": "0xB7", 1702 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1703 "MSRIndex": "0x1A6", 1704 "MSRValue": "0x133", 1705 "SampleAfterValue": "100000", 1706 "UMask": "0x1" 1707 }, 1708 { 1709 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1710 "Counter": "2", 1711 "EventCode": "0xB7", 1712 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1713 "MSRIndex": "0x1A6", 1714 "MSRValue": "0x233", 1715 "SampleAfterValue": "100000", 1716 "UMask": "0x1" 1717 }, 1718 { 1719 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1720 "Counter": "2", 1721 "EventCode": "0xB7", 1722 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1723 "MSRIndex": "0x1A6", 1724 "MSRValue": "0x433", 1725 "SampleAfterValue": "100000", 1726 "UMask": "0x1" 1727 }, 1728 { 1729 "BriefDescription": "Offcore request = all data, response = local cache", 1730 "Counter": "2", 1731 "EventCode": "0xB7", 1732 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1733 "MSRIndex": "0x1A6", 1734 "MSRValue": "0x733", 1735 "SampleAfterValue": "100000", 1736 "UMask": "0x1" 1737 }, 1738 { 1739 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1740 "Counter": "2", 1741 "EventCode": "0xB7", 1742 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1743 "MSRIndex": "0x1A6", 1744 "MSRValue": "0x4733", 1745 "SampleAfterValue": "100000", 1746 "UMask": "0x1" 1747 }, 1748 { 1749 "BriefDescription": "Offcore request = all data, response = remote cache", 1750 "Counter": "2", 1751 "EventCode": "0xB7", 1752 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1753 "MSRIndex": "0x1A6", 1754 "MSRValue": "0x1833", 1755 "SampleAfterValue": "100000", 1756 "UMask": "0x1" 1757 }, 1758 { 1759 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1760 "Counter": "2", 1761 "EventCode": "0xB7", 1762 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1763 "MSRIndex": "0x1A6", 1764 "MSRValue": "0x3833", 1765 "SampleAfterValue": "100000", 1766 "UMask": "0x1" 1767 }, 1768 { 1769 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1770 "Counter": "2", 1771 "EventCode": "0xB7", 1772 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1773 "MSRIndex": "0x1A6", 1774 "MSRValue": "0x1033", 1775 "SampleAfterValue": "100000", 1776 "UMask": "0x1" 1777 }, 1778 { 1779 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1780 "Counter": "2", 1781 "EventCode": "0xB7", 1782 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1783 "MSRIndex": "0x1A6", 1784 "MSRValue": "0x833", 1785 "SampleAfterValue": "100000", 1786 "UMask": "0x1" 1787 }, 1788 { 1789 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1790 "Counter": "2", 1791 "EventCode": "0xB7", 1792 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1793 "MSRIndex": "0x1A6", 1794 "MSRValue": "0x7F03", 1795 "SampleAfterValue": "100000", 1796 "UMask": "0x1" 1797 }, 1798 { 1799 "BriefDescription": "All offcore demand data requests", 1800 "Counter": "2", 1801 "EventCode": "0xB7", 1802 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1803 "MSRIndex": "0x1A6", 1804 "MSRValue": "0xFF03", 1805 "SampleAfterValue": "100000", 1806 "UMask": "0x1" 1807 }, 1808 { 1809 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1810 "Counter": "2", 1811 "EventCode": "0xB7", 1812 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1813 "MSRIndex": "0x1A6", 1814 "MSRValue": "0x8003", 1815 "SampleAfterValue": "100000", 1816 "UMask": "0x1" 1817 }, 1818 { 1819 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1820 "Counter": "2", 1821 "EventCode": "0xB7", 1822 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1823 "MSRIndex": "0x1A6", 1824 "MSRValue": "0x103", 1825 "SampleAfterValue": "100000", 1826 "UMask": "0x1" 1827 }, 1828 { 1829 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1830 "Counter": "2", 1831 "EventCode": "0xB7", 1832 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1833 "MSRIndex": "0x1A6", 1834 "MSRValue": "0x203", 1835 "SampleAfterValue": "100000", 1836 "UMask": "0x1" 1837 }, 1838 { 1839 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1840 "Counter": "2", 1841 "EventCode": "0xB7", 1842 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1843 "MSRIndex": "0x1A6", 1844 "MSRValue": "0x403", 1845 "SampleAfterValue": "100000", 1846 "UMask": "0x1" 1847 }, 1848 { 1849 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1850 "Counter": "2", 1851 "EventCode": "0xB7", 1852 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1853 "MSRIndex": "0x1A6", 1854 "MSRValue": "0x703", 1855 "SampleAfterValue": "100000", 1856 "UMask": "0x1" 1857 }, 1858 { 1859 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1860 "Counter": "2", 1861 "EventCode": "0xB7", 1862 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1863 "MSRIndex": "0x1A6", 1864 "MSRValue": "0x4703", 1865 "SampleAfterValue": "100000", 1866 "UMask": "0x1" 1867 }, 1868 { 1869 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1870 "Counter": "2", 1871 "EventCode": "0xB7", 1872 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1873 "MSRIndex": "0x1A6", 1874 "MSRValue": "0x1803", 1875 "SampleAfterValue": "100000", 1876 "UMask": "0x1" 1877 }, 1878 { 1879 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1880 "Counter": "2", 1881 "EventCode": "0xB7", 1882 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1883 "MSRIndex": "0x1A6", 1884 "MSRValue": "0x3803", 1885 "SampleAfterValue": "100000", 1886 "UMask": "0x1" 1887 }, 1888 { 1889 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1890 "Counter": "2", 1891 "EventCode": "0xB7", 1892 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1893 "MSRIndex": "0x1A6", 1894 "MSRValue": "0x1003", 1895 "SampleAfterValue": "100000", 1896 "UMask": "0x1" 1897 }, 1898 { 1899 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1900 "Counter": "2", 1901 "EventCode": "0xB7", 1902 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1903 "MSRIndex": "0x1A6", 1904 "MSRValue": "0x803", 1905 "SampleAfterValue": "100000", 1906 "UMask": "0x1" 1907 }, 1908 { 1909 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1910 "Counter": "2", 1911 "EventCode": "0xB7", 1912 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1913 "MSRIndex": "0x1A6", 1914 "MSRValue": "0x7F01", 1915 "SampleAfterValue": "100000", 1916 "UMask": "0x1" 1917 }, 1918 { 1919 "BriefDescription": "All offcore demand data reads", 1920 "Counter": "2", 1921 "EventCode": "0xB7", 1922 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1923 "MSRIndex": "0x1A6", 1924 "MSRValue": "0xFF01", 1925 "SampleAfterValue": "100000", 1926 "UMask": "0x1" 1927 }, 1928 { 1929 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1930 "Counter": "2", 1931 "EventCode": "0xB7", 1932 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1933 "MSRIndex": "0x1A6", 1934 "MSRValue": "0x8001", 1935 "SampleAfterValue": "100000", 1936 "UMask": "0x1" 1937 }, 1938 { 1939 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1940 "Counter": "2", 1941 "EventCode": "0xB7", 1942 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1943 "MSRIndex": "0x1A6", 1944 "MSRValue": "0x101", 1945 "SampleAfterValue": "100000", 1946 "UMask": "0x1" 1947 }, 1948 { 1949 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1950 "Counter": "2", 1951 "EventCode": "0xB7", 1952 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1953 "MSRIndex": "0x1A6", 1954 "MSRValue": "0x201", 1955 "SampleAfterValue": "100000", 1956 "UMask": "0x1" 1957 }, 1958 { 1959 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1960 "Counter": "2", 1961 "EventCode": "0xB7", 1962 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1963 "MSRIndex": "0x1A6", 1964 "MSRValue": "0x401", 1965 "SampleAfterValue": "100000", 1966 "UMask": "0x1" 1967 }, 1968 { 1969 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1970 "Counter": "2", 1971 "EventCode": "0xB7", 1972 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1973 "MSRIndex": "0x1A6", 1974 "MSRValue": "0x701", 1975 "SampleAfterValue": "100000", 1976 "UMask": "0x1" 1977 }, 1978 { 1979 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1980 "Counter": "2", 1981 "EventCode": "0xB7", 1982 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1983 "MSRIndex": "0x1A6", 1984 "MSRValue": "0x4701", 1985 "SampleAfterValue": "100000", 1986 "UMask": "0x1" 1987 }, 1988 { 1989 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 1990 "Counter": "2", 1991 "EventCode": "0xB7", 1992 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 1993 "MSRIndex": "0x1A6", 1994 "MSRValue": "0x1801", 1995 "SampleAfterValue": "100000", 1996 "UMask": "0x1" 1997 }, 1998 { 1999 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2000 "Counter": "2", 2001 "EventCode": "0xB7", 2002 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2003 "MSRIndex": "0x1A6", 2004 "MSRValue": "0x3801", 2005 "SampleAfterValue": "100000", 2006 "UMask": "0x1" 2007 }, 2008 { 2009 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2010 "Counter": "2", 2011 "EventCode": "0xB7", 2012 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2013 "MSRIndex": "0x1A6", 2014 "MSRValue": "0x1001", 2015 "SampleAfterValue": "100000", 2016 "UMask": "0x1" 2017 }, 2018 { 2019 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2020 "Counter": "2", 2021 "EventCode": "0xB7", 2022 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2023 "MSRIndex": "0x1A6", 2024 "MSRValue": "0x801", 2025 "SampleAfterValue": "100000", 2026 "UMask": "0x1" 2027 }, 2028 { 2029 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2030 "Counter": "2", 2031 "EventCode": "0xB7", 2032 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2033 "MSRIndex": "0x1A6", 2034 "MSRValue": "0x7F04", 2035 "SampleAfterValue": "100000", 2036 "UMask": "0x1" 2037 }, 2038 { 2039 "BriefDescription": "All offcore demand code reads", 2040 "Counter": "2", 2041 "EventCode": "0xB7", 2042 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2043 "MSRIndex": "0x1A6", 2044 "MSRValue": "0xFF04", 2045 "SampleAfterValue": "100000", 2046 "UMask": "0x1" 2047 }, 2048 { 2049 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2050 "Counter": "2", 2051 "EventCode": "0xB7", 2052 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2053 "MSRIndex": "0x1A6", 2054 "MSRValue": "0x8004", 2055 "SampleAfterValue": "100000", 2056 "UMask": "0x1" 2057 }, 2058 { 2059 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2060 "Counter": "2", 2061 "EventCode": "0xB7", 2062 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2063 "MSRIndex": "0x1A6", 2064 "MSRValue": "0x104", 2065 "SampleAfterValue": "100000", 2066 "UMask": "0x1" 2067 }, 2068 { 2069 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2070 "Counter": "2", 2071 "EventCode": "0xB7", 2072 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2073 "MSRIndex": "0x1A6", 2074 "MSRValue": "0x204", 2075 "SampleAfterValue": "100000", 2076 "UMask": "0x1" 2077 }, 2078 { 2079 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2080 "Counter": "2", 2081 "EventCode": "0xB7", 2082 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2083 "MSRIndex": "0x1A6", 2084 "MSRValue": "0x404", 2085 "SampleAfterValue": "100000", 2086 "UMask": "0x1" 2087 }, 2088 { 2089 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2090 "Counter": "2", 2091 "EventCode": "0xB7", 2092 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2093 "MSRIndex": "0x1A6", 2094 "MSRValue": "0x704", 2095 "SampleAfterValue": "100000", 2096 "UMask": "0x1" 2097 }, 2098 { 2099 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2100 "Counter": "2", 2101 "EventCode": "0xB7", 2102 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2103 "MSRIndex": "0x1A6", 2104 "MSRValue": "0x4704", 2105 "SampleAfterValue": "100000", 2106 "UMask": "0x1" 2107 }, 2108 { 2109 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2110 "Counter": "2", 2111 "EventCode": "0xB7", 2112 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2113 "MSRIndex": "0x1A6", 2114 "MSRValue": "0x1804", 2115 "SampleAfterValue": "100000", 2116 "UMask": "0x1" 2117 }, 2118 { 2119 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2120 "Counter": "2", 2121 "EventCode": "0xB7", 2122 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2123 "MSRIndex": "0x1A6", 2124 "MSRValue": "0x3804", 2125 "SampleAfterValue": "100000", 2126 "UMask": "0x1" 2127 }, 2128 { 2129 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2130 "Counter": "2", 2131 "EventCode": "0xB7", 2132 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2133 "MSRIndex": "0x1A6", 2134 "MSRValue": "0x1004", 2135 "SampleAfterValue": "100000", 2136 "UMask": "0x1" 2137 }, 2138 { 2139 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2140 "Counter": "2", 2141 "EventCode": "0xB7", 2142 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2143 "MSRIndex": "0x1A6", 2144 "MSRValue": "0x804", 2145 "SampleAfterValue": "100000", 2146 "UMask": "0x1" 2147 }, 2148 { 2149 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2150 "Counter": "2", 2151 "EventCode": "0xB7", 2152 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2153 "MSRIndex": "0x1A6", 2154 "MSRValue": "0x7F02", 2155 "SampleAfterValue": "100000", 2156 "UMask": "0x1" 2157 }, 2158 { 2159 "BriefDescription": "All offcore demand RFO requests", 2160 "Counter": "2", 2161 "EventCode": "0xB7", 2162 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2163 "MSRIndex": "0x1A6", 2164 "MSRValue": "0xFF02", 2165 "SampleAfterValue": "100000", 2166 "UMask": "0x1" 2167 }, 2168 { 2169 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2170 "Counter": "2", 2171 "EventCode": "0xB7", 2172 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2173 "MSRIndex": "0x1A6", 2174 "MSRValue": "0x8002", 2175 "SampleAfterValue": "100000", 2176 "UMask": "0x1" 2177 }, 2178 { 2179 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2180 "Counter": "2", 2181 "EventCode": "0xB7", 2182 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2183 "MSRIndex": "0x1A6", 2184 "MSRValue": "0x102", 2185 "SampleAfterValue": "100000", 2186 "UMask": "0x1" 2187 }, 2188 { 2189 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2190 "Counter": "2", 2191 "EventCode": "0xB7", 2192 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2193 "MSRIndex": "0x1A6", 2194 "MSRValue": "0x202", 2195 "SampleAfterValue": "100000", 2196 "UMask": "0x1" 2197 }, 2198 { 2199 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2200 "Counter": "2", 2201 "EventCode": "0xB7", 2202 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2203 "MSRIndex": "0x1A6", 2204 "MSRValue": "0x402", 2205 "SampleAfterValue": "100000", 2206 "UMask": "0x1" 2207 }, 2208 { 2209 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2210 "Counter": "2", 2211 "EventCode": "0xB7", 2212 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2213 "MSRIndex": "0x1A6", 2214 "MSRValue": "0x702", 2215 "SampleAfterValue": "100000", 2216 "UMask": "0x1" 2217 }, 2218 { 2219 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2220 "Counter": "2", 2221 "EventCode": "0xB7", 2222 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2223 "MSRIndex": "0x1A6", 2224 "MSRValue": "0x4702", 2225 "SampleAfterValue": "100000", 2226 "UMask": "0x1" 2227 }, 2228 { 2229 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2230 "Counter": "2", 2231 "EventCode": "0xB7", 2232 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2233 "MSRIndex": "0x1A6", 2234 "MSRValue": "0x1802", 2235 "SampleAfterValue": "100000", 2236 "UMask": "0x1" 2237 }, 2238 { 2239 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2240 "Counter": "2", 2241 "EventCode": "0xB7", 2242 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2243 "MSRIndex": "0x1A6", 2244 "MSRValue": "0x3802", 2245 "SampleAfterValue": "100000", 2246 "UMask": "0x1" 2247 }, 2248 { 2249 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2250 "Counter": "2", 2251 "EventCode": "0xB7", 2252 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2253 "MSRIndex": "0x1A6", 2254 "MSRValue": "0x1002", 2255 "SampleAfterValue": "100000", 2256 "UMask": "0x1" 2257 }, 2258 { 2259 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2260 "Counter": "2", 2261 "EventCode": "0xB7", 2262 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2263 "MSRIndex": "0x1A6", 2264 "MSRValue": "0x802", 2265 "SampleAfterValue": "100000", 2266 "UMask": "0x1" 2267 }, 2268 { 2269 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2270 "Counter": "2", 2271 "EventCode": "0xB7", 2272 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2273 "MSRIndex": "0x1A6", 2274 "MSRValue": "0x7F80", 2275 "SampleAfterValue": "100000", 2276 "UMask": "0x1" 2277 }, 2278 { 2279 "BriefDescription": "All offcore other requests", 2280 "Counter": "2", 2281 "EventCode": "0xB7", 2282 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2283 "MSRIndex": "0x1A6", 2284 "MSRValue": "0xFF80", 2285 "SampleAfterValue": "100000", 2286 "UMask": "0x1" 2287 }, 2288 { 2289 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2290 "Counter": "2", 2291 "EventCode": "0xB7", 2292 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2293 "MSRIndex": "0x1A6", 2294 "MSRValue": "0x8080", 2295 "SampleAfterValue": "100000", 2296 "UMask": "0x1" 2297 }, 2298 { 2299 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2300 "Counter": "2", 2301 "EventCode": "0xB7", 2302 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2303 "MSRIndex": "0x1A6", 2304 "MSRValue": "0x180", 2305 "SampleAfterValue": "100000", 2306 "UMask": "0x1" 2307 }, 2308 { 2309 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2310 "Counter": "2", 2311 "EventCode": "0xB7", 2312 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2313 "MSRIndex": "0x1A6", 2314 "MSRValue": "0x280", 2315 "SampleAfterValue": "100000", 2316 "UMask": "0x1" 2317 }, 2318 { 2319 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2320 "Counter": "2", 2321 "EventCode": "0xB7", 2322 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2323 "MSRIndex": "0x1A6", 2324 "MSRValue": "0x480", 2325 "SampleAfterValue": "100000", 2326 "UMask": "0x1" 2327 }, 2328 { 2329 "BriefDescription": "Offcore other requests satisfied by the LLC", 2330 "Counter": "2", 2331 "EventCode": "0xB7", 2332 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2333 "MSRIndex": "0x1A6", 2334 "MSRValue": "0x780", 2335 "SampleAfterValue": "100000", 2336 "UMask": "0x1" 2337 }, 2338 { 2339 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2340 "Counter": "2", 2341 "EventCode": "0xB7", 2342 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2343 "MSRIndex": "0x1A6", 2344 "MSRValue": "0x4780", 2345 "SampleAfterValue": "100000", 2346 "UMask": "0x1" 2347 }, 2348 { 2349 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2350 "Counter": "2", 2351 "EventCode": "0xB7", 2352 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2353 "MSRIndex": "0x1A6", 2354 "MSRValue": "0x1880", 2355 "SampleAfterValue": "100000", 2356 "UMask": "0x1" 2357 }, 2358 { 2359 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2360 "Counter": "2", 2361 "EventCode": "0xB7", 2362 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2363 "MSRIndex": "0x1A6", 2364 "MSRValue": "0x3880", 2365 "SampleAfterValue": "100000", 2366 "UMask": "0x1" 2367 }, 2368 { 2369 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2370 "Counter": "2", 2371 "EventCode": "0xB7", 2372 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2373 "MSRIndex": "0x1A6", 2374 "MSRValue": "0x1080", 2375 "SampleAfterValue": "100000", 2376 "UMask": "0x1" 2377 }, 2378 { 2379 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2380 "Counter": "2", 2381 "EventCode": "0xB7", 2382 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2383 "MSRIndex": "0x1A6", 2384 "MSRValue": "0x880", 2385 "SampleAfterValue": "100000", 2386 "UMask": "0x1" 2387 }, 2388 { 2389 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2390 "Counter": "2", 2391 "EventCode": "0xB7", 2392 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2393 "MSRIndex": "0x1A6", 2394 "MSRValue": "0x7F30", 2395 "SampleAfterValue": "100000", 2396 "UMask": "0x1" 2397 }, 2398 { 2399 "BriefDescription": "All offcore prefetch data requests", 2400 "Counter": "2", 2401 "EventCode": "0xB7", 2402 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2403 "MSRIndex": "0x1A6", 2404 "MSRValue": "0xFF30", 2405 "SampleAfterValue": "100000", 2406 "UMask": "0x1" 2407 }, 2408 { 2409 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2410 "Counter": "2", 2411 "EventCode": "0xB7", 2412 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2413 "MSRIndex": "0x1A6", 2414 "MSRValue": "0x8030", 2415 "SampleAfterValue": "100000", 2416 "UMask": "0x1" 2417 }, 2418 { 2419 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2420 "Counter": "2", 2421 "EventCode": "0xB7", 2422 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2423 "MSRIndex": "0x1A6", 2424 "MSRValue": "0x130", 2425 "SampleAfterValue": "100000", 2426 "UMask": "0x1" 2427 }, 2428 { 2429 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2430 "Counter": "2", 2431 "EventCode": "0xB7", 2432 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2433 "MSRIndex": "0x1A6", 2434 "MSRValue": "0x230", 2435 "SampleAfterValue": "100000", 2436 "UMask": "0x1" 2437 }, 2438 { 2439 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2440 "Counter": "2", 2441 "EventCode": "0xB7", 2442 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2443 "MSRIndex": "0x1A6", 2444 "MSRValue": "0x430", 2445 "SampleAfterValue": "100000", 2446 "UMask": "0x1" 2447 }, 2448 { 2449 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2450 "Counter": "2", 2451 "EventCode": "0xB7", 2452 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2453 "MSRIndex": "0x1A6", 2454 "MSRValue": "0x730", 2455 "SampleAfterValue": "100000", 2456 "UMask": "0x1" 2457 }, 2458 { 2459 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2460 "Counter": "2", 2461 "EventCode": "0xB7", 2462 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2463 "MSRIndex": "0x1A6", 2464 "MSRValue": "0x4730", 2465 "SampleAfterValue": "100000", 2466 "UMask": "0x1" 2467 }, 2468 { 2469 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2470 "Counter": "2", 2471 "EventCode": "0xB7", 2472 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2473 "MSRIndex": "0x1A6", 2474 "MSRValue": "0x1830", 2475 "SampleAfterValue": "100000", 2476 "UMask": "0x1" 2477 }, 2478 { 2479 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2480 "Counter": "2", 2481 "EventCode": "0xB7", 2482 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2483 "MSRIndex": "0x1A6", 2484 "MSRValue": "0x3830", 2485 "SampleAfterValue": "100000", 2486 "UMask": "0x1" 2487 }, 2488 { 2489 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2490 "Counter": "2", 2491 "EventCode": "0xB7", 2492 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2493 "MSRIndex": "0x1A6", 2494 "MSRValue": "0x1030", 2495 "SampleAfterValue": "100000", 2496 "UMask": "0x1" 2497 }, 2498 { 2499 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2500 "Counter": "2", 2501 "EventCode": "0xB7", 2502 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2503 "MSRIndex": "0x1A6", 2504 "MSRValue": "0x830", 2505 "SampleAfterValue": "100000", 2506 "UMask": "0x1" 2507 }, 2508 { 2509 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2510 "Counter": "2", 2511 "EventCode": "0xB7", 2512 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2513 "MSRIndex": "0x1A6", 2514 "MSRValue": "0x7F10", 2515 "SampleAfterValue": "100000", 2516 "UMask": "0x1" 2517 }, 2518 { 2519 "BriefDescription": "All offcore prefetch data reads", 2520 "Counter": "2", 2521 "EventCode": "0xB7", 2522 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2523 "MSRIndex": "0x1A6", 2524 "MSRValue": "0xFF10", 2525 "SampleAfterValue": "100000", 2526 "UMask": "0x1" 2527 }, 2528 { 2529 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2530 "Counter": "2", 2531 "EventCode": "0xB7", 2532 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2533 "MSRIndex": "0x1A6", 2534 "MSRValue": "0x8010", 2535 "SampleAfterValue": "100000", 2536 "UMask": "0x1" 2537 }, 2538 { 2539 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2540 "Counter": "2", 2541 "EventCode": "0xB7", 2542 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2543 "MSRIndex": "0x1A6", 2544 "MSRValue": "0x110", 2545 "SampleAfterValue": "100000", 2546 "UMask": "0x1" 2547 }, 2548 { 2549 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2550 "Counter": "2", 2551 "EventCode": "0xB7", 2552 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2553 "MSRIndex": "0x1A6", 2554 "MSRValue": "0x210", 2555 "SampleAfterValue": "100000", 2556 "UMask": "0x1" 2557 }, 2558 { 2559 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2560 "Counter": "2", 2561 "EventCode": "0xB7", 2562 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2563 "MSRIndex": "0x1A6", 2564 "MSRValue": "0x410", 2565 "SampleAfterValue": "100000", 2566 "UMask": "0x1" 2567 }, 2568 { 2569 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2570 "Counter": "2", 2571 "EventCode": "0xB7", 2572 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2573 "MSRIndex": "0x1A6", 2574 "MSRValue": "0x710", 2575 "SampleAfterValue": "100000", 2576 "UMask": "0x1" 2577 }, 2578 { 2579 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2580 "Counter": "2", 2581 "EventCode": "0xB7", 2582 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2583 "MSRIndex": "0x1A6", 2584 "MSRValue": "0x4710", 2585 "SampleAfterValue": "100000", 2586 "UMask": "0x1" 2587 }, 2588 { 2589 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2590 "Counter": "2", 2591 "EventCode": "0xB7", 2592 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2593 "MSRIndex": "0x1A6", 2594 "MSRValue": "0x1810", 2595 "SampleAfterValue": "100000", 2596 "UMask": "0x1" 2597 }, 2598 { 2599 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2600 "Counter": "2", 2601 "EventCode": "0xB7", 2602 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2603 "MSRIndex": "0x1A6", 2604 "MSRValue": "0x3810", 2605 "SampleAfterValue": "100000", 2606 "UMask": "0x1" 2607 }, 2608 { 2609 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2610 "Counter": "2", 2611 "EventCode": "0xB7", 2612 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2613 "MSRIndex": "0x1A6", 2614 "MSRValue": "0x1010", 2615 "SampleAfterValue": "100000", 2616 "UMask": "0x1" 2617 }, 2618 { 2619 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2620 "Counter": "2", 2621 "EventCode": "0xB7", 2622 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2623 "MSRIndex": "0x1A6", 2624 "MSRValue": "0x810", 2625 "SampleAfterValue": "100000", 2626 "UMask": "0x1" 2627 }, 2628 { 2629 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2630 "Counter": "2", 2631 "EventCode": "0xB7", 2632 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2633 "MSRIndex": "0x1A6", 2634 "MSRValue": "0x7F40", 2635 "SampleAfterValue": "100000", 2636 "UMask": "0x1" 2637 }, 2638 { 2639 "BriefDescription": "All offcore prefetch code reads", 2640 "Counter": "2", 2641 "EventCode": "0xB7", 2642 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2643 "MSRIndex": "0x1A6", 2644 "MSRValue": "0xFF40", 2645 "SampleAfterValue": "100000", 2646 "UMask": "0x1" 2647 }, 2648 { 2649 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2650 "Counter": "2", 2651 "EventCode": "0xB7", 2652 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2653 "MSRIndex": "0x1A6", 2654 "MSRValue": "0x8040", 2655 "SampleAfterValue": "100000", 2656 "UMask": "0x1" 2657 }, 2658 { 2659 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2660 "Counter": "2", 2661 "EventCode": "0xB7", 2662 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2663 "MSRIndex": "0x1A6", 2664 "MSRValue": "0x140", 2665 "SampleAfterValue": "100000", 2666 "UMask": "0x1" 2667 }, 2668 { 2669 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2670 "Counter": "2", 2671 "EventCode": "0xB7", 2672 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2673 "MSRIndex": "0x1A6", 2674 "MSRValue": "0x240", 2675 "SampleAfterValue": "100000", 2676 "UMask": "0x1" 2677 }, 2678 { 2679 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2680 "Counter": "2", 2681 "EventCode": "0xB7", 2682 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2683 "MSRIndex": "0x1A6", 2684 "MSRValue": "0x440", 2685 "SampleAfterValue": "100000", 2686 "UMask": "0x1" 2687 }, 2688 { 2689 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2690 "Counter": "2", 2691 "EventCode": "0xB7", 2692 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2693 "MSRIndex": "0x1A6", 2694 "MSRValue": "0x740", 2695 "SampleAfterValue": "100000", 2696 "UMask": "0x1" 2697 }, 2698 { 2699 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2700 "Counter": "2", 2701 "EventCode": "0xB7", 2702 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2703 "MSRIndex": "0x1A6", 2704 "MSRValue": "0x4740", 2705 "SampleAfterValue": "100000", 2706 "UMask": "0x1" 2707 }, 2708 { 2709 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2710 "Counter": "2", 2711 "EventCode": "0xB7", 2712 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2713 "MSRIndex": "0x1A6", 2714 "MSRValue": "0x1840", 2715 "SampleAfterValue": "100000", 2716 "UMask": "0x1" 2717 }, 2718 { 2719 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2720 "Counter": "2", 2721 "EventCode": "0xB7", 2722 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2723 "MSRIndex": "0x1A6", 2724 "MSRValue": "0x3840", 2725 "SampleAfterValue": "100000", 2726 "UMask": "0x1" 2727 }, 2728 { 2729 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2730 "Counter": "2", 2731 "EventCode": "0xB7", 2732 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2733 "MSRIndex": "0x1A6", 2734 "MSRValue": "0x1040", 2735 "SampleAfterValue": "100000", 2736 "UMask": "0x1" 2737 }, 2738 { 2739 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2740 "Counter": "2", 2741 "EventCode": "0xB7", 2742 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2743 "MSRIndex": "0x1A6", 2744 "MSRValue": "0x840", 2745 "SampleAfterValue": "100000", 2746 "UMask": "0x1" 2747 }, 2748 { 2749 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2750 "Counter": "2", 2751 "EventCode": "0xB7", 2752 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2753 "MSRIndex": "0x1A6", 2754 "MSRValue": "0x7F20", 2755 "SampleAfterValue": "100000", 2756 "UMask": "0x1" 2757 }, 2758 { 2759 "BriefDescription": "All offcore prefetch RFO requests", 2760 "Counter": "2", 2761 "EventCode": "0xB7", 2762 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2763 "MSRIndex": "0x1A6", 2764 "MSRValue": "0xFF20", 2765 "SampleAfterValue": "100000", 2766 "UMask": "0x1" 2767 }, 2768 { 2769 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2770 "Counter": "2", 2771 "EventCode": "0xB7", 2772 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2773 "MSRIndex": "0x1A6", 2774 "MSRValue": "0x8020", 2775 "SampleAfterValue": "100000", 2776 "UMask": "0x1" 2777 }, 2778 { 2779 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2780 "Counter": "2", 2781 "EventCode": "0xB7", 2782 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2783 "MSRIndex": "0x1A6", 2784 "MSRValue": "0x120", 2785 "SampleAfterValue": "100000", 2786 "UMask": "0x1" 2787 }, 2788 { 2789 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2790 "Counter": "2", 2791 "EventCode": "0xB7", 2792 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2793 "MSRIndex": "0x1A6", 2794 "MSRValue": "0x220", 2795 "SampleAfterValue": "100000", 2796 "UMask": "0x1" 2797 }, 2798 { 2799 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2800 "Counter": "2", 2801 "EventCode": "0xB7", 2802 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2803 "MSRIndex": "0x1A6", 2804 "MSRValue": "0x420", 2805 "SampleAfterValue": "100000", 2806 "UMask": "0x1" 2807 }, 2808 { 2809 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2810 "Counter": "2", 2811 "EventCode": "0xB7", 2812 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2813 "MSRIndex": "0x1A6", 2814 "MSRValue": "0x720", 2815 "SampleAfterValue": "100000", 2816 "UMask": "0x1" 2817 }, 2818 { 2819 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2820 "Counter": "2", 2821 "EventCode": "0xB7", 2822 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2823 "MSRIndex": "0x1A6", 2824 "MSRValue": "0x4720", 2825 "SampleAfterValue": "100000", 2826 "UMask": "0x1" 2827 }, 2828 { 2829 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2830 "Counter": "2", 2831 "EventCode": "0xB7", 2832 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2833 "MSRIndex": "0x1A6", 2834 "MSRValue": "0x1820", 2835 "SampleAfterValue": "100000", 2836 "UMask": "0x1" 2837 }, 2838 { 2839 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2840 "Counter": "2", 2841 "EventCode": "0xB7", 2842 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2843 "MSRIndex": "0x1A6", 2844 "MSRValue": "0x3820", 2845 "SampleAfterValue": "100000", 2846 "UMask": "0x1" 2847 }, 2848 { 2849 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2850 "Counter": "2", 2851 "EventCode": "0xB7", 2852 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2853 "MSRIndex": "0x1A6", 2854 "MSRValue": "0x1020", 2855 "SampleAfterValue": "100000", 2856 "UMask": "0x1" 2857 }, 2858 { 2859 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2860 "Counter": "2", 2861 "EventCode": "0xB7", 2862 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2863 "MSRIndex": "0x1A6", 2864 "MSRValue": "0x820", 2865 "SampleAfterValue": "100000", 2866 "UMask": "0x1" 2867 }, 2868 { 2869 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2870 "Counter": "2", 2871 "EventCode": "0xB7", 2872 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2873 "MSRIndex": "0x1A6", 2874 "MSRValue": "0x7F70", 2875 "SampleAfterValue": "100000", 2876 "UMask": "0x1" 2877 }, 2878 { 2879 "BriefDescription": "All offcore prefetch requests", 2880 "Counter": "2", 2881 "EventCode": "0xB7", 2882 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2883 "MSRIndex": "0x1A6", 2884 "MSRValue": "0xFF70", 2885 "SampleAfterValue": "100000", 2886 "UMask": "0x1" 2887 }, 2888 { 2889 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2890 "Counter": "2", 2891 "EventCode": "0xB7", 2892 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2893 "MSRIndex": "0x1A6", 2894 "MSRValue": "0x8070", 2895 "SampleAfterValue": "100000", 2896 "UMask": "0x1" 2897 }, 2898 { 2899 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2900 "Counter": "2", 2901 "EventCode": "0xB7", 2902 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2903 "MSRIndex": "0x1A6", 2904 "MSRValue": "0x170", 2905 "SampleAfterValue": "100000", 2906 "UMask": "0x1" 2907 }, 2908 { 2909 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2910 "Counter": "2", 2911 "EventCode": "0xB7", 2912 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2913 "MSRIndex": "0x1A6", 2914 "MSRValue": "0x270", 2915 "SampleAfterValue": "100000", 2916 "UMask": "0x1" 2917 }, 2918 { 2919 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2920 "Counter": "2", 2921 "EventCode": "0xB7", 2922 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2923 "MSRIndex": "0x1A6", 2924 "MSRValue": "0x470", 2925 "SampleAfterValue": "100000", 2926 "UMask": "0x1" 2927 }, 2928 { 2929 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2930 "Counter": "2", 2931 "EventCode": "0xB7", 2932 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2933 "MSRIndex": "0x1A6", 2934 "MSRValue": "0x770", 2935 "SampleAfterValue": "100000", 2936 "UMask": "0x1" 2937 }, 2938 { 2939 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2940 "Counter": "2", 2941 "EventCode": "0xB7", 2942 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2943 "MSRIndex": "0x1A6", 2944 "MSRValue": "0x4770", 2945 "SampleAfterValue": "100000", 2946 "UMask": "0x1" 2947 }, 2948 { 2949 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2950 "Counter": "2", 2951 "EventCode": "0xB7", 2952 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2953 "MSRIndex": "0x1A6", 2954 "MSRValue": "0x1870", 2955 "SampleAfterValue": "100000", 2956 "UMask": "0x1" 2957 }, 2958 { 2959 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2960 "Counter": "2", 2961 "EventCode": "0xB7", 2962 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2963 "MSRIndex": "0x1A6", 2964 "MSRValue": "0x3870", 2965 "SampleAfterValue": "100000", 2966 "UMask": "0x1" 2967 }, 2968 { 2969 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2970 "Counter": "2", 2971 "EventCode": "0xB7", 2972 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2973 "MSRIndex": "0x1A6", 2974 "MSRValue": "0x1070", 2975 "SampleAfterValue": "100000", 2976 "UMask": "0x1" 2977 }, 2978 { 2979 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2980 "Counter": "2", 2981 "EventCode": "0xB7", 2982 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2983 "MSRIndex": "0x1A6", 2984 "MSRValue": "0x870", 2985 "SampleAfterValue": "100000", 2986 "UMask": "0x1" 2987 }, 2988 { 2989 "BriefDescription": "Super Queue lock splits across a cache line", 2990 "Counter": "0,1,2,3", 2991 "EventCode": "0xF4", 2992 "EventName": "SQ_MISC.SPLIT_LOCK", 2993 "SampleAfterValue": "2000000", 2994 "UMask": "0x10" 2995 }, 2996 { 2997 "BriefDescription": "Loads delayed with at-Retirement block code", 2998 "Counter": "0,1,2,3", 2999 "EventCode": "0x6", 3000 "EventName": "STORE_BLOCKS.AT_RET", 3001 "SampleAfterValue": "200000", 3002 "UMask": "0x4" 3003 }, 3004 { 3005 "BriefDescription": "Cacheable loads delayed with L1D block code", 3006 "Counter": "0,1,2,3", 3007 "EventCode": "0x6", 3008 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3009 "SampleAfterValue": "200000", 3010 "UMask": "0x8" 3011 } 3012] 3013