1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "All references to the L1 data cache", 52 "Counter": "0,1", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.ANY", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1 data cacheable reads and writes", 60 "Counter": "0,1", 61 "EventCode": "0x43", 62 "EventName": "L1D_ALL_REF.CACHEABLE", 63 "SampleAfterValue": "2000000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1 data cache read in E state", 68 "Counter": "0,1", 69 "EventCode": "0x40", 70 "EventName": "L1D_CACHE_LD.E_STATE", 71 "SampleAfterValue": "2000000", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "L1 data cache read in I state (misses)", 76 "Counter": "0,1", 77 "EventCode": "0x40", 78 "EventName": "L1D_CACHE_LD.I_STATE", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "L1 data cache reads", 84 "Counter": "0,1", 85 "EventCode": "0x40", 86 "EventName": "L1D_CACHE_LD.MESI", 87 "SampleAfterValue": "2000000", 88 "UMask": "0xf" 89 }, 90 { 91 "BriefDescription": "L1 data cache read in M state", 92 "Counter": "0,1", 93 "EventCode": "0x40", 94 "EventName": "L1D_CACHE_LD.M_STATE", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x8" 97 }, 98 { 99 "BriefDescription": "L1 data cache read in S state", 100 "Counter": "0,1", 101 "EventCode": "0x40", 102 "EventName": "L1D_CACHE_LD.S_STATE", 103 "SampleAfterValue": "2000000", 104 "UMask": "0x2" 105 }, 106 { 107 "BriefDescription": "L1 data cache load locks in E state", 108 "Counter": "0,1", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.E_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x4" 113 }, 114 { 115 "BriefDescription": "L1 data cache load lock hits", 116 "Counter": "0,1", 117 "EventCode": "0x42", 118 "EventName": "L1D_CACHE_LOCK.HIT", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "L1 data cache load locks in M state", 124 "Counter": "0,1", 125 "EventCode": "0x42", 126 "EventName": "L1D_CACHE_LOCK.M_STATE", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x8" 129 }, 130 { 131 "BriefDescription": "L1 data cache load locks in S state", 132 "Counter": "0,1", 133 "EventCode": "0x42", 134 "EventName": "L1D_CACHE_LOCK.S_STATE", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x2" 137 }, 138 { 139 "BriefDescription": "L1D load lock accepted in fill buffer", 140 "Counter": "0,1", 141 "EventCode": "0x53", 142 "EventName": "L1D_CACHE_LOCK_FB_HIT", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 148 "Counter": "0,1", 149 "EventCode": "0x52", 150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "L1 data cache stores in E state", 156 "Counter": "0,1", 157 "EventCode": "0x41", 158 "EventName": "L1D_CACHE_ST.E_STATE", 159 "SampleAfterValue": "2000000", 160 "UMask": "0x4" 161 }, 162 { 163 "BriefDescription": "L1 data cache stores in M state", 164 "Counter": "0,1", 165 "EventCode": "0x41", 166 "EventName": "L1D_CACHE_ST.M_STATE", 167 "SampleAfterValue": "2000000", 168 "UMask": "0x8" 169 }, 170 { 171 "BriefDescription": "L1 data cache stores in S state", 172 "Counter": "0,1", 173 "EventCode": "0x41", 174 "EventName": "L1D_CACHE_ST.S_STATE", 175 "SampleAfterValue": "2000000", 176 "UMask": "0x2" 177 }, 178 { 179 "BriefDescription": "L1D hardware prefetch misses", 180 "Counter": "0,1", 181 "EventCode": "0x4E", 182 "EventName": "L1D_PREFETCH.MISS", 183 "SampleAfterValue": "200000", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "L1D hardware prefetch requests", 188 "Counter": "0,1", 189 "EventCode": "0x4E", 190 "EventName": "L1D_PREFETCH.REQUESTS", 191 "SampleAfterValue": "200000", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "L1D hardware prefetch requests triggered", 196 "Counter": "0,1", 197 "EventCode": "0x4E", 198 "EventName": "L1D_PREFETCH.TRIGGERS", 199 "SampleAfterValue": "200000", 200 "UMask": "0x4" 201 }, 202 { 203 "BriefDescription": "L1 writebacks to L2 in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x28", 206 "EventName": "L1D_WB_L2.E_STATE", 207 "SampleAfterValue": "100000", 208 "UMask": "0x4" 209 }, 210 { 211 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x28", 214 "EventName": "L1D_WB_L2.I_STATE", 215 "SampleAfterValue": "100000", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "All L1 writebacks to L2", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x28", 222 "EventName": "L1D_WB_L2.MESI", 223 "SampleAfterValue": "100000", 224 "UMask": "0xf" 225 }, 226 { 227 "BriefDescription": "L1 writebacks to L2 in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x28", 230 "EventName": "L1D_WB_L2.M_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x8" 233 }, 234 { 235 "BriefDescription": "L1 writebacks to L2 in S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x28", 238 "EventName": "L1D_WB_L2.S_STATE", 239 "SampleAfterValue": "100000", 240 "UMask": "0x2" 241 }, 242 { 243 "BriefDescription": "All L2 data requests", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x26", 246 "EventName": "L2_DATA_RQSTS.ANY", 247 "SampleAfterValue": "200000", 248 "UMask": "0xff" 249 }, 250 { 251 "BriefDescription": "L2 data demand loads in E state", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x26", 254 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 255 "SampleAfterValue": "200000", 256 "UMask": "0x4" 257 }, 258 { 259 "BriefDescription": "L2 data demand loads in I state (misses)", 260 "Counter": "0,1,2,3", 261 "EventCode": "0x26", 262 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 263 "SampleAfterValue": "200000", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "L2 data demand requests", 268 "Counter": "0,1,2,3", 269 "EventCode": "0x26", 270 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 271 "SampleAfterValue": "200000", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "L2 data demand loads in M state", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 279 "SampleAfterValue": "200000", 280 "UMask": "0x8" 281 }, 282 { 283 "BriefDescription": "L2 data demand loads in S state", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x26", 286 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 287 "SampleAfterValue": "200000", 288 "UMask": "0x2" 289 }, 290 { 291 "BriefDescription": "L2 data prefetches in E state", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x26", 294 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 295 "SampleAfterValue": "200000", 296 "UMask": "0x40" 297 }, 298 { 299 "BriefDescription": "L2 data prefetches in the I state (misses)", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x26", 302 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 303 "SampleAfterValue": "200000", 304 "UMask": "0x10" 305 }, 306 { 307 "BriefDescription": "All L2 data prefetches", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x26", 310 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 311 "SampleAfterValue": "200000", 312 "UMask": "0xf0" 313 }, 314 { 315 "BriefDescription": "L2 data prefetches in M state", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x26", 318 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 319 "SampleAfterValue": "200000", 320 "UMask": "0x80" 321 }, 322 { 323 "BriefDescription": "L2 data prefetches in the S state", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x26", 326 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 327 "SampleAfterValue": "200000", 328 "UMask": "0x20" 329 }, 330 { 331 "BriefDescription": "L2 lines allocated", 332 "Counter": "0,1,2,3", 333 "EventCode": "0xF1", 334 "EventName": "L2_LINES_IN.ANY", 335 "SampleAfterValue": "100000", 336 "UMask": "0x7" 337 }, 338 { 339 "BriefDescription": "L2 lines allocated in the E state", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xF1", 342 "EventName": "L2_LINES_IN.E_STATE", 343 "SampleAfterValue": "100000", 344 "UMask": "0x4" 345 }, 346 { 347 "BriefDescription": "L2 lines allocated in the S state", 348 "Counter": "0,1,2,3", 349 "EventCode": "0xF1", 350 "EventName": "L2_LINES_IN.S_STATE", 351 "SampleAfterValue": "100000", 352 "UMask": "0x2" 353 }, 354 { 355 "BriefDescription": "L2 lines evicted", 356 "Counter": "0,1,2,3", 357 "EventCode": "0xF2", 358 "EventName": "L2_LINES_OUT.ANY", 359 "SampleAfterValue": "100000", 360 "UMask": "0xf" 361 }, 362 { 363 "BriefDescription": "L2 lines evicted by a demand request", 364 "Counter": "0,1,2,3", 365 "EventCode": "0xF2", 366 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 367 "SampleAfterValue": "100000", 368 "UMask": "0x1" 369 }, 370 { 371 "BriefDescription": "L2 modified lines evicted by a demand request", 372 "Counter": "0,1,2,3", 373 "EventCode": "0xF2", 374 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 375 "SampleAfterValue": "100000", 376 "UMask": "0x2" 377 }, 378 { 379 "BriefDescription": "L2 lines evicted by a prefetch request", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xF2", 382 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 383 "SampleAfterValue": "100000", 384 "UMask": "0x4" 385 }, 386 { 387 "BriefDescription": "L2 modified lines evicted by a prefetch request", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF2", 390 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 391 "SampleAfterValue": "100000", 392 "UMask": "0x8" 393 }, 394 { 395 "BriefDescription": "L2 instruction fetches", 396 "Counter": "0,1,2,3", 397 "EventCode": "0x24", 398 "EventName": "L2_RQSTS.IFETCHES", 399 "SampleAfterValue": "200000", 400 "UMask": "0x30" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch hits", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x24", 406 "EventName": "L2_RQSTS.IFETCH_HIT", 407 "SampleAfterValue": "200000", 408 "UMask": "0x10" 409 }, 410 { 411 "BriefDescription": "L2 instruction fetch misses", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x24", 414 "EventName": "L2_RQSTS.IFETCH_MISS", 415 "SampleAfterValue": "200000", 416 "UMask": "0x20" 417 }, 418 { 419 "BriefDescription": "L2 load hits", 420 "Counter": "0,1,2,3", 421 "EventCode": "0x24", 422 "EventName": "L2_RQSTS.LD_HIT", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 load misses", 428 "Counter": "0,1,2,3", 429 "EventCode": "0x24", 430 "EventName": "L2_RQSTS.LD_MISS", 431 "SampleAfterValue": "200000", 432 "UMask": "0x2" 433 }, 434 { 435 "BriefDescription": "L2 requests", 436 "Counter": "0,1,2,3", 437 "EventCode": "0x24", 438 "EventName": "L2_RQSTS.LOADS", 439 "SampleAfterValue": "200000", 440 "UMask": "0x3" 441 }, 442 { 443 "BriefDescription": "All L2 misses", 444 "Counter": "0,1,2,3", 445 "EventCode": "0x24", 446 "EventName": "L2_RQSTS.MISS", 447 "SampleAfterValue": "200000", 448 "UMask": "0xaa" 449 }, 450 { 451 "BriefDescription": "All L2 prefetches", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x24", 454 "EventName": "L2_RQSTS.PREFETCHES", 455 "SampleAfterValue": "200000", 456 "UMask": "0xc0" 457 }, 458 { 459 "BriefDescription": "L2 prefetch hits", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x24", 462 "EventName": "L2_RQSTS.PREFETCH_HIT", 463 "SampleAfterValue": "200000", 464 "UMask": "0x40" 465 }, 466 { 467 "BriefDescription": "L2 prefetch misses", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x24", 470 "EventName": "L2_RQSTS.PREFETCH_MISS", 471 "SampleAfterValue": "200000", 472 "UMask": "0x80" 473 }, 474 { 475 "BriefDescription": "All L2 requests", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x24", 478 "EventName": "L2_RQSTS.REFERENCES", 479 "SampleAfterValue": "200000", 480 "UMask": "0xff" 481 }, 482 { 483 "BriefDescription": "L2 RFO requests", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x24", 486 "EventName": "L2_RQSTS.RFOS", 487 "SampleAfterValue": "200000", 488 "UMask": "0xc" 489 }, 490 { 491 "BriefDescription": "L2 RFO hits", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x24", 494 "EventName": "L2_RQSTS.RFO_HIT", 495 "SampleAfterValue": "200000", 496 "UMask": "0x4" 497 }, 498 { 499 "BriefDescription": "L2 RFO misses", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x24", 502 "EventName": "L2_RQSTS.RFO_MISS", 503 "SampleAfterValue": "200000", 504 "UMask": "0x8" 505 }, 506 { 507 "BriefDescription": "All L2 transactions", 508 "Counter": "0,1,2,3", 509 "EventCode": "0xF0", 510 "EventName": "L2_TRANSACTIONS.ANY", 511 "SampleAfterValue": "200000", 512 "UMask": "0x80" 513 }, 514 { 515 "BriefDescription": "L2 fill transactions", 516 "Counter": "0,1,2,3", 517 "EventCode": "0xF0", 518 "EventName": "L2_TRANSACTIONS.FILL", 519 "SampleAfterValue": "200000", 520 "UMask": "0x20" 521 }, 522 { 523 "BriefDescription": "L2 instruction fetch transactions", 524 "Counter": "0,1,2,3", 525 "EventCode": "0xF0", 526 "EventName": "L2_TRANSACTIONS.IFETCH", 527 "SampleAfterValue": "200000", 528 "UMask": "0x4" 529 }, 530 { 531 "BriefDescription": "L1D writeback to L2 transactions", 532 "Counter": "0,1,2,3", 533 "EventCode": "0xF0", 534 "EventName": "L2_TRANSACTIONS.L1D_WB", 535 "SampleAfterValue": "200000", 536 "UMask": "0x10" 537 }, 538 { 539 "BriefDescription": "L2 Load transactions", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xF0", 542 "EventName": "L2_TRANSACTIONS.LOAD", 543 "SampleAfterValue": "200000", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "L2 prefetch transactions", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xF0", 550 "EventName": "L2_TRANSACTIONS.PREFETCH", 551 "SampleAfterValue": "200000", 552 "UMask": "0x8" 553 }, 554 { 555 "BriefDescription": "L2 RFO transactions", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xF0", 558 "EventName": "L2_TRANSACTIONS.RFO", 559 "SampleAfterValue": "200000", 560 "UMask": "0x2" 561 }, 562 { 563 "BriefDescription": "L2 writeback to LLC transactions", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xF0", 566 "EventName": "L2_TRANSACTIONS.WB", 567 "SampleAfterValue": "200000", 568 "UMask": "0x40" 569 }, 570 { 571 "BriefDescription": "L2 demand lock RFOs in E state", 572 "Counter": "0,1,2,3", 573 "EventCode": "0x27", 574 "EventName": "L2_WRITE.LOCK.E_STATE", 575 "SampleAfterValue": "100000", 576 "UMask": "0x40" 577 }, 578 { 579 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 580 "Counter": "0,1,2,3", 581 "EventCode": "0x27", 582 "EventName": "L2_WRITE.LOCK.HIT", 583 "SampleAfterValue": "100000", 584 "UMask": "0xe0" 585 }, 586 { 587 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 588 "Counter": "0,1,2,3", 589 "EventCode": "0x27", 590 "EventName": "L2_WRITE.LOCK.I_STATE", 591 "SampleAfterValue": "100000", 592 "UMask": "0x10" 593 }, 594 { 595 "BriefDescription": "All demand L2 lock RFOs", 596 "Counter": "0,1,2,3", 597 "EventCode": "0x27", 598 "EventName": "L2_WRITE.LOCK.MESI", 599 "SampleAfterValue": "100000", 600 "UMask": "0xf0" 601 }, 602 { 603 "BriefDescription": "L2 demand lock RFOs in M state", 604 "Counter": "0,1,2,3", 605 "EventCode": "0x27", 606 "EventName": "L2_WRITE.LOCK.M_STATE", 607 "SampleAfterValue": "100000", 608 "UMask": "0x80" 609 }, 610 { 611 "BriefDescription": "L2 demand lock RFOs in S state", 612 "Counter": "0,1,2,3", 613 "EventCode": "0x27", 614 "EventName": "L2_WRITE.LOCK.S_STATE", 615 "SampleAfterValue": "100000", 616 "UMask": "0x20" 617 }, 618 { 619 "BriefDescription": "All L2 demand store RFOs that hit the cache", 620 "Counter": "0,1,2,3", 621 "EventCode": "0x27", 622 "EventName": "L2_WRITE.RFO.HIT", 623 "SampleAfterValue": "100000", 624 "UMask": "0xe" 625 }, 626 { 627 "BriefDescription": "L2 demand store RFOs in I state (misses)", 628 "Counter": "0,1,2,3", 629 "EventCode": "0x27", 630 "EventName": "L2_WRITE.RFO.I_STATE", 631 "SampleAfterValue": "100000", 632 "UMask": "0x1" 633 }, 634 { 635 "BriefDescription": "All L2 demand store RFOs", 636 "Counter": "0,1,2,3", 637 "EventCode": "0x27", 638 "EventName": "L2_WRITE.RFO.MESI", 639 "SampleAfterValue": "100000", 640 "UMask": "0xf" 641 }, 642 { 643 "BriefDescription": "L2 demand store RFOs in M state", 644 "Counter": "0,1,2,3", 645 "EventCode": "0x27", 646 "EventName": "L2_WRITE.RFO.M_STATE", 647 "SampleAfterValue": "100000", 648 "UMask": "0x8" 649 }, 650 { 651 "BriefDescription": "L2 demand store RFOs in S state", 652 "Counter": "0,1,2,3", 653 "EventCode": "0x27", 654 "EventName": "L2_WRITE.RFO.S_STATE", 655 "SampleAfterValue": "100000", 656 "UMask": "0x2" 657 }, 658 { 659 "BriefDescription": "Longest latency cache miss", 660 "Counter": "0,1,2,3", 661 "EventCode": "0x2E", 662 "EventName": "LONGEST_LAT_CACHE.MISS", 663 "SampleAfterValue": "100000", 664 "UMask": "0x41" 665 }, 666 { 667 "BriefDescription": "Longest latency cache reference", 668 "Counter": "0,1,2,3", 669 "EventCode": "0x2E", 670 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 671 "SampleAfterValue": "200000", 672 "UMask": "0x4f" 673 }, 674 { 675 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 676 "Counter": "3", 677 "EventCode": "0xB", 678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 679 "MSRIndex": "0x3F6", 680 "PEBS": "2", 681 "SampleAfterValue": "2000000", 682 "UMask": "0x10" 683 }, 684 { 685 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 686 "Counter": "3", 687 "EventCode": "0xB", 688 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 689 "MSRIndex": "0x3F6", 690 "MSRValue": "0x400", 691 "PEBS": "2", 692 "SampleAfterValue": "100", 693 "UMask": "0x10" 694 }, 695 { 696 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 697 "Counter": "3", 698 "EventCode": "0xB", 699 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 700 "MSRIndex": "0x3F6", 701 "MSRValue": "0x80", 702 "PEBS": "2", 703 "SampleAfterValue": "1000", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 711 "MSRIndex": "0x3F6", 712 "MSRValue": "0x10", 713 "PEBS": "2", 714 "SampleAfterValue": "10000", 715 "UMask": "0x10" 716 }, 717 { 718 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 719 "Counter": "3", 720 "EventCode": "0xB", 721 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 722 "MSRIndex": "0x3F6", 723 "MSRValue": "0x4000", 724 "PEBS": "2", 725 "SampleAfterValue": "5", 726 "UMask": "0x10" 727 }, 728 { 729 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 730 "Counter": "3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x800", 735 "PEBS": "2", 736 "SampleAfterValue": "50", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 741 "Counter": "3", 742 "EventCode": "0xB", 743 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 744 "MSRIndex": "0x3F6", 745 "MSRValue": "0x100", 746 "PEBS": "2", 747 "SampleAfterValue": "500", 748 "UMask": "0x10" 749 }, 750 { 751 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 752 "Counter": "3", 753 "EventCode": "0xB", 754 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 755 "MSRIndex": "0x3F6", 756 "MSRValue": "0x20", 757 "PEBS": "2", 758 "SampleAfterValue": "5000", 759 "UMask": "0x10" 760 }, 761 { 762 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 763 "Counter": "3", 764 "EventCode": "0xB", 765 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 766 "MSRIndex": "0x3F6", 767 "MSRValue": "0x8000", 768 "PEBS": "2", 769 "SampleAfterValue": "3", 770 "UMask": "0x10" 771 }, 772 { 773 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 774 "Counter": "3", 775 "EventCode": "0xB", 776 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 777 "MSRIndex": "0x3F6", 778 "MSRValue": "0x4", 779 "PEBS": "2", 780 "SampleAfterValue": "50000", 781 "UMask": "0x10" 782 }, 783 { 784 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 785 "Counter": "3", 786 "EventCode": "0xB", 787 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 788 "MSRIndex": "0x3F6", 789 "MSRValue": "0x1000", 790 "PEBS": "2", 791 "SampleAfterValue": "20", 792 "UMask": "0x10" 793 }, 794 { 795 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 796 "Counter": "3", 797 "EventCode": "0xB", 798 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 799 "MSRIndex": "0x3F6", 800 "MSRValue": "0x200", 801 "PEBS": "2", 802 "SampleAfterValue": "200", 803 "UMask": "0x10" 804 }, 805 { 806 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 807 "Counter": "3", 808 "EventCode": "0xB", 809 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 810 "MSRIndex": "0x3F6", 811 "MSRValue": "0x40", 812 "PEBS": "2", 813 "SampleAfterValue": "2000", 814 "UMask": "0x10" 815 }, 816 { 817 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 818 "Counter": "3", 819 "EventCode": "0xB", 820 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 821 "MSRIndex": "0x3F6", 822 "MSRValue": "0x8", 823 "PEBS": "2", 824 "SampleAfterValue": "20000", 825 "UMask": "0x10" 826 }, 827 { 828 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 829 "Counter": "3", 830 "EventCode": "0xB", 831 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 832 "MSRIndex": "0x3F6", 833 "MSRValue": "0x2000", 834 "PEBS": "2", 835 "SampleAfterValue": "10", 836 "UMask": "0x10" 837 }, 838 { 839 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 840 "Counter": "0,1,2,3", 841 "EventCode": "0xB", 842 "EventName": "MEM_INST_RETIRED.LOADS", 843 "PEBS": "1", 844 "SampleAfterValue": "2000000", 845 "UMask": "0x1" 846 }, 847 { 848 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 849 "Counter": "0,1,2,3", 850 "EventCode": "0xB", 851 "EventName": "MEM_INST_RETIRED.STORES", 852 "PEBS": "1", 853 "SampleAfterValue": "2000000", 854 "UMask": "0x2" 855 }, 856 { 857 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 858 "Counter": "0,1,2,3", 859 "EventCode": "0xCB", 860 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 861 "PEBS": "1", 862 "SampleAfterValue": "200000", 863 "UMask": "0x40" 864 }, 865 { 866 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 867 "Counter": "0,1,2,3", 868 "EventCode": "0xCB", 869 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 870 "PEBS": "1", 871 "SampleAfterValue": "2000000", 872 "UMask": "0x1" 873 }, 874 { 875 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 876 "Counter": "0,1,2,3", 877 "EventCode": "0xCB", 878 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 879 "PEBS": "1", 880 "SampleAfterValue": "200000", 881 "UMask": "0x2" 882 }, 883 { 884 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 885 "Counter": "0,1,2,3", 886 "EventCode": "0xCB", 887 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 888 "PEBS": "1", 889 "SampleAfterValue": "10000", 890 "UMask": "0x10" 891 }, 892 { 893 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 894 "Counter": "0,1,2,3", 895 "EventCode": "0xCB", 896 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 897 "PEBS": "1", 898 "SampleAfterValue": "40000", 899 "UMask": "0x4" 900 }, 901 { 902 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 903 "Counter": "0,1,2,3", 904 "EventCode": "0xCB", 905 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 906 "PEBS": "1", 907 "SampleAfterValue": "40000", 908 "UMask": "0x8" 909 }, 910 { 911 "BriefDescription": "Offcore L1 data cache writebacks", 912 "Counter": "0,1,2,3", 913 "EventCode": "0xB0", 914 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 915 "SampleAfterValue": "100000", 916 "UMask": "0x40" 917 }, 918 { 919 "BriefDescription": "Offcore requests blocked due to Super Queue full", 920 "Counter": "0,1,2,3", 921 "EventCode": "0xB2", 922 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 923 "SampleAfterValue": "100000", 924 "UMask": "0x1" 925 }, 926 { 927 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 928 "Counter": "2", 929 "EventCode": "0xB7", 930 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 931 "MSRIndex": "0x1A6", 932 "MSRValue": "0x7F11", 933 "SampleAfterValue": "100000", 934 "UMask": "0x1" 935 }, 936 { 937 "BriefDescription": "All offcore data reads", 938 "Counter": "2", 939 "EventCode": "0xB7", 940 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 941 "MSRIndex": "0x1A6", 942 "MSRValue": "0xFF11", 943 "SampleAfterValue": "100000", 944 "UMask": "0x1" 945 }, 946 { 947 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 948 "Counter": "2", 949 "EventCode": "0xB7", 950 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 951 "MSRIndex": "0x1A6", 952 "MSRValue": "0x8011", 953 "SampleAfterValue": "100000", 954 "UMask": "0x1" 955 }, 956 { 957 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 958 "Counter": "2", 959 "EventCode": "0xB7", 960 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 961 "MSRIndex": "0x1A6", 962 "MSRValue": "0x111", 963 "SampleAfterValue": "100000", 964 "UMask": "0x1" 965 }, 966 { 967 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 968 "Counter": "2", 969 "EventCode": "0xB7", 970 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 971 "MSRIndex": "0x1A6", 972 "MSRValue": "0x211", 973 "SampleAfterValue": "100000", 974 "UMask": "0x1" 975 }, 976 { 977 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 978 "Counter": "2", 979 "EventCode": "0xB7", 980 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 981 "MSRIndex": "0x1A6", 982 "MSRValue": "0x411", 983 "SampleAfterValue": "100000", 984 "UMask": "0x1" 985 }, 986 { 987 "BriefDescription": "Offcore data reads satisfied by the LLC", 988 "Counter": "2", 989 "EventCode": "0xB7", 990 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 991 "MSRIndex": "0x1A6", 992 "MSRValue": "0x711", 993 "SampleAfterValue": "100000", 994 "UMask": "0x1" 995 }, 996 { 997 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 998 "Counter": "2", 999 "EventCode": "0xB7", 1000 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1001 "MSRIndex": "0x1A6", 1002 "MSRValue": "0x4711", 1003 "SampleAfterValue": "100000", 1004 "UMask": "0x1" 1005 }, 1006 { 1007 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1008 "Counter": "2", 1009 "EventCode": "0xB7", 1010 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1011 "MSRIndex": "0x1A6", 1012 "MSRValue": "0x1811", 1013 "SampleAfterValue": "100000", 1014 "UMask": "0x1" 1015 }, 1016 { 1017 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1018 "Counter": "2", 1019 "EventCode": "0xB7", 1020 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1021 "MSRIndex": "0x1A6", 1022 "MSRValue": "0x3811", 1023 "SampleAfterValue": "100000", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1028 "Counter": "2", 1029 "EventCode": "0xB7", 1030 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1031 "MSRIndex": "0x1A6", 1032 "MSRValue": "0x1011", 1033 "SampleAfterValue": "100000", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1038 "Counter": "2", 1039 "EventCode": "0xB7", 1040 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1041 "MSRIndex": "0x1A6", 1042 "MSRValue": "0x811", 1043 "SampleAfterValue": "100000", 1044 "UMask": "0x1" 1045 }, 1046 { 1047 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1048 "Counter": "2", 1049 "EventCode": "0xB7", 1050 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1051 "MSRIndex": "0x1A6", 1052 "MSRValue": "0x7F44", 1053 "SampleAfterValue": "100000", 1054 "UMask": "0x1" 1055 }, 1056 { 1057 "BriefDescription": "All offcore code reads", 1058 "Counter": "2", 1059 "EventCode": "0xB7", 1060 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1061 "MSRIndex": "0x1A6", 1062 "MSRValue": "0xFF44", 1063 "SampleAfterValue": "100000", 1064 "UMask": "0x1" 1065 }, 1066 { 1067 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1068 "Counter": "2", 1069 "EventCode": "0xB7", 1070 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1071 "MSRIndex": "0x1A6", 1072 "MSRValue": "0x8044", 1073 "SampleAfterValue": "100000", 1074 "UMask": "0x1" 1075 }, 1076 { 1077 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1078 "Counter": "2", 1079 "EventCode": "0xB7", 1080 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1081 "MSRIndex": "0x1A6", 1082 "MSRValue": "0x144", 1083 "SampleAfterValue": "100000", 1084 "UMask": "0x1" 1085 }, 1086 { 1087 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1088 "Counter": "2", 1089 "EventCode": "0xB7", 1090 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1091 "MSRIndex": "0x1A6", 1092 "MSRValue": "0x244", 1093 "SampleAfterValue": "100000", 1094 "UMask": "0x1" 1095 }, 1096 { 1097 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1098 "Counter": "2", 1099 "EventCode": "0xB7", 1100 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1101 "MSRIndex": "0x1A6", 1102 "MSRValue": "0x444", 1103 "SampleAfterValue": "100000", 1104 "UMask": "0x1" 1105 }, 1106 { 1107 "BriefDescription": "Offcore code reads satisfied by the LLC", 1108 "Counter": "2", 1109 "EventCode": "0xB7", 1110 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1111 "MSRIndex": "0x1A6", 1112 "MSRValue": "0x744", 1113 "SampleAfterValue": "100000", 1114 "UMask": "0x1" 1115 }, 1116 { 1117 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1118 "Counter": "2", 1119 "EventCode": "0xB7", 1120 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1121 "MSRIndex": "0x1A6", 1122 "MSRValue": "0x4744", 1123 "SampleAfterValue": "100000", 1124 "UMask": "0x1" 1125 }, 1126 { 1127 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1128 "Counter": "2", 1129 "EventCode": "0xB7", 1130 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1131 "MSRIndex": "0x1A6", 1132 "MSRValue": "0x1844", 1133 "SampleAfterValue": "100000", 1134 "UMask": "0x1" 1135 }, 1136 { 1137 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1138 "Counter": "2", 1139 "EventCode": "0xB7", 1140 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1141 "MSRIndex": "0x1A6", 1142 "MSRValue": "0x3844", 1143 "SampleAfterValue": "100000", 1144 "UMask": "0x1" 1145 }, 1146 { 1147 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1148 "Counter": "2", 1149 "EventCode": "0xB7", 1150 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1151 "MSRIndex": "0x1A6", 1152 "MSRValue": "0x1044", 1153 "SampleAfterValue": "100000", 1154 "UMask": "0x1" 1155 }, 1156 { 1157 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1158 "Counter": "2", 1159 "EventCode": "0xB7", 1160 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1161 "MSRIndex": "0x1A6", 1162 "MSRValue": "0x844", 1163 "SampleAfterValue": "100000", 1164 "UMask": "0x1" 1165 }, 1166 { 1167 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1168 "Counter": "2", 1169 "EventCode": "0xB7", 1170 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1171 "MSRIndex": "0x1A6", 1172 "MSRValue": "0x7FFF", 1173 "SampleAfterValue": "100000", 1174 "UMask": "0x1" 1175 }, 1176 { 1177 "BriefDescription": "All offcore requests", 1178 "Counter": "2", 1179 "EventCode": "0xB7", 1180 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1181 "MSRIndex": "0x1A6", 1182 "MSRValue": "0xFFFF", 1183 "SampleAfterValue": "100000", 1184 "UMask": "0x1" 1185 }, 1186 { 1187 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1188 "Counter": "2", 1189 "EventCode": "0xB7", 1190 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1191 "MSRIndex": "0x1A6", 1192 "MSRValue": "0x80FF", 1193 "SampleAfterValue": "100000", 1194 "UMask": "0x1" 1195 }, 1196 { 1197 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1198 "Counter": "2", 1199 "EventCode": "0xB7", 1200 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1201 "MSRIndex": "0x1A6", 1202 "MSRValue": "0x1FF", 1203 "SampleAfterValue": "100000", 1204 "UMask": "0x1" 1205 }, 1206 { 1207 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1208 "Counter": "2", 1209 "EventCode": "0xB7", 1210 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1211 "MSRIndex": "0x1A6", 1212 "MSRValue": "0x2FF", 1213 "SampleAfterValue": "100000", 1214 "UMask": "0x1" 1215 }, 1216 { 1217 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1218 "Counter": "2", 1219 "EventCode": "0xB7", 1220 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1221 "MSRIndex": "0x1A6", 1222 "MSRValue": "0x4FF", 1223 "SampleAfterValue": "100000", 1224 "UMask": "0x1" 1225 }, 1226 { 1227 "BriefDescription": "Offcore requests satisfied by the LLC", 1228 "Counter": "2", 1229 "EventCode": "0xB7", 1230 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1231 "MSRIndex": "0x1A6", 1232 "MSRValue": "0x7FF", 1233 "SampleAfterValue": "100000", 1234 "UMask": "0x1" 1235 }, 1236 { 1237 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1238 "Counter": "2", 1239 "EventCode": "0xB7", 1240 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1241 "MSRIndex": "0x1A6", 1242 "MSRValue": "0x47FF", 1243 "SampleAfterValue": "100000", 1244 "UMask": "0x1" 1245 }, 1246 { 1247 "BriefDescription": "Offcore requests satisfied by a remote cache", 1248 "Counter": "2", 1249 "EventCode": "0xB7", 1250 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1251 "MSRIndex": "0x1A6", 1252 "MSRValue": "0x18FF", 1253 "SampleAfterValue": "100000", 1254 "UMask": "0x1" 1255 }, 1256 { 1257 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1258 "Counter": "2", 1259 "EventCode": "0xB7", 1260 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1261 "MSRIndex": "0x1A6", 1262 "MSRValue": "0x38FF", 1263 "SampleAfterValue": "100000", 1264 "UMask": "0x1" 1265 }, 1266 { 1267 "BriefDescription": "Offcore requests that HIT in a remote cache", 1268 "Counter": "2", 1269 "EventCode": "0xB7", 1270 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1271 "MSRIndex": "0x1A6", 1272 "MSRValue": "0x10FF", 1273 "SampleAfterValue": "100000", 1274 "UMask": "0x1" 1275 }, 1276 { 1277 "BriefDescription": "Offcore requests that HITM in a remote cache", 1278 "Counter": "2", 1279 "EventCode": "0xB7", 1280 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1281 "MSRIndex": "0x1A6", 1282 "MSRValue": "0x8FF", 1283 "SampleAfterValue": "100000", 1284 "UMask": "0x1" 1285 }, 1286 { 1287 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1288 "Counter": "2", 1289 "EventCode": "0xB7", 1290 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1291 "MSRIndex": "0x1A6", 1292 "MSRValue": "0x7F22", 1293 "SampleAfterValue": "100000", 1294 "UMask": "0x1" 1295 }, 1296 { 1297 "BriefDescription": "All offcore RFO requests", 1298 "Counter": "2", 1299 "EventCode": "0xB7", 1300 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1301 "MSRIndex": "0x1A6", 1302 "MSRValue": "0xFF22", 1303 "SampleAfterValue": "100000", 1304 "UMask": "0x1" 1305 }, 1306 { 1307 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1308 "Counter": "2", 1309 "EventCode": "0xB7", 1310 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1311 "MSRIndex": "0x1A6", 1312 "MSRValue": "0x8022", 1313 "SampleAfterValue": "100000", 1314 "UMask": "0x1" 1315 }, 1316 { 1317 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1318 "Counter": "2", 1319 "EventCode": "0xB7", 1320 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1321 "MSRIndex": "0x1A6", 1322 "MSRValue": "0x122", 1323 "SampleAfterValue": "100000", 1324 "UMask": "0x1" 1325 }, 1326 { 1327 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1328 "Counter": "2", 1329 "EventCode": "0xB7", 1330 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1331 "MSRIndex": "0x1A6", 1332 "MSRValue": "0x222", 1333 "SampleAfterValue": "100000", 1334 "UMask": "0x1" 1335 }, 1336 { 1337 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1338 "Counter": "2", 1339 "EventCode": "0xB7", 1340 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1341 "MSRIndex": "0x1A6", 1342 "MSRValue": "0x422", 1343 "SampleAfterValue": "100000", 1344 "UMask": "0x1" 1345 }, 1346 { 1347 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1348 "Counter": "2", 1349 "EventCode": "0xB7", 1350 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1351 "MSRIndex": "0x1A6", 1352 "MSRValue": "0x722", 1353 "SampleAfterValue": "100000", 1354 "UMask": "0x1" 1355 }, 1356 { 1357 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1358 "Counter": "2", 1359 "EventCode": "0xB7", 1360 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1361 "MSRIndex": "0x1A6", 1362 "MSRValue": "0x4722", 1363 "SampleAfterValue": "100000", 1364 "UMask": "0x1" 1365 }, 1366 { 1367 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1368 "Counter": "2", 1369 "EventCode": "0xB7", 1370 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1371 "MSRIndex": "0x1A6", 1372 "MSRValue": "0x1822", 1373 "SampleAfterValue": "100000", 1374 "UMask": "0x1" 1375 }, 1376 { 1377 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1378 "Counter": "2", 1379 "EventCode": "0xB7", 1380 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1381 "MSRIndex": "0x1A6", 1382 "MSRValue": "0x3822", 1383 "SampleAfterValue": "100000", 1384 "UMask": "0x1" 1385 }, 1386 { 1387 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1388 "Counter": "2", 1389 "EventCode": "0xB7", 1390 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1391 "MSRIndex": "0x1A6", 1392 "MSRValue": "0x1022", 1393 "SampleAfterValue": "100000", 1394 "UMask": "0x1" 1395 }, 1396 { 1397 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1398 "Counter": "2", 1399 "EventCode": "0xB7", 1400 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1401 "MSRIndex": "0x1A6", 1402 "MSRValue": "0x822", 1403 "SampleAfterValue": "100000", 1404 "UMask": "0x1" 1405 }, 1406 { 1407 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1408 "Counter": "2", 1409 "EventCode": "0xB7", 1410 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1411 "MSRIndex": "0x1A6", 1412 "MSRValue": "0x7F08", 1413 "SampleAfterValue": "100000", 1414 "UMask": "0x1" 1415 }, 1416 { 1417 "BriefDescription": "All offcore writebacks", 1418 "Counter": "2", 1419 "EventCode": "0xB7", 1420 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1421 "MSRIndex": "0x1A6", 1422 "MSRValue": "0xFF08", 1423 "SampleAfterValue": "100000", 1424 "UMask": "0x1" 1425 }, 1426 { 1427 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1428 "Counter": "2", 1429 "EventCode": "0xB7", 1430 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1431 "MSRIndex": "0x1A6", 1432 "MSRValue": "0x8008", 1433 "SampleAfterValue": "100000", 1434 "UMask": "0x1" 1435 }, 1436 { 1437 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1438 "Counter": "2", 1439 "EventCode": "0xB7", 1440 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1441 "MSRIndex": "0x1A6", 1442 "MSRValue": "0x108", 1443 "SampleAfterValue": "100000", 1444 "UMask": "0x1" 1445 }, 1446 { 1447 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1448 "Counter": "2", 1449 "EventCode": "0xB7", 1450 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1451 "MSRIndex": "0x1A6", 1452 "MSRValue": "0x408", 1453 "SampleAfterValue": "100000", 1454 "UMask": "0x1" 1455 }, 1456 { 1457 "BriefDescription": "Offcore writebacks to the LLC", 1458 "Counter": "2", 1459 "EventCode": "0xB7", 1460 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1461 "MSRIndex": "0x1A6", 1462 "MSRValue": "0x708", 1463 "SampleAfterValue": "100000", 1464 "UMask": "0x1" 1465 }, 1466 { 1467 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1468 "Counter": "2", 1469 "EventCode": "0xB7", 1470 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1471 "MSRIndex": "0x1A6", 1472 "MSRValue": "0x4708", 1473 "SampleAfterValue": "100000", 1474 "UMask": "0x1" 1475 }, 1476 { 1477 "BriefDescription": "Offcore writebacks to a remote cache", 1478 "Counter": "2", 1479 "EventCode": "0xB7", 1480 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1481 "MSRIndex": "0x1A6", 1482 "MSRValue": "0x1808", 1483 "SampleAfterValue": "100000", 1484 "UMask": "0x1" 1485 }, 1486 { 1487 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1488 "Counter": "2", 1489 "EventCode": "0xB7", 1490 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1491 "MSRIndex": "0x1A6", 1492 "MSRValue": "0x3808", 1493 "SampleAfterValue": "100000", 1494 "UMask": "0x1" 1495 }, 1496 { 1497 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1498 "Counter": "2", 1499 "EventCode": "0xB7", 1500 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1501 "MSRIndex": "0x1A6", 1502 "MSRValue": "0x1008", 1503 "SampleAfterValue": "100000", 1504 "UMask": "0x1" 1505 }, 1506 { 1507 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1508 "Counter": "2", 1509 "EventCode": "0xB7", 1510 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1511 "MSRIndex": "0x1A6", 1512 "MSRValue": "0x808", 1513 "SampleAfterValue": "100000", 1514 "UMask": "0x1" 1515 }, 1516 { 1517 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1518 "Counter": "2", 1519 "EventCode": "0xB7", 1520 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1521 "MSRIndex": "0x1A6", 1522 "MSRValue": "0x7F77", 1523 "SampleAfterValue": "100000", 1524 "UMask": "0x1" 1525 }, 1526 { 1527 "BriefDescription": "All offcore code or data read requests", 1528 "Counter": "2", 1529 "EventCode": "0xB7", 1530 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1531 "MSRIndex": "0x1A6", 1532 "MSRValue": "0xFF77", 1533 "SampleAfterValue": "100000", 1534 "UMask": "0x1" 1535 }, 1536 { 1537 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1538 "Counter": "2", 1539 "EventCode": "0xB7", 1540 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1541 "MSRIndex": "0x1A6", 1542 "MSRValue": "0x8077", 1543 "SampleAfterValue": "100000", 1544 "UMask": "0x1" 1545 }, 1546 { 1547 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1548 "Counter": "2", 1549 "EventCode": "0xB7", 1550 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1551 "MSRIndex": "0x1A6", 1552 "MSRValue": "0x177", 1553 "SampleAfterValue": "100000", 1554 "UMask": "0x1" 1555 }, 1556 { 1557 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1558 "Counter": "2", 1559 "EventCode": "0xB7", 1560 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1561 "MSRIndex": "0x1A6", 1562 "MSRValue": "0x277", 1563 "SampleAfterValue": "100000", 1564 "UMask": "0x1" 1565 }, 1566 { 1567 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1568 "Counter": "2", 1569 "EventCode": "0xB7", 1570 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1571 "MSRIndex": "0x1A6", 1572 "MSRValue": "0x477", 1573 "SampleAfterValue": "100000", 1574 "UMask": "0x1" 1575 }, 1576 { 1577 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1578 "Counter": "2", 1579 "EventCode": "0xB7", 1580 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1581 "MSRIndex": "0x1A6", 1582 "MSRValue": "0x777", 1583 "SampleAfterValue": "100000", 1584 "UMask": "0x1" 1585 }, 1586 { 1587 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1588 "Counter": "2", 1589 "EventCode": "0xB7", 1590 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1591 "MSRIndex": "0x1A6", 1592 "MSRValue": "0x4777", 1593 "SampleAfterValue": "100000", 1594 "UMask": "0x1" 1595 }, 1596 { 1597 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1598 "Counter": "2", 1599 "EventCode": "0xB7", 1600 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1601 "MSRIndex": "0x1A6", 1602 "MSRValue": "0x1877", 1603 "SampleAfterValue": "100000", 1604 "UMask": "0x1" 1605 }, 1606 { 1607 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1608 "Counter": "2", 1609 "EventCode": "0xB7", 1610 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1611 "MSRIndex": "0x1A6", 1612 "MSRValue": "0x3877", 1613 "SampleAfterValue": "100000", 1614 "UMask": "0x1" 1615 }, 1616 { 1617 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1618 "Counter": "2", 1619 "EventCode": "0xB7", 1620 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1621 "MSRIndex": "0x1A6", 1622 "MSRValue": "0x1077", 1623 "SampleAfterValue": "100000", 1624 "UMask": "0x1" 1625 }, 1626 { 1627 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1628 "Counter": "2", 1629 "EventCode": "0xB7", 1630 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1631 "MSRIndex": "0x1A6", 1632 "MSRValue": "0x877", 1633 "SampleAfterValue": "100000", 1634 "UMask": "0x1" 1635 }, 1636 { 1637 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1638 "Counter": "2", 1639 "EventCode": "0xB7", 1640 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1641 "MSRIndex": "0x1A6", 1642 "MSRValue": "0x7F33", 1643 "SampleAfterValue": "100000", 1644 "UMask": "0x1" 1645 }, 1646 { 1647 "BriefDescription": "Offcore request = all data, response = any location", 1648 "Counter": "2", 1649 "EventCode": "0xB7", 1650 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1651 "MSRIndex": "0x1A6", 1652 "MSRValue": "0xFF33", 1653 "SampleAfterValue": "100000", 1654 "UMask": "0x1" 1655 }, 1656 { 1657 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1658 "Counter": "2", 1659 "EventCode": "0xB7", 1660 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1661 "MSRIndex": "0x1A6", 1662 "MSRValue": "0x8033", 1663 "SampleAfterValue": "100000", 1664 "UMask": "0x1" 1665 }, 1666 { 1667 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1668 "Counter": "2", 1669 "EventCode": "0xB7", 1670 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1671 "MSRIndex": "0x1A6", 1672 "MSRValue": "0x133", 1673 "SampleAfterValue": "100000", 1674 "UMask": "0x1" 1675 }, 1676 { 1677 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1678 "Counter": "2", 1679 "EventCode": "0xB7", 1680 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1681 "MSRIndex": "0x1A6", 1682 "MSRValue": "0x233", 1683 "SampleAfterValue": "100000", 1684 "UMask": "0x1" 1685 }, 1686 { 1687 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1688 "Counter": "2", 1689 "EventCode": "0xB7", 1690 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1691 "MSRIndex": "0x1A6", 1692 "MSRValue": "0x433", 1693 "SampleAfterValue": "100000", 1694 "UMask": "0x1" 1695 }, 1696 { 1697 "BriefDescription": "Offcore request = all data, response = local cache", 1698 "Counter": "2", 1699 "EventCode": "0xB7", 1700 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1701 "MSRIndex": "0x1A6", 1702 "MSRValue": "0x733", 1703 "SampleAfterValue": "100000", 1704 "UMask": "0x1" 1705 }, 1706 { 1707 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1708 "Counter": "2", 1709 "EventCode": "0xB7", 1710 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1711 "MSRIndex": "0x1A6", 1712 "MSRValue": "0x4733", 1713 "SampleAfterValue": "100000", 1714 "UMask": "0x1" 1715 }, 1716 { 1717 "BriefDescription": "Offcore request = all data, response = remote cache", 1718 "Counter": "2", 1719 "EventCode": "0xB7", 1720 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1721 "MSRIndex": "0x1A6", 1722 "MSRValue": "0x1833", 1723 "SampleAfterValue": "100000", 1724 "UMask": "0x1" 1725 }, 1726 { 1727 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1728 "Counter": "2", 1729 "EventCode": "0xB7", 1730 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1731 "MSRIndex": "0x1A6", 1732 "MSRValue": "0x3833", 1733 "SampleAfterValue": "100000", 1734 "UMask": "0x1" 1735 }, 1736 { 1737 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1738 "Counter": "2", 1739 "EventCode": "0xB7", 1740 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1741 "MSRIndex": "0x1A6", 1742 "MSRValue": "0x1033", 1743 "SampleAfterValue": "100000", 1744 "UMask": "0x1" 1745 }, 1746 { 1747 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1748 "Counter": "2", 1749 "EventCode": "0xB7", 1750 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1751 "MSRIndex": "0x1A6", 1752 "MSRValue": "0x833", 1753 "SampleAfterValue": "100000", 1754 "UMask": "0x1" 1755 }, 1756 { 1757 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1758 "Counter": "2", 1759 "EventCode": "0xB7", 1760 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1761 "MSRIndex": "0x1A6", 1762 "MSRValue": "0x7F03", 1763 "SampleAfterValue": "100000", 1764 "UMask": "0x1" 1765 }, 1766 { 1767 "BriefDescription": "All offcore demand data requests", 1768 "Counter": "2", 1769 "EventCode": "0xB7", 1770 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1771 "MSRIndex": "0x1A6", 1772 "MSRValue": "0xFF03", 1773 "SampleAfterValue": "100000", 1774 "UMask": "0x1" 1775 }, 1776 { 1777 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1778 "Counter": "2", 1779 "EventCode": "0xB7", 1780 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1781 "MSRIndex": "0x1A6", 1782 "MSRValue": "0x8003", 1783 "SampleAfterValue": "100000", 1784 "UMask": "0x1" 1785 }, 1786 { 1787 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1788 "Counter": "2", 1789 "EventCode": "0xB7", 1790 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1791 "MSRIndex": "0x1A6", 1792 "MSRValue": "0x103", 1793 "SampleAfterValue": "100000", 1794 "UMask": "0x1" 1795 }, 1796 { 1797 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1798 "Counter": "2", 1799 "EventCode": "0xB7", 1800 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1801 "MSRIndex": "0x1A6", 1802 "MSRValue": "0x203", 1803 "SampleAfterValue": "100000", 1804 "UMask": "0x1" 1805 }, 1806 { 1807 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1808 "Counter": "2", 1809 "EventCode": "0xB7", 1810 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1811 "MSRIndex": "0x1A6", 1812 "MSRValue": "0x403", 1813 "SampleAfterValue": "100000", 1814 "UMask": "0x1" 1815 }, 1816 { 1817 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1818 "Counter": "2", 1819 "EventCode": "0xB7", 1820 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1821 "MSRIndex": "0x1A6", 1822 "MSRValue": "0x703", 1823 "SampleAfterValue": "100000", 1824 "UMask": "0x1" 1825 }, 1826 { 1827 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1828 "Counter": "2", 1829 "EventCode": "0xB7", 1830 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1831 "MSRIndex": "0x1A6", 1832 "MSRValue": "0x4703", 1833 "SampleAfterValue": "100000", 1834 "UMask": "0x1" 1835 }, 1836 { 1837 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1838 "Counter": "2", 1839 "EventCode": "0xB7", 1840 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1841 "MSRIndex": "0x1A6", 1842 "MSRValue": "0x1803", 1843 "SampleAfterValue": "100000", 1844 "UMask": "0x1" 1845 }, 1846 { 1847 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1848 "Counter": "2", 1849 "EventCode": "0xB7", 1850 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1851 "MSRIndex": "0x1A6", 1852 "MSRValue": "0x3803", 1853 "SampleAfterValue": "100000", 1854 "UMask": "0x1" 1855 }, 1856 { 1857 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1858 "Counter": "2", 1859 "EventCode": "0xB7", 1860 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1861 "MSRIndex": "0x1A6", 1862 "MSRValue": "0x1003", 1863 "SampleAfterValue": "100000", 1864 "UMask": "0x1" 1865 }, 1866 { 1867 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1868 "Counter": "2", 1869 "EventCode": "0xB7", 1870 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1871 "MSRIndex": "0x1A6", 1872 "MSRValue": "0x803", 1873 "SampleAfterValue": "100000", 1874 "UMask": "0x1" 1875 }, 1876 { 1877 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1878 "Counter": "2", 1879 "EventCode": "0xB7", 1880 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1881 "MSRIndex": "0x1A6", 1882 "MSRValue": "0x7F01", 1883 "SampleAfterValue": "100000", 1884 "UMask": "0x1" 1885 }, 1886 { 1887 "BriefDescription": "All offcore demand data reads", 1888 "Counter": "2", 1889 "EventCode": "0xB7", 1890 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1891 "MSRIndex": "0x1A6", 1892 "MSRValue": "0xFF01", 1893 "SampleAfterValue": "100000", 1894 "UMask": "0x1" 1895 }, 1896 { 1897 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1898 "Counter": "2", 1899 "EventCode": "0xB7", 1900 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1901 "MSRIndex": "0x1A6", 1902 "MSRValue": "0x8001", 1903 "SampleAfterValue": "100000", 1904 "UMask": "0x1" 1905 }, 1906 { 1907 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1908 "Counter": "2", 1909 "EventCode": "0xB7", 1910 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1911 "MSRIndex": "0x1A6", 1912 "MSRValue": "0x101", 1913 "SampleAfterValue": "100000", 1914 "UMask": "0x1" 1915 }, 1916 { 1917 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1918 "Counter": "2", 1919 "EventCode": "0xB7", 1920 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1921 "MSRIndex": "0x1A6", 1922 "MSRValue": "0x201", 1923 "SampleAfterValue": "100000", 1924 "UMask": "0x1" 1925 }, 1926 { 1927 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1928 "Counter": "2", 1929 "EventCode": "0xB7", 1930 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1931 "MSRIndex": "0x1A6", 1932 "MSRValue": "0x401", 1933 "SampleAfterValue": "100000", 1934 "UMask": "0x1" 1935 }, 1936 { 1937 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1938 "Counter": "2", 1939 "EventCode": "0xB7", 1940 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1941 "MSRIndex": "0x1A6", 1942 "MSRValue": "0x701", 1943 "SampleAfterValue": "100000", 1944 "UMask": "0x1" 1945 }, 1946 { 1947 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1948 "Counter": "2", 1949 "EventCode": "0xB7", 1950 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1951 "MSRIndex": "0x1A6", 1952 "MSRValue": "0x4701", 1953 "SampleAfterValue": "100000", 1954 "UMask": "0x1" 1955 }, 1956 { 1957 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 1958 "Counter": "2", 1959 "EventCode": "0xB7", 1960 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 1961 "MSRIndex": "0x1A6", 1962 "MSRValue": "0x1801", 1963 "SampleAfterValue": "100000", 1964 "UMask": "0x1" 1965 }, 1966 { 1967 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 1968 "Counter": "2", 1969 "EventCode": "0xB7", 1970 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 1971 "MSRIndex": "0x1A6", 1972 "MSRValue": "0x3801", 1973 "SampleAfterValue": "100000", 1974 "UMask": "0x1" 1975 }, 1976 { 1977 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 1978 "Counter": "2", 1979 "EventCode": "0xB7", 1980 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 1981 "MSRIndex": "0x1A6", 1982 "MSRValue": "0x1001", 1983 "SampleAfterValue": "100000", 1984 "UMask": "0x1" 1985 }, 1986 { 1987 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 1988 "Counter": "2", 1989 "EventCode": "0xB7", 1990 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1991 "MSRIndex": "0x1A6", 1992 "MSRValue": "0x801", 1993 "SampleAfterValue": "100000", 1994 "UMask": "0x1" 1995 }, 1996 { 1997 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 1998 "Counter": "2", 1999 "EventCode": "0xB7", 2000 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2001 "MSRIndex": "0x1A6", 2002 "MSRValue": "0x7F04", 2003 "SampleAfterValue": "100000", 2004 "UMask": "0x1" 2005 }, 2006 { 2007 "BriefDescription": "All offcore demand code reads", 2008 "Counter": "2", 2009 "EventCode": "0xB7", 2010 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2011 "MSRIndex": "0x1A6", 2012 "MSRValue": "0xFF04", 2013 "SampleAfterValue": "100000", 2014 "UMask": "0x1" 2015 }, 2016 { 2017 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2018 "Counter": "2", 2019 "EventCode": "0xB7", 2020 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2021 "MSRIndex": "0x1A6", 2022 "MSRValue": "0x8004", 2023 "SampleAfterValue": "100000", 2024 "UMask": "0x1" 2025 }, 2026 { 2027 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2028 "Counter": "2", 2029 "EventCode": "0xB7", 2030 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2031 "MSRIndex": "0x1A6", 2032 "MSRValue": "0x104", 2033 "SampleAfterValue": "100000", 2034 "UMask": "0x1" 2035 }, 2036 { 2037 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2038 "Counter": "2", 2039 "EventCode": "0xB7", 2040 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2041 "MSRIndex": "0x1A6", 2042 "MSRValue": "0x204", 2043 "SampleAfterValue": "100000", 2044 "UMask": "0x1" 2045 }, 2046 { 2047 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2048 "Counter": "2", 2049 "EventCode": "0xB7", 2050 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2051 "MSRIndex": "0x1A6", 2052 "MSRValue": "0x404", 2053 "SampleAfterValue": "100000", 2054 "UMask": "0x1" 2055 }, 2056 { 2057 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2058 "Counter": "2", 2059 "EventCode": "0xB7", 2060 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2061 "MSRIndex": "0x1A6", 2062 "MSRValue": "0x704", 2063 "SampleAfterValue": "100000", 2064 "UMask": "0x1" 2065 }, 2066 { 2067 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2068 "Counter": "2", 2069 "EventCode": "0xB7", 2070 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2071 "MSRIndex": "0x1A6", 2072 "MSRValue": "0x4704", 2073 "SampleAfterValue": "100000", 2074 "UMask": "0x1" 2075 }, 2076 { 2077 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2078 "Counter": "2", 2079 "EventCode": "0xB7", 2080 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2081 "MSRIndex": "0x1A6", 2082 "MSRValue": "0x1804", 2083 "SampleAfterValue": "100000", 2084 "UMask": "0x1" 2085 }, 2086 { 2087 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2088 "Counter": "2", 2089 "EventCode": "0xB7", 2090 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2091 "MSRIndex": "0x1A6", 2092 "MSRValue": "0x3804", 2093 "SampleAfterValue": "100000", 2094 "UMask": "0x1" 2095 }, 2096 { 2097 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2098 "Counter": "2", 2099 "EventCode": "0xB7", 2100 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2101 "MSRIndex": "0x1A6", 2102 "MSRValue": "0x1004", 2103 "SampleAfterValue": "100000", 2104 "UMask": "0x1" 2105 }, 2106 { 2107 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2108 "Counter": "2", 2109 "EventCode": "0xB7", 2110 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2111 "MSRIndex": "0x1A6", 2112 "MSRValue": "0x804", 2113 "SampleAfterValue": "100000", 2114 "UMask": "0x1" 2115 }, 2116 { 2117 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2118 "Counter": "2", 2119 "EventCode": "0xB7", 2120 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2121 "MSRIndex": "0x1A6", 2122 "MSRValue": "0x7F02", 2123 "SampleAfterValue": "100000", 2124 "UMask": "0x1" 2125 }, 2126 { 2127 "BriefDescription": "All offcore demand RFO requests", 2128 "Counter": "2", 2129 "EventCode": "0xB7", 2130 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2131 "MSRIndex": "0x1A6", 2132 "MSRValue": "0xFF02", 2133 "SampleAfterValue": "100000", 2134 "UMask": "0x1" 2135 }, 2136 { 2137 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2138 "Counter": "2", 2139 "EventCode": "0xB7", 2140 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2141 "MSRIndex": "0x1A6", 2142 "MSRValue": "0x8002", 2143 "SampleAfterValue": "100000", 2144 "UMask": "0x1" 2145 }, 2146 { 2147 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2148 "Counter": "2", 2149 "EventCode": "0xB7", 2150 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2151 "MSRIndex": "0x1A6", 2152 "MSRValue": "0x102", 2153 "SampleAfterValue": "100000", 2154 "UMask": "0x1" 2155 }, 2156 { 2157 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2158 "Counter": "2", 2159 "EventCode": "0xB7", 2160 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2161 "MSRIndex": "0x1A6", 2162 "MSRValue": "0x202", 2163 "SampleAfterValue": "100000", 2164 "UMask": "0x1" 2165 }, 2166 { 2167 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2168 "Counter": "2", 2169 "EventCode": "0xB7", 2170 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2171 "MSRIndex": "0x1A6", 2172 "MSRValue": "0x402", 2173 "SampleAfterValue": "100000", 2174 "UMask": "0x1" 2175 }, 2176 { 2177 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2178 "Counter": "2", 2179 "EventCode": "0xB7", 2180 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2181 "MSRIndex": "0x1A6", 2182 "MSRValue": "0x702", 2183 "SampleAfterValue": "100000", 2184 "UMask": "0x1" 2185 }, 2186 { 2187 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2188 "Counter": "2", 2189 "EventCode": "0xB7", 2190 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2191 "MSRIndex": "0x1A6", 2192 "MSRValue": "0x4702", 2193 "SampleAfterValue": "100000", 2194 "UMask": "0x1" 2195 }, 2196 { 2197 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2198 "Counter": "2", 2199 "EventCode": "0xB7", 2200 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2201 "MSRIndex": "0x1A6", 2202 "MSRValue": "0x1802", 2203 "SampleAfterValue": "100000", 2204 "UMask": "0x1" 2205 }, 2206 { 2207 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2208 "Counter": "2", 2209 "EventCode": "0xB7", 2210 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2211 "MSRIndex": "0x1A6", 2212 "MSRValue": "0x3802", 2213 "SampleAfterValue": "100000", 2214 "UMask": "0x1" 2215 }, 2216 { 2217 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2218 "Counter": "2", 2219 "EventCode": "0xB7", 2220 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2221 "MSRIndex": "0x1A6", 2222 "MSRValue": "0x1002", 2223 "SampleAfterValue": "100000", 2224 "UMask": "0x1" 2225 }, 2226 { 2227 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2228 "Counter": "2", 2229 "EventCode": "0xB7", 2230 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2231 "MSRIndex": "0x1A6", 2232 "MSRValue": "0x802", 2233 "SampleAfterValue": "100000", 2234 "UMask": "0x1" 2235 }, 2236 { 2237 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2238 "Counter": "2", 2239 "EventCode": "0xB7", 2240 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2241 "MSRIndex": "0x1A6", 2242 "MSRValue": "0x7F80", 2243 "SampleAfterValue": "100000", 2244 "UMask": "0x1" 2245 }, 2246 { 2247 "BriefDescription": "All offcore other requests", 2248 "Counter": "2", 2249 "EventCode": "0xB7", 2250 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2251 "MSRIndex": "0x1A6", 2252 "MSRValue": "0xFF80", 2253 "SampleAfterValue": "100000", 2254 "UMask": "0x1" 2255 }, 2256 { 2257 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2258 "Counter": "2", 2259 "EventCode": "0xB7", 2260 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2261 "MSRIndex": "0x1A6", 2262 "MSRValue": "0x8080", 2263 "SampleAfterValue": "100000", 2264 "UMask": "0x1" 2265 }, 2266 { 2267 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2268 "Counter": "2", 2269 "EventCode": "0xB7", 2270 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2271 "MSRIndex": "0x1A6", 2272 "MSRValue": "0x180", 2273 "SampleAfterValue": "100000", 2274 "UMask": "0x1" 2275 }, 2276 { 2277 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2278 "Counter": "2", 2279 "EventCode": "0xB7", 2280 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2281 "MSRIndex": "0x1A6", 2282 "MSRValue": "0x280", 2283 "SampleAfterValue": "100000", 2284 "UMask": "0x1" 2285 }, 2286 { 2287 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2288 "Counter": "2", 2289 "EventCode": "0xB7", 2290 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2291 "MSRIndex": "0x1A6", 2292 "MSRValue": "0x480", 2293 "SampleAfterValue": "100000", 2294 "UMask": "0x1" 2295 }, 2296 { 2297 "BriefDescription": "Offcore other requests satisfied by the LLC", 2298 "Counter": "2", 2299 "EventCode": "0xB7", 2300 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2301 "MSRIndex": "0x1A6", 2302 "MSRValue": "0x780", 2303 "SampleAfterValue": "100000", 2304 "UMask": "0x1" 2305 }, 2306 { 2307 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2308 "Counter": "2", 2309 "EventCode": "0xB7", 2310 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2311 "MSRIndex": "0x1A6", 2312 "MSRValue": "0x4780", 2313 "SampleAfterValue": "100000", 2314 "UMask": "0x1" 2315 }, 2316 { 2317 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2318 "Counter": "2", 2319 "EventCode": "0xB7", 2320 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2321 "MSRIndex": "0x1A6", 2322 "MSRValue": "0x1880", 2323 "SampleAfterValue": "100000", 2324 "UMask": "0x1" 2325 }, 2326 { 2327 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2328 "Counter": "2", 2329 "EventCode": "0xB7", 2330 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2331 "MSRIndex": "0x1A6", 2332 "MSRValue": "0x3880", 2333 "SampleAfterValue": "100000", 2334 "UMask": "0x1" 2335 }, 2336 { 2337 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2338 "Counter": "2", 2339 "EventCode": "0xB7", 2340 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2341 "MSRIndex": "0x1A6", 2342 "MSRValue": "0x1080", 2343 "SampleAfterValue": "100000", 2344 "UMask": "0x1" 2345 }, 2346 { 2347 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2348 "Counter": "2", 2349 "EventCode": "0xB7", 2350 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2351 "MSRIndex": "0x1A6", 2352 "MSRValue": "0x880", 2353 "SampleAfterValue": "100000", 2354 "UMask": "0x1" 2355 }, 2356 { 2357 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2358 "Counter": "2", 2359 "EventCode": "0xB7", 2360 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2361 "MSRIndex": "0x1A6", 2362 "MSRValue": "0x7F30", 2363 "SampleAfterValue": "100000", 2364 "UMask": "0x1" 2365 }, 2366 { 2367 "BriefDescription": "All offcore prefetch data requests", 2368 "Counter": "2", 2369 "EventCode": "0xB7", 2370 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2371 "MSRIndex": "0x1A6", 2372 "MSRValue": "0xFF30", 2373 "SampleAfterValue": "100000", 2374 "UMask": "0x1" 2375 }, 2376 { 2377 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2378 "Counter": "2", 2379 "EventCode": "0xB7", 2380 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2381 "MSRIndex": "0x1A6", 2382 "MSRValue": "0x8030", 2383 "SampleAfterValue": "100000", 2384 "UMask": "0x1" 2385 }, 2386 { 2387 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2388 "Counter": "2", 2389 "EventCode": "0xB7", 2390 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2391 "MSRIndex": "0x1A6", 2392 "MSRValue": "0x130", 2393 "SampleAfterValue": "100000", 2394 "UMask": "0x1" 2395 }, 2396 { 2397 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2398 "Counter": "2", 2399 "EventCode": "0xB7", 2400 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2401 "MSRIndex": "0x1A6", 2402 "MSRValue": "0x230", 2403 "SampleAfterValue": "100000", 2404 "UMask": "0x1" 2405 }, 2406 { 2407 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2408 "Counter": "2", 2409 "EventCode": "0xB7", 2410 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2411 "MSRIndex": "0x1A6", 2412 "MSRValue": "0x430", 2413 "SampleAfterValue": "100000", 2414 "UMask": "0x1" 2415 }, 2416 { 2417 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2418 "Counter": "2", 2419 "EventCode": "0xB7", 2420 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2421 "MSRIndex": "0x1A6", 2422 "MSRValue": "0x730", 2423 "SampleAfterValue": "100000", 2424 "UMask": "0x1" 2425 }, 2426 { 2427 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2428 "Counter": "2", 2429 "EventCode": "0xB7", 2430 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2431 "MSRIndex": "0x1A6", 2432 "MSRValue": "0x4730", 2433 "SampleAfterValue": "100000", 2434 "UMask": "0x1" 2435 }, 2436 { 2437 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2438 "Counter": "2", 2439 "EventCode": "0xB7", 2440 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2441 "MSRIndex": "0x1A6", 2442 "MSRValue": "0x1830", 2443 "SampleAfterValue": "100000", 2444 "UMask": "0x1" 2445 }, 2446 { 2447 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2448 "Counter": "2", 2449 "EventCode": "0xB7", 2450 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2451 "MSRIndex": "0x1A6", 2452 "MSRValue": "0x3830", 2453 "SampleAfterValue": "100000", 2454 "UMask": "0x1" 2455 }, 2456 { 2457 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2458 "Counter": "2", 2459 "EventCode": "0xB7", 2460 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2461 "MSRIndex": "0x1A6", 2462 "MSRValue": "0x1030", 2463 "SampleAfterValue": "100000", 2464 "UMask": "0x1" 2465 }, 2466 { 2467 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2468 "Counter": "2", 2469 "EventCode": "0xB7", 2470 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2471 "MSRIndex": "0x1A6", 2472 "MSRValue": "0x830", 2473 "SampleAfterValue": "100000", 2474 "UMask": "0x1" 2475 }, 2476 { 2477 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2478 "Counter": "2", 2479 "EventCode": "0xB7", 2480 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2481 "MSRIndex": "0x1A6", 2482 "MSRValue": "0x7F10", 2483 "SampleAfterValue": "100000", 2484 "UMask": "0x1" 2485 }, 2486 { 2487 "BriefDescription": "All offcore prefetch data reads", 2488 "Counter": "2", 2489 "EventCode": "0xB7", 2490 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2491 "MSRIndex": "0x1A6", 2492 "MSRValue": "0xFF10", 2493 "SampleAfterValue": "100000", 2494 "UMask": "0x1" 2495 }, 2496 { 2497 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2498 "Counter": "2", 2499 "EventCode": "0xB7", 2500 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2501 "MSRIndex": "0x1A6", 2502 "MSRValue": "0x8010", 2503 "SampleAfterValue": "100000", 2504 "UMask": "0x1" 2505 }, 2506 { 2507 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2508 "Counter": "2", 2509 "EventCode": "0xB7", 2510 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2511 "MSRIndex": "0x1A6", 2512 "MSRValue": "0x110", 2513 "SampleAfterValue": "100000", 2514 "UMask": "0x1" 2515 }, 2516 { 2517 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2518 "Counter": "2", 2519 "EventCode": "0xB7", 2520 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2521 "MSRIndex": "0x1A6", 2522 "MSRValue": "0x210", 2523 "SampleAfterValue": "100000", 2524 "UMask": "0x1" 2525 }, 2526 { 2527 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2528 "Counter": "2", 2529 "EventCode": "0xB7", 2530 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2531 "MSRIndex": "0x1A6", 2532 "MSRValue": "0x410", 2533 "SampleAfterValue": "100000", 2534 "UMask": "0x1" 2535 }, 2536 { 2537 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2538 "Counter": "2", 2539 "EventCode": "0xB7", 2540 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2541 "MSRIndex": "0x1A6", 2542 "MSRValue": "0x710", 2543 "SampleAfterValue": "100000", 2544 "UMask": "0x1" 2545 }, 2546 { 2547 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2548 "Counter": "2", 2549 "EventCode": "0xB7", 2550 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2551 "MSRIndex": "0x1A6", 2552 "MSRValue": "0x4710", 2553 "SampleAfterValue": "100000", 2554 "UMask": "0x1" 2555 }, 2556 { 2557 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2558 "Counter": "2", 2559 "EventCode": "0xB7", 2560 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2561 "MSRIndex": "0x1A6", 2562 "MSRValue": "0x1810", 2563 "SampleAfterValue": "100000", 2564 "UMask": "0x1" 2565 }, 2566 { 2567 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2568 "Counter": "2", 2569 "EventCode": "0xB7", 2570 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2571 "MSRIndex": "0x1A6", 2572 "MSRValue": "0x3810", 2573 "SampleAfterValue": "100000", 2574 "UMask": "0x1" 2575 }, 2576 { 2577 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2578 "Counter": "2", 2579 "EventCode": "0xB7", 2580 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2581 "MSRIndex": "0x1A6", 2582 "MSRValue": "0x1010", 2583 "SampleAfterValue": "100000", 2584 "UMask": "0x1" 2585 }, 2586 { 2587 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2588 "Counter": "2", 2589 "EventCode": "0xB7", 2590 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2591 "MSRIndex": "0x1A6", 2592 "MSRValue": "0x810", 2593 "SampleAfterValue": "100000", 2594 "UMask": "0x1" 2595 }, 2596 { 2597 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2598 "Counter": "2", 2599 "EventCode": "0xB7", 2600 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2601 "MSRIndex": "0x1A6", 2602 "MSRValue": "0x7F40", 2603 "SampleAfterValue": "100000", 2604 "UMask": "0x1" 2605 }, 2606 { 2607 "BriefDescription": "All offcore prefetch code reads", 2608 "Counter": "2", 2609 "EventCode": "0xB7", 2610 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2611 "MSRIndex": "0x1A6", 2612 "MSRValue": "0xFF40", 2613 "SampleAfterValue": "100000", 2614 "UMask": "0x1" 2615 }, 2616 { 2617 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2618 "Counter": "2", 2619 "EventCode": "0xB7", 2620 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2621 "MSRIndex": "0x1A6", 2622 "MSRValue": "0x8040", 2623 "SampleAfterValue": "100000", 2624 "UMask": "0x1" 2625 }, 2626 { 2627 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2628 "Counter": "2", 2629 "EventCode": "0xB7", 2630 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2631 "MSRIndex": "0x1A6", 2632 "MSRValue": "0x140", 2633 "SampleAfterValue": "100000", 2634 "UMask": "0x1" 2635 }, 2636 { 2637 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2638 "Counter": "2", 2639 "EventCode": "0xB7", 2640 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2641 "MSRIndex": "0x1A6", 2642 "MSRValue": "0x240", 2643 "SampleAfterValue": "100000", 2644 "UMask": "0x1" 2645 }, 2646 { 2647 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2648 "Counter": "2", 2649 "EventCode": "0xB7", 2650 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2651 "MSRIndex": "0x1A6", 2652 "MSRValue": "0x440", 2653 "SampleAfterValue": "100000", 2654 "UMask": "0x1" 2655 }, 2656 { 2657 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2658 "Counter": "2", 2659 "EventCode": "0xB7", 2660 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2661 "MSRIndex": "0x1A6", 2662 "MSRValue": "0x740", 2663 "SampleAfterValue": "100000", 2664 "UMask": "0x1" 2665 }, 2666 { 2667 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2668 "Counter": "2", 2669 "EventCode": "0xB7", 2670 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2671 "MSRIndex": "0x1A6", 2672 "MSRValue": "0x4740", 2673 "SampleAfterValue": "100000", 2674 "UMask": "0x1" 2675 }, 2676 { 2677 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2678 "Counter": "2", 2679 "EventCode": "0xB7", 2680 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2681 "MSRIndex": "0x1A6", 2682 "MSRValue": "0x1840", 2683 "SampleAfterValue": "100000", 2684 "UMask": "0x1" 2685 }, 2686 { 2687 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2688 "Counter": "2", 2689 "EventCode": "0xB7", 2690 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2691 "MSRIndex": "0x1A6", 2692 "MSRValue": "0x3840", 2693 "SampleAfterValue": "100000", 2694 "UMask": "0x1" 2695 }, 2696 { 2697 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2698 "Counter": "2", 2699 "EventCode": "0xB7", 2700 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2701 "MSRIndex": "0x1A6", 2702 "MSRValue": "0x1040", 2703 "SampleAfterValue": "100000", 2704 "UMask": "0x1" 2705 }, 2706 { 2707 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2708 "Counter": "2", 2709 "EventCode": "0xB7", 2710 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2711 "MSRIndex": "0x1A6", 2712 "MSRValue": "0x840", 2713 "SampleAfterValue": "100000", 2714 "UMask": "0x1" 2715 }, 2716 { 2717 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2718 "Counter": "2", 2719 "EventCode": "0xB7", 2720 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2721 "MSRIndex": "0x1A6", 2722 "MSRValue": "0x7F20", 2723 "SampleAfterValue": "100000", 2724 "UMask": "0x1" 2725 }, 2726 { 2727 "BriefDescription": "All offcore prefetch RFO requests", 2728 "Counter": "2", 2729 "EventCode": "0xB7", 2730 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2731 "MSRIndex": "0x1A6", 2732 "MSRValue": "0xFF20", 2733 "SampleAfterValue": "100000", 2734 "UMask": "0x1" 2735 }, 2736 { 2737 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2738 "Counter": "2", 2739 "EventCode": "0xB7", 2740 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2741 "MSRIndex": "0x1A6", 2742 "MSRValue": "0x8020", 2743 "SampleAfterValue": "100000", 2744 "UMask": "0x1" 2745 }, 2746 { 2747 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2748 "Counter": "2", 2749 "EventCode": "0xB7", 2750 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2751 "MSRIndex": "0x1A6", 2752 "MSRValue": "0x120", 2753 "SampleAfterValue": "100000", 2754 "UMask": "0x1" 2755 }, 2756 { 2757 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2758 "Counter": "2", 2759 "EventCode": "0xB7", 2760 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2761 "MSRIndex": "0x1A6", 2762 "MSRValue": "0x220", 2763 "SampleAfterValue": "100000", 2764 "UMask": "0x1" 2765 }, 2766 { 2767 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2768 "Counter": "2", 2769 "EventCode": "0xB7", 2770 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2771 "MSRIndex": "0x1A6", 2772 "MSRValue": "0x420", 2773 "SampleAfterValue": "100000", 2774 "UMask": "0x1" 2775 }, 2776 { 2777 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2778 "Counter": "2", 2779 "EventCode": "0xB7", 2780 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2781 "MSRIndex": "0x1A6", 2782 "MSRValue": "0x720", 2783 "SampleAfterValue": "100000", 2784 "UMask": "0x1" 2785 }, 2786 { 2787 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2788 "Counter": "2", 2789 "EventCode": "0xB7", 2790 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2791 "MSRIndex": "0x1A6", 2792 "MSRValue": "0x4720", 2793 "SampleAfterValue": "100000", 2794 "UMask": "0x1" 2795 }, 2796 { 2797 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2798 "Counter": "2", 2799 "EventCode": "0xB7", 2800 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2801 "MSRIndex": "0x1A6", 2802 "MSRValue": "0x1820", 2803 "SampleAfterValue": "100000", 2804 "UMask": "0x1" 2805 }, 2806 { 2807 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2808 "Counter": "2", 2809 "EventCode": "0xB7", 2810 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2811 "MSRIndex": "0x1A6", 2812 "MSRValue": "0x3820", 2813 "SampleAfterValue": "100000", 2814 "UMask": "0x1" 2815 }, 2816 { 2817 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2818 "Counter": "2", 2819 "EventCode": "0xB7", 2820 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2821 "MSRIndex": "0x1A6", 2822 "MSRValue": "0x1020", 2823 "SampleAfterValue": "100000", 2824 "UMask": "0x1" 2825 }, 2826 { 2827 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2828 "Counter": "2", 2829 "EventCode": "0xB7", 2830 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2831 "MSRIndex": "0x1A6", 2832 "MSRValue": "0x820", 2833 "SampleAfterValue": "100000", 2834 "UMask": "0x1" 2835 }, 2836 { 2837 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2838 "Counter": "2", 2839 "EventCode": "0xB7", 2840 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2841 "MSRIndex": "0x1A6", 2842 "MSRValue": "0x7F70", 2843 "SampleAfterValue": "100000", 2844 "UMask": "0x1" 2845 }, 2846 { 2847 "BriefDescription": "All offcore prefetch requests", 2848 "Counter": "2", 2849 "EventCode": "0xB7", 2850 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2851 "MSRIndex": "0x1A6", 2852 "MSRValue": "0xFF70", 2853 "SampleAfterValue": "100000", 2854 "UMask": "0x1" 2855 }, 2856 { 2857 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2858 "Counter": "2", 2859 "EventCode": "0xB7", 2860 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2861 "MSRIndex": "0x1A6", 2862 "MSRValue": "0x8070", 2863 "SampleAfterValue": "100000", 2864 "UMask": "0x1" 2865 }, 2866 { 2867 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2868 "Counter": "2", 2869 "EventCode": "0xB7", 2870 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2871 "MSRIndex": "0x1A6", 2872 "MSRValue": "0x170", 2873 "SampleAfterValue": "100000", 2874 "UMask": "0x1" 2875 }, 2876 { 2877 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2878 "Counter": "2", 2879 "EventCode": "0xB7", 2880 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2881 "MSRIndex": "0x1A6", 2882 "MSRValue": "0x270", 2883 "SampleAfterValue": "100000", 2884 "UMask": "0x1" 2885 }, 2886 { 2887 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2888 "Counter": "2", 2889 "EventCode": "0xB7", 2890 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2891 "MSRIndex": "0x1A6", 2892 "MSRValue": "0x470", 2893 "SampleAfterValue": "100000", 2894 "UMask": "0x1" 2895 }, 2896 { 2897 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2898 "Counter": "2", 2899 "EventCode": "0xB7", 2900 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2901 "MSRIndex": "0x1A6", 2902 "MSRValue": "0x770", 2903 "SampleAfterValue": "100000", 2904 "UMask": "0x1" 2905 }, 2906 { 2907 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2908 "Counter": "2", 2909 "EventCode": "0xB7", 2910 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2911 "MSRIndex": "0x1A6", 2912 "MSRValue": "0x4770", 2913 "SampleAfterValue": "100000", 2914 "UMask": "0x1" 2915 }, 2916 { 2917 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2918 "Counter": "2", 2919 "EventCode": "0xB7", 2920 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2921 "MSRIndex": "0x1A6", 2922 "MSRValue": "0x1870", 2923 "SampleAfterValue": "100000", 2924 "UMask": "0x1" 2925 }, 2926 { 2927 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2928 "Counter": "2", 2929 "EventCode": "0xB7", 2930 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2931 "MSRIndex": "0x1A6", 2932 "MSRValue": "0x3870", 2933 "SampleAfterValue": "100000", 2934 "UMask": "0x1" 2935 }, 2936 { 2937 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2938 "Counter": "2", 2939 "EventCode": "0xB7", 2940 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2941 "MSRIndex": "0x1A6", 2942 "MSRValue": "0x1070", 2943 "SampleAfterValue": "100000", 2944 "UMask": "0x1" 2945 }, 2946 { 2947 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2948 "Counter": "2", 2949 "EventCode": "0xB7", 2950 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2951 "MSRIndex": "0x1A6", 2952 "MSRValue": "0x870", 2953 "SampleAfterValue": "100000", 2954 "UMask": "0x1" 2955 }, 2956 { 2957 "BriefDescription": "Super Queue lock splits across a cache line", 2958 "Counter": "0,1,2,3", 2959 "EventCode": "0xF4", 2960 "EventName": "SQ_MISC.SPLIT_LOCK", 2961 "SampleAfterValue": "2000000", 2962 "UMask": "0x10" 2963 }, 2964 { 2965 "BriefDescription": "Loads delayed with at-Retirement block code", 2966 "Counter": "0,1,2,3", 2967 "EventCode": "0x6", 2968 "EventName": "STORE_BLOCKS.AT_RET", 2969 "SampleAfterValue": "200000", 2970 "UMask": "0x4" 2971 }, 2972 { 2973 "BriefDescription": "Cacheable loads delayed with L1D block code", 2974 "Counter": "0,1,2,3", 2975 "EventCode": "0x6", 2976 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2977 "SampleAfterValue": "200000", 2978 "UMask": "0x8" 2979 } 2980] 2981