xref: /linux/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json (revision 34f7c6e7d4396090692a09789db231e12cb4762b) 
1[
2    {
3        "BriefDescription": "Cycles the divider is busy",
4        "Counter": "0,1,2,3",
5        "EventCode": "0x14",
6        "EventName": "ARITH.CYCLES_DIV_BUSY",
7        "SampleAfterValue": "2000000",
8        "UMask": "0x1"
9    },
10    {
11        "BriefDescription": "Divide Operations executed",
12        "Counter": "0,1,2,3",
13        "CounterMask": "1",
14        "EdgeDetect": "1",
15        "EventCode": "0x14",
16        "EventName": "ARITH.DIV",
17        "Invert": "1",
18        "SampleAfterValue": "2000000",
19        "UMask": "0x1"
20    },
21    {
22        "BriefDescription": "Multiply operations executed",
23        "Counter": "0,1,2,3",
24        "EventCode": "0x14",
25        "EventName": "ARITH.MUL",
26        "SampleAfterValue": "2000000",
27        "UMask": "0x2"
28    },
29    {
30        "BriefDescription": "BACLEAR asserted with bad target address",
31        "Counter": "0,1,2,3",
32        "EventCode": "0xE6",
33        "EventName": "BACLEAR.BAD_TARGET",
34        "SampleAfterValue": "2000000",
35        "UMask": "0x2"
36    },
37    {
38        "BriefDescription": "BACLEAR asserted, regardless of cause",
39        "Counter": "0,1,2,3",
40        "EventCode": "0xE6",
41        "EventName": "BACLEAR.CLEAR",
42        "SampleAfterValue": "2000000",
43        "UMask": "0x1"
44    },
45    {
46        "BriefDescription": "Instruction queue forced BACLEAR",
47        "Counter": "0,1,2,3",
48        "EventCode": "0xA7",
49        "EventName": "BACLEAR_FORCE_IQ",
50        "SampleAfterValue": "2000000",
51        "UMask": "0x1"
52    },
53    {
54        "BriefDescription": "Branch instructions decoded",
55        "Counter": "0,1,2,3",
56        "EventCode": "0xE0",
57        "EventName": "BR_INST_DECODED",
58        "SampleAfterValue": "2000000",
59        "UMask": "0x1"
60    },
61    {
62        "BriefDescription": "Branch instructions executed",
63        "Counter": "0,1,2,3",
64        "EventCode": "0x88",
65        "EventName": "BR_INST_EXEC.ANY",
66        "SampleAfterValue": "200000",
67        "UMask": "0x7f"
68    },
69    {
70        "BriefDescription": "Conditional branch instructions executed",
71        "Counter": "0,1,2,3",
72        "EventCode": "0x88",
73        "EventName": "BR_INST_EXEC.COND",
74        "SampleAfterValue": "200000",
75        "UMask": "0x1"
76    },
77    {
78        "BriefDescription": "Unconditional branches executed",
79        "Counter": "0,1,2,3",
80        "EventCode": "0x88",
81        "EventName": "BR_INST_EXEC.DIRECT",
82        "SampleAfterValue": "200000",
83        "UMask": "0x2"
84    },
85    {
86        "BriefDescription": "Unconditional call branches executed",
87        "Counter": "0,1,2,3",
88        "EventCode": "0x88",
89        "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
90        "SampleAfterValue": "20000",
91        "UMask": "0x10"
92    },
93    {
94        "BriefDescription": "Indirect call branches executed",
95        "Counter": "0,1,2,3",
96        "EventCode": "0x88",
97        "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
98        "SampleAfterValue": "20000",
99        "UMask": "0x20"
100    },
101    {
102        "BriefDescription": "Indirect non call branches executed",
103        "Counter": "0,1,2,3",
104        "EventCode": "0x88",
105        "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
106        "SampleAfterValue": "20000",
107        "UMask": "0x4"
108    },
109    {
110        "BriefDescription": "Call branches executed",
111        "Counter": "0,1,2,3",
112        "EventCode": "0x88",
113        "EventName": "BR_INST_EXEC.NEAR_CALLS",
114        "SampleAfterValue": "20000",
115        "UMask": "0x30"
116    },
117    {
118        "BriefDescription": "All non call branches executed",
119        "Counter": "0,1,2,3",
120        "EventCode": "0x88",
121        "EventName": "BR_INST_EXEC.NON_CALLS",
122        "SampleAfterValue": "200000",
123        "UMask": "0x7"
124    },
125    {
126        "BriefDescription": "Indirect return branches executed",
127        "Counter": "0,1,2,3",
128        "EventCode": "0x88",
129        "EventName": "BR_INST_EXEC.RETURN_NEAR",
130        "SampleAfterValue": "20000",
131        "UMask": "0x8"
132    },
133    {
134        "BriefDescription": "Taken branches executed",
135        "Counter": "0,1,2,3",
136        "EventCode": "0x88",
137        "EventName": "BR_INST_EXEC.TAKEN",
138        "SampleAfterValue": "200000",
139        "UMask": "0x40"
140    },
141    {
142        "BriefDescription": "Retired branch instructions (Precise Event)",
143        "Counter": "0,1,2,3",
144        "EventCode": "0xC4",
145        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
146        "PEBS": "1",
147        "SampleAfterValue": "200000",
148        "UMask": "0x4"
149    },
150    {
151        "BriefDescription": "Retired conditional branch instructions (Precise Event)",
152        "Counter": "0,1,2,3",
153        "EventCode": "0xC4",
154        "EventName": "BR_INST_RETIRED.CONDITIONAL",
155        "PEBS": "1",
156        "SampleAfterValue": "200000",
157        "UMask": "0x1"
158    },
159    {
160        "BriefDescription": "Retired near call instructions (Precise Event)",
161        "Counter": "0,1,2,3",
162        "EventCode": "0xC4",
163        "EventName": "BR_INST_RETIRED.NEAR_CALL",
164        "PEBS": "1",
165        "SampleAfterValue": "20000",
166        "UMask": "0x2"
167    },
168    {
169        "BriefDescription": "Mispredicted branches executed",
170        "Counter": "0,1,2,3",
171        "EventCode": "0x89",
172        "EventName": "BR_MISP_EXEC.ANY",
173        "SampleAfterValue": "20000",
174        "UMask": "0x7f"
175    },
176    {
177        "BriefDescription": "Mispredicted conditional branches executed",
178        "Counter": "0,1,2,3",
179        "EventCode": "0x89",
180        "EventName": "BR_MISP_EXEC.COND",
181        "SampleAfterValue": "20000",
182        "UMask": "0x1"
183    },
184    {
185        "BriefDescription": "Mispredicted unconditional branches executed",
186        "Counter": "0,1,2,3",
187        "EventCode": "0x89",
188        "EventName": "BR_MISP_EXEC.DIRECT",
189        "SampleAfterValue": "20000",
190        "UMask": "0x2"
191    },
192    {
193        "BriefDescription": "Mispredicted non call branches executed",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x89",
196        "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
197        "SampleAfterValue": "2000",
198        "UMask": "0x10"
199    },
200    {
201        "BriefDescription": "Mispredicted indirect call branches executed",
202        "Counter": "0,1,2,3",
203        "EventCode": "0x89",
204        "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
205        "SampleAfterValue": "2000",
206        "UMask": "0x20"
207    },
208    {
209        "BriefDescription": "Mispredicted indirect non call branches executed",
210        "Counter": "0,1,2,3",
211        "EventCode": "0x89",
212        "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
213        "SampleAfterValue": "2000",
214        "UMask": "0x4"
215    },
216    {
217        "BriefDescription": "Mispredicted call branches executed",
218        "Counter": "0,1,2,3",
219        "EventCode": "0x89",
220        "EventName": "BR_MISP_EXEC.NEAR_CALLS",
221        "SampleAfterValue": "2000",
222        "UMask": "0x30"
223    },
224    {
225        "BriefDescription": "Mispredicted non call branches executed",
226        "Counter": "0,1,2,3",
227        "EventCode": "0x89",
228        "EventName": "BR_MISP_EXEC.NON_CALLS",
229        "SampleAfterValue": "20000",
230        "UMask": "0x7"
231    },
232    {
233        "BriefDescription": "Mispredicted return branches executed",
234        "Counter": "0,1,2,3",
235        "EventCode": "0x89",
236        "EventName": "BR_MISP_EXEC.RETURN_NEAR",
237        "SampleAfterValue": "2000",
238        "UMask": "0x8"
239    },
240    {
241        "BriefDescription": "Mispredicted taken branches executed",
242        "Counter": "0,1,2,3",
243        "EventCode": "0x89",
244        "EventName": "BR_MISP_EXEC.TAKEN",
245        "SampleAfterValue": "20000",
246        "UMask": "0x40"
247    },
248    {
249        "BriefDescription": "Mispredicted near retired calls (Precise Event)",
250        "Counter": "0,1,2,3",
251        "EventCode": "0xC5",
252        "EventName": "BR_MISP_RETIRED.NEAR_CALL",
253        "PEBS": "1",
254        "SampleAfterValue": "2000",
255        "UMask": "0x2"
256    },
257    {
258        "BriefDescription": "Reference cycles when thread is not halted (fixed counter)",
259        "Counter": "Fixed counter 3",
260        "EventCode": "0x0",
261        "EventName": "CPU_CLK_UNHALTED.REF",
262        "SampleAfterValue": "2000000",
263        "UMask": "0x0"
264    },
265    {
266        "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)",
267        "Counter": "0,1,2,3",
268        "EventCode": "0x3C",
269        "EventName": "CPU_CLK_UNHALTED.REF_P",
270        "SampleAfterValue": "100000",
271        "UMask": "0x1"
272    },
273    {
274        "BriefDescription": "Cycles when thread is not halted (fixed counter)",
275        "Counter": "Fixed counter 2",
276        "EventCode": "0x0",
277        "EventName": "CPU_CLK_UNHALTED.THREAD",
278        "SampleAfterValue": "2000000",
279        "UMask": "0x0"
280    },
281    {
282        "BriefDescription": "Cycles when thread is not halted (programmable counter)",
283        "Counter": "0,1,2,3",
284        "EventCode": "0x3C",
285        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
286        "SampleAfterValue": "2000000",
287        "UMask": "0x0"
288    },
289    {
290        "BriefDescription": "Total CPU cycles",
291        "Counter": "0,1,2,3",
292        "CounterMask": "2",
293        "EventCode": "0x3C",
294        "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
295        "Invert": "1",
296        "SampleAfterValue": "2000000",
297        "UMask": "0x0"
298    },
299    {
300        "BriefDescription": "Any Instruction Length Decoder stall cycles",
301        "Counter": "0,1,2,3",
302        "EventCode": "0x87",
303        "EventName": "ILD_STALL.ANY",
304        "SampleAfterValue": "2000000",
305        "UMask": "0xf"
306    },
307    {
308        "BriefDescription": "Instruction Queue full stall cycles",
309        "Counter": "0,1,2,3",
310        "EventCode": "0x87",
311        "EventName": "ILD_STALL.IQ_FULL",
312        "SampleAfterValue": "2000000",
313        "UMask": "0x4"
314    },
315    {
316        "BriefDescription": "Length Change Prefix stall cycles",
317        "Counter": "0,1,2,3",
318        "EventCode": "0x87",
319        "EventName": "ILD_STALL.LCP",
320        "SampleAfterValue": "2000000",
321        "UMask": "0x1"
322    },
323    {
324        "BriefDescription": "Stall cycles due to BPU MRU bypass",
325        "Counter": "0,1,2,3",
326        "EventCode": "0x87",
327        "EventName": "ILD_STALL.MRU",
328        "SampleAfterValue": "2000000",
329        "UMask": "0x2"
330    },
331    {
332        "BriefDescription": "Regen stall cycles",
333        "Counter": "0,1,2,3",
334        "EventCode": "0x87",
335        "EventName": "ILD_STALL.REGEN",
336        "SampleAfterValue": "2000000",
337        "UMask": "0x8"
338    },
339    {
340        "BriefDescription": "Instructions that must be decoded by decoder 0",
341        "Counter": "0,1,2,3",
342        "EventCode": "0x18",
343        "EventName": "INST_DECODED.DEC0",
344        "SampleAfterValue": "2000000",
345        "UMask": "0x1"
346    },
347    {
348        "BriefDescription": "Instructions written to instruction queue.",
349        "Counter": "0,1,2,3",
350        "EventCode": "0x17",
351        "EventName": "INST_QUEUE_WRITES",
352        "SampleAfterValue": "2000000",
353        "UMask": "0x1"
354    },
355    {
356        "BriefDescription": "Cycles instructions are written to the instruction queue",
357        "Counter": "0,1,2,3",
358        "EventCode": "0x1E",
359        "EventName": "INST_QUEUE_WRITE_CYCLES",
360        "SampleAfterValue": "2000000",
361        "UMask": "0x1"
362    },
363    {
364        "BriefDescription": "Instructions retired (fixed counter)",
365        "Counter": "Fixed counter 1",
366        "EventCode": "0x0",
367        "EventName": "INST_RETIRED.ANY",
368        "SampleAfterValue": "2000000",
369        "UMask": "0x0"
370    },
371    {
372        "BriefDescription": "Instructions retired (Programmable counter and Precise Event)",
373        "Counter": "0,1,2,3",
374        "EventCode": "0xC0",
375        "EventName": "INST_RETIRED.ANY_P",
376        "PEBS": "1",
377        "SampleAfterValue": "2000000",
378        "UMask": "0x1"
379    },
380    {
381        "BriefDescription": "Retired MMX instructions (Precise Event)",
382        "Counter": "0,1,2,3",
383        "EventCode": "0xC0",
384        "EventName": "INST_RETIRED.MMX",
385        "PEBS": "1",
386        "SampleAfterValue": "2000000",
387        "UMask": "0x4"
388    },
389    {
390        "BriefDescription": "Total cycles (Precise Event)",
391        "Counter": "0,1,2,3",
392        "CounterMask": "16",
393        "EventCode": "0xC0",
394        "EventName": "INST_RETIRED.TOTAL_CYCLES",
395        "Invert": "1",
396        "PEBS": "1",
397        "SampleAfterValue": "2000000",
398        "UMask": "0x1"
399    },
400    {
401        "BriefDescription": "Total cycles (Precise Event)",
402        "Counter": "0,1,2,3",
403        "CounterMask": "16",
404        "EventCode": "0xC0",
405        "EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
406        "Invert": "1",
407        "PEBS": "2",
408        "SampleAfterValue": "2000000",
409        "UMask": "0x1"
410    },
411    {
412        "BriefDescription": "Retired floating-point operations (Precise Event)",
413        "Counter": "0,1,2,3",
414        "EventCode": "0xC0",
415        "EventName": "INST_RETIRED.X87",
416        "PEBS": "1",
417        "SampleAfterValue": "2000000",
418        "UMask": "0x2"
419    },
420    {
421        "BriefDescription": "Load operations conflicting with software prefetches",
422        "Counter": "0,1",
423        "EventCode": "0x4C",
424        "EventName": "LOAD_HIT_PRE",
425        "SampleAfterValue": "200000",
426        "UMask": "0x1"
427    },
428    {
429        "BriefDescription": "Cycles when uops were delivered by the LSD",
430        "Counter": "0,1,2,3",
431        "CounterMask": "1",
432        "EventCode": "0xA8",
433        "EventName": "LSD.ACTIVE",
434        "SampleAfterValue": "2000000",
435        "UMask": "0x1"
436    },
437    {
438        "BriefDescription": "Cycles no uops were delivered by the LSD",
439        "Counter": "0,1,2,3",
440        "CounterMask": "1",
441        "EventCode": "0xA8",
442        "EventName": "LSD.INACTIVE",
443        "Invert": "1",
444        "SampleAfterValue": "2000000",
445        "UMask": "0x1"
446    },
447    {
448        "BriefDescription": "Loops that can't stream from the instruction queue",
449        "Counter": "0,1,2,3",
450        "EventCode": "0x20",
451        "EventName": "LSD_OVERFLOW",
452        "SampleAfterValue": "2000000",
453        "UMask": "0x1"
454    },
455    {
456        "BriefDescription": "Cycles machine clear asserted",
457        "Counter": "0,1,2,3",
458        "EventCode": "0xC3",
459        "EventName": "MACHINE_CLEARS.CYCLES",
460        "SampleAfterValue": "20000",
461        "UMask": "0x1"
462    },
463    {
464        "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts",
465        "Counter": "0,1,2,3",
466        "EventCode": "0xC3",
467        "EventName": "MACHINE_CLEARS.MEM_ORDER",
468        "SampleAfterValue": "20000",
469        "UMask": "0x2"
470    },
471    {
472        "BriefDescription": "Self-Modifying Code detected",
473        "Counter": "0,1,2,3",
474        "EventCode": "0xC3",
475        "EventName": "MACHINE_CLEARS.SMC",
476        "SampleAfterValue": "20000",
477        "UMask": "0x4"
478    },
479    {
480        "BriefDescription": "Resource related stall cycles",
481        "Counter": "0,1,2,3",
482        "EventCode": "0xA2",
483        "EventName": "RESOURCE_STALLS.ANY",
484        "SampleAfterValue": "2000000",
485        "UMask": "0x1"
486    },
487    {
488        "BriefDescription": "FPU control word write stall cycles",
489        "Counter": "0,1,2,3",
490        "EventCode": "0xA2",
491        "EventName": "RESOURCE_STALLS.FPCW",
492        "SampleAfterValue": "2000000",
493        "UMask": "0x20"
494    },
495    {
496        "BriefDescription": "Load buffer stall cycles",
497        "Counter": "0,1,2,3",
498        "EventCode": "0xA2",
499        "EventName": "RESOURCE_STALLS.LOAD",
500        "SampleAfterValue": "2000000",
501        "UMask": "0x2"
502    },
503    {
504        "BriefDescription": "MXCSR rename stall cycles",
505        "Counter": "0,1,2,3",
506        "EventCode": "0xA2",
507        "EventName": "RESOURCE_STALLS.MXCSR",
508        "SampleAfterValue": "2000000",
509        "UMask": "0x40"
510    },
511    {
512        "BriefDescription": "Other Resource related stall cycles",
513        "Counter": "0,1,2,3",
514        "EventCode": "0xA2",
515        "EventName": "RESOURCE_STALLS.OTHER",
516        "SampleAfterValue": "2000000",
517        "UMask": "0x80"
518    },
519    {
520        "BriefDescription": "ROB full stall cycles",
521        "Counter": "0,1,2,3",
522        "EventCode": "0xA2",
523        "EventName": "RESOURCE_STALLS.ROB_FULL",
524        "SampleAfterValue": "2000000",
525        "UMask": "0x10"
526    },
527    {
528        "BriefDescription": "Reservation Station full stall cycles",
529        "Counter": "0,1,2,3",
530        "EventCode": "0xA2",
531        "EventName": "RESOURCE_STALLS.RS_FULL",
532        "SampleAfterValue": "2000000",
533        "UMask": "0x4"
534    },
535    {
536        "BriefDescription": "Store buffer stall cycles",
537        "Counter": "0,1,2,3",
538        "EventCode": "0xA2",
539        "EventName": "RESOURCE_STALLS.STORE",
540        "SampleAfterValue": "2000000",
541        "UMask": "0x8"
542    },
543    {
544        "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)",
545        "Counter": "0,1,2,3",
546        "EventCode": "0xC7",
547        "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
548        "PEBS": "1",
549        "SampleAfterValue": "200000",
550        "UMask": "0x4"
551    },
552    {
553        "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)",
554        "Counter": "0,1,2,3",
555        "EventCode": "0xC7",
556        "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
557        "PEBS": "1",
558        "SampleAfterValue": "200000",
559        "UMask": "0x1"
560    },
561    {
562        "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)",
563        "Counter": "0,1,2,3",
564        "EventCode": "0xC7",
565        "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
566        "PEBS": "1",
567        "SampleAfterValue": "200000",
568        "UMask": "0x8"
569    },
570    {
571        "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)",
572        "Counter": "0,1,2,3",
573        "EventCode": "0xC7",
574        "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
575        "PEBS": "1",
576        "SampleAfterValue": "200000",
577        "UMask": "0x2"
578    },
579    {
580        "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)",
581        "Counter": "0,1,2,3",
582        "EventCode": "0xC7",
583        "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
584        "PEBS": "1",
585        "SampleAfterValue": "200000",
586        "UMask": "0x10"
587    },
588    {
589        "BriefDescription": "Stack pointer instructions decoded",
590        "Counter": "0,1,2,3",
591        "EventCode": "0xD1",
592        "EventName": "UOPS_DECODED.ESP_FOLDING",
593        "SampleAfterValue": "2000000",
594        "UMask": "0x4"
595    },
596    {
597        "BriefDescription": "Stack pointer sync operations",
598        "Counter": "0,1,2,3",
599        "EventCode": "0xD1",
600        "EventName": "UOPS_DECODED.ESP_SYNC",
601        "SampleAfterValue": "2000000",
602        "UMask": "0x8"
603    },
604    {
605        "BriefDescription": "Uops decoded by Microcode Sequencer",
606        "Counter": "0,1,2,3",
607        "CounterMask": "1",
608        "EventCode": "0xD1",
609        "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
610        "SampleAfterValue": "2000000",
611        "UMask": "0x2"
612    },
613    {
614        "BriefDescription": "Cycles no Uops are decoded",
615        "Counter": "0,1,2,3",
616        "CounterMask": "1",
617        "EventCode": "0xD1",
618        "EventName": "UOPS_DECODED.STALL_CYCLES",
619        "Invert": "1",
620        "SampleAfterValue": "2000000",
621        "UMask": "0x1"
622    },
623    {
624        "AnyThread": "1",
625        "BriefDescription": "Cycles Uops executed on any port (core count)",
626        "Counter": "0,1,2,3",
627        "CounterMask": "1",
628        "EventCode": "0xB1",
629        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
630        "SampleAfterValue": "2000000",
631        "UMask": "0x3f"
632    },
633    {
634        "AnyThread": "1",
635        "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
636        "Counter": "0,1,2,3",
637        "CounterMask": "1",
638        "EventCode": "0xB1",
639        "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
640        "SampleAfterValue": "2000000",
641        "UMask": "0x1f"
642    },
643    {
644        "AnyThread": "1",
645        "BriefDescription": "Uops executed on any port (core count)",
646        "Counter": "0,1,2,3",
647        "CounterMask": "1",
648        "EdgeDetect": "1",
649        "EventCode": "0xB1",
650        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
651        "Invert": "1",
652        "SampleAfterValue": "2000000",
653        "UMask": "0x3f"
654    },
655    {
656        "AnyThread": "1",
657        "BriefDescription": "Uops executed on ports 0-4 (core count)",
658        "Counter": "0,1,2,3",
659        "CounterMask": "1",
660        "EdgeDetect": "1",
661        "EventCode": "0xB1",
662        "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
663        "Invert": "1",
664        "SampleAfterValue": "2000000",
665        "UMask": "0x1f"
666    },
667    {
668        "AnyThread": "1",
669        "BriefDescription": "Cycles no Uops issued on any port (core count)",
670        "Counter": "0,1,2,3",
671        "CounterMask": "1",
672        "EventCode": "0xB1",
673        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
674        "Invert": "1",
675        "SampleAfterValue": "2000000",
676        "UMask": "0x3f"
677    },
678    {
679        "AnyThread": "1",
680        "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
681        "Counter": "0,1,2,3",
682        "CounterMask": "1",
683        "EventCode": "0xB1",
684        "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
685        "Invert": "1",
686        "SampleAfterValue": "2000000",
687        "UMask": "0x1f"
688    },
689    {
690        "BriefDescription": "Uops executed on port 0",
691        "Counter": "0,1,2,3",
692        "EventCode": "0xB1",
693        "EventName": "UOPS_EXECUTED.PORT0",
694        "SampleAfterValue": "2000000",
695        "UMask": "0x1"
696    },
697    {
698        "BriefDescription": "Uops issued on ports 0, 1 or 5",
699        "Counter": "0,1,2,3",
700        "EventCode": "0xB1",
701        "EventName": "UOPS_EXECUTED.PORT015",
702        "SampleAfterValue": "2000000",
703        "UMask": "0x40"
704    },
705    {
706        "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
707        "Counter": "0,1,2,3",
708        "CounterMask": "1",
709        "EventCode": "0xB1",
710        "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
711        "Invert": "1",
712        "SampleAfterValue": "2000000",
713        "UMask": "0x40"
714    },
715    {
716        "BriefDescription": "Uops executed on port 1",
717        "Counter": "0,1,2,3",
718        "EventCode": "0xB1",
719        "EventName": "UOPS_EXECUTED.PORT1",
720        "SampleAfterValue": "2000000",
721        "UMask": "0x2"
722    },
723    {
724        "AnyThread": "1",
725        "BriefDescription": "Uops issued on ports 2, 3 or 4",
726        "Counter": "0,1,2,3",
727        "EventCode": "0xB1",
728        "EventName": "UOPS_EXECUTED.PORT234_CORE",
729        "SampleAfterValue": "2000000",
730        "UMask": "0x80"
731    },
732    {
733        "AnyThread": "1",
734        "BriefDescription": "Uops executed on port 2 (core count)",
735        "Counter": "0,1,2,3",
736        "EventCode": "0xB1",
737        "EventName": "UOPS_EXECUTED.PORT2_CORE",
738        "SampleAfterValue": "2000000",
739        "UMask": "0x4"
740    },
741    {
742        "AnyThread": "1",
743        "BriefDescription": "Uops executed on port 3 (core count)",
744        "Counter": "0,1,2,3",
745        "EventCode": "0xB1",
746        "EventName": "UOPS_EXECUTED.PORT3_CORE",
747        "SampleAfterValue": "2000000",
748        "UMask": "0x8"
749    },
750    {
751        "AnyThread": "1",
752        "BriefDescription": "Uops executed on port 4 (core count)",
753        "Counter": "0,1,2,3",
754        "EventCode": "0xB1",
755        "EventName": "UOPS_EXECUTED.PORT4_CORE",
756        "SampleAfterValue": "2000000",
757        "UMask": "0x10"
758    },
759    {
760        "BriefDescription": "Uops executed on port 5",
761        "Counter": "0,1,2,3",
762        "EventCode": "0xB1",
763        "EventName": "UOPS_EXECUTED.PORT5",
764        "SampleAfterValue": "2000000",
765        "UMask": "0x20"
766    },
767    {
768        "BriefDescription": "Uops issued",
769        "Counter": "0,1,2,3",
770        "EventCode": "0xE",
771        "EventName": "UOPS_ISSUED.ANY",
772        "SampleAfterValue": "2000000",
773        "UMask": "0x1"
774    },
775    {
776        "AnyThread": "1",
777        "BriefDescription": "Cycles no Uops were issued on any thread",
778        "Counter": "0,1,2,3",
779        "CounterMask": "1",
780        "EventCode": "0xE",
781        "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
782        "Invert": "1",
783        "SampleAfterValue": "2000000",
784        "UMask": "0x1"
785    },
786    {
787        "AnyThread": "1",
788        "BriefDescription": "Cycles Uops were issued on either thread",
789        "Counter": "0,1,2,3",
790        "CounterMask": "1",
791        "EventCode": "0xE",
792        "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
793        "SampleAfterValue": "2000000",
794        "UMask": "0x1"
795    },
796    {
797        "BriefDescription": "Fused Uops issued",
798        "Counter": "0,1,2,3",
799        "EventCode": "0xE",
800        "EventName": "UOPS_ISSUED.FUSED",
801        "SampleAfterValue": "2000000",
802        "UMask": "0x2"
803    },
804    {
805        "BriefDescription": "Cycles no Uops were issued",
806        "Counter": "0,1,2,3",
807        "CounterMask": "1",
808        "EventCode": "0xE",
809        "EventName": "UOPS_ISSUED.STALL_CYCLES",
810        "Invert": "1",
811        "SampleAfterValue": "2000000",
812        "UMask": "0x1"
813    },
814    {
815        "BriefDescription": "Cycles Uops are being retired",
816        "Counter": "0,1,2,3",
817        "CounterMask": "1",
818        "EventCode": "0xC2",
819        "EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
820        "PEBS": "1",
821        "SampleAfterValue": "2000000",
822        "UMask": "0x1"
823    },
824    {
825        "BriefDescription": "Uops retired (Precise Event)",
826        "Counter": "0,1,2,3",
827        "EventCode": "0xC2",
828        "EventName": "UOPS_RETIRED.ANY",
829        "PEBS": "1",
830        "SampleAfterValue": "2000000",
831        "UMask": "0x1"
832    },
833    {
834        "BriefDescription": "Macro-fused Uops retired (Precise Event)",
835        "Counter": "0,1,2,3",
836        "EventCode": "0xC2",
837        "EventName": "UOPS_RETIRED.MACRO_FUSED",
838        "PEBS": "1",
839        "SampleAfterValue": "2000000",
840        "UMask": "0x4"
841    },
842    {
843        "BriefDescription": "Retirement slots used (Precise Event)",
844        "Counter": "0,1,2,3",
845        "EventCode": "0xC2",
846        "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
847        "PEBS": "1",
848        "SampleAfterValue": "2000000",
849        "UMask": "0x2"
850    },
851    {
852        "BriefDescription": "Cycles Uops are not retiring (Precise Event)",
853        "Counter": "0,1,2,3",
854        "CounterMask": "1",
855        "EventCode": "0xC2",
856        "EventName": "UOPS_RETIRED.STALL_CYCLES",
857        "Invert": "1",
858        "PEBS": "1",
859        "SampleAfterValue": "2000000",
860        "UMask": "0x1"
861    },
862    {
863        "BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
864        "Counter": "0,1,2,3",
865        "CounterMask": "16",
866        "EventCode": "0xC2",
867        "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
868        "Invert": "1",
869        "PEBS": "1",
870        "SampleAfterValue": "2000000",
871        "UMask": "0x1"
872    },
873    {
874        "BriefDescription": "Uop unfusions due to FP exceptions",
875        "Counter": "0,1,2,3",
876        "EventCode": "0xDB",
877        "EventName": "UOP_UNFUSION",
878        "SampleAfterValue": "2000000",
879        "UMask": "0x1"
880    }
881]