1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "All references to the L1 data cache", 52 "Counter": "0,1", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.ANY", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1 data cacheable reads and writes", 60 "Counter": "0,1", 61 "EventCode": "0x43", 62 "EventName": "L1D_ALL_REF.CACHEABLE", 63 "SampleAfterValue": "2000000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1 data cache read in E state", 68 "Counter": "0,1", 69 "EventCode": "0x40", 70 "EventName": "L1D_CACHE_LD.E_STATE", 71 "SampleAfterValue": "2000000", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "L1 data cache read in I state (misses)", 76 "Counter": "0,1", 77 "EventCode": "0x40", 78 "EventName": "L1D_CACHE_LD.I_STATE", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "L1 data cache reads", 84 "Counter": "0,1", 85 "EventCode": "0x40", 86 "EventName": "L1D_CACHE_LD.MESI", 87 "SampleAfterValue": "2000000", 88 "UMask": "0xf" 89 }, 90 { 91 "BriefDescription": "L1 data cache read in M state", 92 "Counter": "0,1", 93 "EventCode": "0x40", 94 "EventName": "L1D_CACHE_LD.M_STATE", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x8" 97 }, 98 { 99 "BriefDescription": "L1 data cache read in S state", 100 "Counter": "0,1", 101 "EventCode": "0x40", 102 "EventName": "L1D_CACHE_LD.S_STATE", 103 "SampleAfterValue": "2000000", 104 "UMask": "0x2" 105 }, 106 { 107 "BriefDescription": "L1 data cache load locks in E state", 108 "Counter": "0,1", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.E_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x4" 113 }, 114 { 115 "BriefDescription": "L1 data cache load lock hits", 116 "Counter": "0,1", 117 "EventCode": "0x42", 118 "EventName": "L1D_CACHE_LOCK.HIT", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "L1 data cache load locks in M state", 124 "Counter": "0,1", 125 "EventCode": "0x42", 126 "EventName": "L1D_CACHE_LOCK.M_STATE", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x8" 129 }, 130 { 131 "BriefDescription": "L1 data cache load locks in S state", 132 "Counter": "0,1", 133 "EventCode": "0x42", 134 "EventName": "L1D_CACHE_LOCK.S_STATE", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x2" 137 }, 138 { 139 "BriefDescription": "L1D load lock accepted in fill buffer", 140 "Counter": "0,1", 141 "EventCode": "0x53", 142 "EventName": "L1D_CACHE_LOCK_FB_HIT", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 148 "Counter": "0,1", 149 "EventCode": "0x52", 150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "L1 data cache stores in E state", 156 "Counter": "0,1", 157 "EventCode": "0x41", 158 "EventName": "L1D_CACHE_ST.E_STATE", 159 "SampleAfterValue": "2000000", 160 "UMask": "0x4" 161 }, 162 { 163 "BriefDescription": "L1 data cache stores in M state", 164 "Counter": "0,1", 165 "EventCode": "0x41", 166 "EventName": "L1D_CACHE_ST.M_STATE", 167 "SampleAfterValue": "2000000", 168 "UMask": "0x8" 169 }, 170 { 171 "BriefDescription": "L1 data cache stores in S state", 172 "Counter": "0,1", 173 "EventCode": "0x41", 174 "EventName": "L1D_CACHE_ST.S_STATE", 175 "SampleAfterValue": "2000000", 176 "UMask": "0x2" 177 }, 178 { 179 "BriefDescription": "L1D hardware prefetch misses", 180 "Counter": "0,1", 181 "EventCode": "0x4E", 182 "EventName": "L1D_PREFETCH.MISS", 183 "SampleAfterValue": "200000", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "L1D hardware prefetch requests", 188 "Counter": "0,1", 189 "EventCode": "0x4E", 190 "EventName": "L1D_PREFETCH.REQUESTS", 191 "SampleAfterValue": "200000", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "L1D hardware prefetch requests triggered", 196 "Counter": "0,1", 197 "EventCode": "0x4E", 198 "EventName": "L1D_PREFETCH.TRIGGERS", 199 "SampleAfterValue": "200000", 200 "UMask": "0x4" 201 }, 202 { 203 "BriefDescription": "L1 writebacks to L2 in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x28", 206 "EventName": "L1D_WB_L2.E_STATE", 207 "SampleAfterValue": "100000", 208 "UMask": "0x4" 209 }, 210 { 211 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x28", 214 "EventName": "L1D_WB_L2.I_STATE", 215 "SampleAfterValue": "100000", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "All L1 writebacks to L2", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x28", 222 "EventName": "L1D_WB_L2.MESI", 223 "SampleAfterValue": "100000", 224 "UMask": "0xf" 225 }, 226 { 227 "BriefDescription": "L1 writebacks to L2 in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x28", 230 "EventName": "L1D_WB_L2.M_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x8" 233 }, 234 { 235 "BriefDescription": "L1 writebacks to L2 in S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x28", 238 "EventName": "L1D_WB_L2.S_STATE", 239 "SampleAfterValue": "100000", 240 "UMask": "0x2" 241 }, 242 { 243 "BriefDescription": "L1I instruction fetch stall cycles", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x80", 246 "EventName": "L1I.CYCLES_STALLED", 247 "SampleAfterValue": "2000000", 248 "UMask": "0x4" 249 }, 250 { 251 "BriefDescription": "L1I instruction fetch hits", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x80", 254 "EventName": "L1I.HITS", 255 "SampleAfterValue": "2000000", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "L1I instruction fetch misses", 260 "Counter": "0,1,2,3", 261 "EventCode": "0x80", 262 "EventName": "L1I.MISSES", 263 "SampleAfterValue": "2000000", 264 "UMask": "0x2" 265 }, 266 { 267 "BriefDescription": "L1I Instruction fetches", 268 "Counter": "0,1,2,3", 269 "EventCode": "0x80", 270 "EventName": "L1I.READS", 271 "SampleAfterValue": "2000000", 272 "UMask": "0x3" 273 }, 274 { 275 "BriefDescription": "All L2 data requests", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.ANY", 279 "SampleAfterValue": "200000", 280 "UMask": "0xff" 281 }, 282 { 283 "BriefDescription": "L2 data demand loads in E state", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x26", 286 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 287 "SampleAfterValue": "200000", 288 "UMask": "0x4" 289 }, 290 { 291 "BriefDescription": "L2 data demand loads in I state (misses)", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x26", 294 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 295 "SampleAfterValue": "200000", 296 "UMask": "0x1" 297 }, 298 { 299 "BriefDescription": "L2 data demand requests", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x26", 302 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 303 "SampleAfterValue": "200000", 304 "UMask": "0xf" 305 }, 306 { 307 "BriefDescription": "L2 data demand loads in M state", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x26", 310 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 311 "SampleAfterValue": "200000", 312 "UMask": "0x8" 313 }, 314 { 315 "BriefDescription": "L2 data demand loads in S state", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x26", 318 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 319 "SampleAfterValue": "200000", 320 "UMask": "0x2" 321 }, 322 { 323 "BriefDescription": "L2 data prefetches in E state", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x26", 326 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 327 "SampleAfterValue": "200000", 328 "UMask": "0x40" 329 }, 330 { 331 "BriefDescription": "L2 data prefetches in the I state (misses)", 332 "Counter": "0,1,2,3", 333 "EventCode": "0x26", 334 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 335 "SampleAfterValue": "200000", 336 "UMask": "0x10" 337 }, 338 { 339 "BriefDescription": "All L2 data prefetches", 340 "Counter": "0,1,2,3", 341 "EventCode": "0x26", 342 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 343 "SampleAfterValue": "200000", 344 "UMask": "0xf0" 345 }, 346 { 347 "BriefDescription": "L2 data prefetches in M state", 348 "Counter": "0,1,2,3", 349 "EventCode": "0x26", 350 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 351 "SampleAfterValue": "200000", 352 "UMask": "0x80" 353 }, 354 { 355 "BriefDescription": "L2 data prefetches in the S state", 356 "Counter": "0,1,2,3", 357 "EventCode": "0x26", 358 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 359 "SampleAfterValue": "200000", 360 "UMask": "0x20" 361 }, 362 { 363 "BriefDescription": "L2 lines allocated", 364 "Counter": "0,1,2,3", 365 "EventCode": "0xF1", 366 "EventName": "L2_LINES_IN.ANY", 367 "SampleAfterValue": "100000", 368 "UMask": "0x7" 369 }, 370 { 371 "BriefDescription": "L2 lines allocated in the E state", 372 "Counter": "0,1,2,3", 373 "EventCode": "0xF1", 374 "EventName": "L2_LINES_IN.E_STATE", 375 "SampleAfterValue": "100000", 376 "UMask": "0x4" 377 }, 378 { 379 "BriefDescription": "L2 lines allocated in the S state", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xF1", 382 "EventName": "L2_LINES_IN.S_STATE", 383 "SampleAfterValue": "100000", 384 "UMask": "0x2" 385 }, 386 { 387 "BriefDescription": "L2 lines evicted", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF2", 390 "EventName": "L2_LINES_OUT.ANY", 391 "SampleAfterValue": "100000", 392 "UMask": "0xf" 393 }, 394 { 395 "BriefDescription": "L2 lines evicted by a demand request", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xF2", 398 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 399 "SampleAfterValue": "100000", 400 "UMask": "0x1" 401 }, 402 { 403 "BriefDescription": "L2 modified lines evicted by a demand request", 404 "Counter": "0,1,2,3", 405 "EventCode": "0xF2", 406 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 407 "SampleAfterValue": "100000", 408 "UMask": "0x2" 409 }, 410 { 411 "BriefDescription": "L2 lines evicted by a prefetch request", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xF2", 414 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 415 "SampleAfterValue": "100000", 416 "UMask": "0x4" 417 }, 418 { 419 "BriefDescription": "L2 modified lines evicted by a prefetch request", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xF2", 422 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 423 "SampleAfterValue": "100000", 424 "UMask": "0x8" 425 }, 426 { 427 "BriefDescription": "L2 instruction fetches", 428 "Counter": "0,1,2,3", 429 "EventCode": "0x24", 430 "EventName": "L2_RQSTS.IFETCHES", 431 "SampleAfterValue": "200000", 432 "UMask": "0x30" 433 }, 434 { 435 "BriefDescription": "L2 instruction fetch hits", 436 "Counter": "0,1,2,3", 437 "EventCode": "0x24", 438 "EventName": "L2_RQSTS.IFETCH_HIT", 439 "SampleAfterValue": "200000", 440 "UMask": "0x10" 441 }, 442 { 443 "BriefDescription": "L2 instruction fetch misses", 444 "Counter": "0,1,2,3", 445 "EventCode": "0x24", 446 "EventName": "L2_RQSTS.IFETCH_MISS", 447 "SampleAfterValue": "200000", 448 "UMask": "0x20" 449 }, 450 { 451 "BriefDescription": "L2 load hits", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x24", 454 "EventName": "L2_RQSTS.LD_HIT", 455 "SampleAfterValue": "200000", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "L2 load misses", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x24", 462 "EventName": "L2_RQSTS.LD_MISS", 463 "SampleAfterValue": "200000", 464 "UMask": "0x2" 465 }, 466 { 467 "BriefDescription": "L2 requests", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x24", 470 "EventName": "L2_RQSTS.LOADS", 471 "SampleAfterValue": "200000", 472 "UMask": "0x3" 473 }, 474 { 475 "BriefDescription": "All L2 misses", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x24", 478 "EventName": "L2_RQSTS.MISS", 479 "SampleAfterValue": "200000", 480 "UMask": "0xaa" 481 }, 482 { 483 "BriefDescription": "All L2 prefetches", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x24", 486 "EventName": "L2_RQSTS.PREFETCHES", 487 "SampleAfterValue": "200000", 488 "UMask": "0xc0" 489 }, 490 { 491 "BriefDescription": "L2 prefetch hits", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x24", 494 "EventName": "L2_RQSTS.PREFETCH_HIT", 495 "SampleAfterValue": "200000", 496 "UMask": "0x40" 497 }, 498 { 499 "BriefDescription": "L2 prefetch misses", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x24", 502 "EventName": "L2_RQSTS.PREFETCH_MISS", 503 "SampleAfterValue": "200000", 504 "UMask": "0x80" 505 }, 506 { 507 "BriefDescription": "All L2 requests", 508 "Counter": "0,1,2,3", 509 "EventCode": "0x24", 510 "EventName": "L2_RQSTS.REFERENCES", 511 "SampleAfterValue": "200000", 512 "UMask": "0xff" 513 }, 514 { 515 "BriefDescription": "L2 RFO requests", 516 "Counter": "0,1,2,3", 517 "EventCode": "0x24", 518 "EventName": "L2_RQSTS.RFOS", 519 "SampleAfterValue": "200000", 520 "UMask": "0xc" 521 }, 522 { 523 "BriefDescription": "L2 RFO hits", 524 "Counter": "0,1,2,3", 525 "EventCode": "0x24", 526 "EventName": "L2_RQSTS.RFO_HIT", 527 "SampleAfterValue": "200000", 528 "UMask": "0x4" 529 }, 530 { 531 "BriefDescription": "L2 RFO misses", 532 "Counter": "0,1,2,3", 533 "EventCode": "0x24", 534 "EventName": "L2_RQSTS.RFO_MISS", 535 "SampleAfterValue": "200000", 536 "UMask": "0x8" 537 }, 538 { 539 "BriefDescription": "All L2 transactions", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xF0", 542 "EventName": "L2_TRANSACTIONS.ANY", 543 "SampleAfterValue": "200000", 544 "UMask": "0x80" 545 }, 546 { 547 "BriefDescription": "L2 fill transactions", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xF0", 550 "EventName": "L2_TRANSACTIONS.FILL", 551 "SampleAfterValue": "200000", 552 "UMask": "0x20" 553 }, 554 { 555 "BriefDescription": "L2 instruction fetch transactions", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xF0", 558 "EventName": "L2_TRANSACTIONS.IFETCH", 559 "SampleAfterValue": "200000", 560 "UMask": "0x4" 561 }, 562 { 563 "BriefDescription": "L1D writeback to L2 transactions", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xF0", 566 "EventName": "L2_TRANSACTIONS.L1D_WB", 567 "SampleAfterValue": "200000", 568 "UMask": "0x10" 569 }, 570 { 571 "BriefDescription": "L2 Load transactions", 572 "Counter": "0,1,2,3", 573 "EventCode": "0xF0", 574 "EventName": "L2_TRANSACTIONS.LOAD", 575 "SampleAfterValue": "200000", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "L2 prefetch transactions", 580 "Counter": "0,1,2,3", 581 "EventCode": "0xF0", 582 "EventName": "L2_TRANSACTIONS.PREFETCH", 583 "SampleAfterValue": "200000", 584 "UMask": "0x8" 585 }, 586 { 587 "BriefDescription": "L2 RFO transactions", 588 "Counter": "0,1,2,3", 589 "EventCode": "0xF0", 590 "EventName": "L2_TRANSACTIONS.RFO", 591 "SampleAfterValue": "200000", 592 "UMask": "0x2" 593 }, 594 { 595 "BriefDescription": "L2 writeback to LLC transactions", 596 "Counter": "0,1,2,3", 597 "EventCode": "0xF0", 598 "EventName": "L2_TRANSACTIONS.WB", 599 "SampleAfterValue": "200000", 600 "UMask": "0x40" 601 }, 602 { 603 "BriefDescription": "L2 demand lock RFOs in E state", 604 "Counter": "0,1,2,3", 605 "EventCode": "0x27", 606 "EventName": "L2_WRITE.LOCK.E_STATE", 607 "SampleAfterValue": "100000", 608 "UMask": "0x40" 609 }, 610 { 611 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 612 "Counter": "0,1,2,3", 613 "EventCode": "0x27", 614 "EventName": "L2_WRITE.LOCK.HIT", 615 "SampleAfterValue": "100000", 616 "UMask": "0xe0" 617 }, 618 { 619 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 620 "Counter": "0,1,2,3", 621 "EventCode": "0x27", 622 "EventName": "L2_WRITE.LOCK.I_STATE", 623 "SampleAfterValue": "100000", 624 "UMask": "0x10" 625 }, 626 { 627 "BriefDescription": "All demand L2 lock RFOs", 628 "Counter": "0,1,2,3", 629 "EventCode": "0x27", 630 "EventName": "L2_WRITE.LOCK.MESI", 631 "SampleAfterValue": "100000", 632 "UMask": "0xf0" 633 }, 634 { 635 "BriefDescription": "L2 demand lock RFOs in M state", 636 "Counter": "0,1,2,3", 637 "EventCode": "0x27", 638 "EventName": "L2_WRITE.LOCK.M_STATE", 639 "SampleAfterValue": "100000", 640 "UMask": "0x80" 641 }, 642 { 643 "BriefDescription": "L2 demand lock RFOs in S state", 644 "Counter": "0,1,2,3", 645 "EventCode": "0x27", 646 "EventName": "L2_WRITE.LOCK.S_STATE", 647 "SampleAfterValue": "100000", 648 "UMask": "0x20" 649 }, 650 { 651 "BriefDescription": "All L2 demand store RFOs that hit the cache", 652 "Counter": "0,1,2,3", 653 "EventCode": "0x27", 654 "EventName": "L2_WRITE.RFO.HIT", 655 "SampleAfterValue": "100000", 656 "UMask": "0xe" 657 }, 658 { 659 "BriefDescription": "L2 demand store RFOs in I state (misses)", 660 "Counter": "0,1,2,3", 661 "EventCode": "0x27", 662 "EventName": "L2_WRITE.RFO.I_STATE", 663 "SampleAfterValue": "100000", 664 "UMask": "0x1" 665 }, 666 { 667 "BriefDescription": "All L2 demand store RFOs", 668 "Counter": "0,1,2,3", 669 "EventCode": "0x27", 670 "EventName": "L2_WRITE.RFO.MESI", 671 "SampleAfterValue": "100000", 672 "UMask": "0xf" 673 }, 674 { 675 "BriefDescription": "L2 demand store RFOs in M state", 676 "Counter": "0,1,2,3", 677 "EventCode": "0x27", 678 "EventName": "L2_WRITE.RFO.M_STATE", 679 "SampleAfterValue": "100000", 680 "UMask": "0x8" 681 }, 682 { 683 "BriefDescription": "L2 demand store RFOs in S state", 684 "Counter": "0,1,2,3", 685 "EventCode": "0x27", 686 "EventName": "L2_WRITE.RFO.S_STATE", 687 "SampleAfterValue": "100000", 688 "UMask": "0x2" 689 }, 690 { 691 "BriefDescription": "Longest latency cache miss", 692 "Counter": "0,1,2,3", 693 "EventCode": "0x2E", 694 "EventName": "LONGEST_LAT_CACHE.MISS", 695 "SampleAfterValue": "100000", 696 "UMask": "0x41" 697 }, 698 { 699 "BriefDescription": "Longest latency cache reference", 700 "Counter": "0,1,2,3", 701 "EventCode": "0x2E", 702 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 703 "SampleAfterValue": "200000", 704 "UMask": "0x4f" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 711 "MSRIndex": "0x3F6", 712 "PEBS": "2", 713 "SampleAfterValue": "2000000", 714 "UMask": "0x10" 715 }, 716 { 717 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 718 "Counter": "3", 719 "EventCode": "0xB", 720 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 721 "MSRIndex": "0x3F6", 722 "MSRValue": "0x400", 723 "PEBS": "2", 724 "SampleAfterValue": "100", 725 "UMask": "0x10" 726 }, 727 { 728 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 729 "Counter": "3", 730 "EventCode": "0xB", 731 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 732 "MSRIndex": "0x3F6", 733 "MSRValue": "0x80", 734 "PEBS": "2", 735 "SampleAfterValue": "1000", 736 "UMask": "0x10" 737 }, 738 { 739 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 740 "Counter": "3", 741 "EventCode": "0xB", 742 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 743 "MSRIndex": "0x3F6", 744 "MSRValue": "0x10", 745 "PEBS": "2", 746 "SampleAfterValue": "10000", 747 "UMask": "0x10" 748 }, 749 { 750 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 751 "Counter": "3", 752 "EventCode": "0xB", 753 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 754 "MSRIndex": "0x3F6", 755 "MSRValue": "0x4000", 756 "PEBS": "2", 757 "SampleAfterValue": "5", 758 "UMask": "0x10" 759 }, 760 { 761 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 762 "Counter": "3", 763 "EventCode": "0xB", 764 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 765 "MSRIndex": "0x3F6", 766 "MSRValue": "0x800", 767 "PEBS": "2", 768 "SampleAfterValue": "50", 769 "UMask": "0x10" 770 }, 771 { 772 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 773 "Counter": "3", 774 "EventCode": "0xB", 775 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 776 "MSRIndex": "0x3F6", 777 "MSRValue": "0x100", 778 "PEBS": "2", 779 "SampleAfterValue": "500", 780 "UMask": "0x10" 781 }, 782 { 783 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 784 "Counter": "3", 785 "EventCode": "0xB", 786 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 787 "MSRIndex": "0x3F6", 788 "MSRValue": "0x20", 789 "PEBS": "2", 790 "SampleAfterValue": "5000", 791 "UMask": "0x10" 792 }, 793 { 794 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 795 "Counter": "3", 796 "EventCode": "0xB", 797 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 798 "MSRIndex": "0x3F6", 799 "MSRValue": "0x8000", 800 "PEBS": "2", 801 "SampleAfterValue": "3", 802 "UMask": "0x10" 803 }, 804 { 805 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 806 "Counter": "3", 807 "EventCode": "0xB", 808 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 809 "MSRIndex": "0x3F6", 810 "MSRValue": "0x4", 811 "PEBS": "2", 812 "SampleAfterValue": "50000", 813 "UMask": "0x10" 814 }, 815 { 816 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 817 "Counter": "3", 818 "EventCode": "0xB", 819 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 820 "MSRIndex": "0x3F6", 821 "MSRValue": "0x1000", 822 "PEBS": "2", 823 "SampleAfterValue": "20", 824 "UMask": "0x10" 825 }, 826 { 827 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 828 "Counter": "3", 829 "EventCode": "0xB", 830 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 831 "MSRIndex": "0x3F6", 832 "MSRValue": "0x200", 833 "PEBS": "2", 834 "SampleAfterValue": "200", 835 "UMask": "0x10" 836 }, 837 { 838 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 839 "Counter": "3", 840 "EventCode": "0xB", 841 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 842 "MSRIndex": "0x3F6", 843 "MSRValue": "0x40", 844 "PEBS": "2", 845 "SampleAfterValue": "2000", 846 "UMask": "0x10" 847 }, 848 { 849 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 850 "Counter": "3", 851 "EventCode": "0xB", 852 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 853 "MSRIndex": "0x3F6", 854 "MSRValue": "0x8", 855 "PEBS": "2", 856 "SampleAfterValue": "20000", 857 "UMask": "0x10" 858 }, 859 { 860 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 861 "Counter": "3", 862 "EventCode": "0xB", 863 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 864 "MSRIndex": "0x3F6", 865 "MSRValue": "0x2000", 866 "PEBS": "2", 867 "SampleAfterValue": "10", 868 "UMask": "0x10" 869 }, 870 { 871 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 872 "Counter": "0,1,2,3", 873 "EventCode": "0xB", 874 "EventName": "MEM_INST_RETIRED.LOADS", 875 "PEBS": "1", 876 "SampleAfterValue": "2000000", 877 "UMask": "0x1" 878 }, 879 { 880 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 881 "Counter": "0,1,2,3", 882 "EventCode": "0xB", 883 "EventName": "MEM_INST_RETIRED.STORES", 884 "PEBS": "1", 885 "SampleAfterValue": "2000000", 886 "UMask": "0x2" 887 }, 888 { 889 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 890 "Counter": "0,1,2,3", 891 "EventCode": "0xCB", 892 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 893 "PEBS": "1", 894 "SampleAfterValue": "200000", 895 "UMask": "0x40" 896 }, 897 { 898 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 899 "Counter": "0,1,2,3", 900 "EventCode": "0xCB", 901 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 902 "PEBS": "1", 903 "SampleAfterValue": "2000000", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 908 "Counter": "0,1,2,3", 909 "EventCode": "0xCB", 910 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 911 "PEBS": "1", 912 "SampleAfterValue": "200000", 913 "UMask": "0x2" 914 }, 915 { 916 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 917 "Counter": "0,1,2,3", 918 "EventCode": "0xCB", 919 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 920 "PEBS": "1", 921 "SampleAfterValue": "10000", 922 "UMask": "0x10" 923 }, 924 { 925 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 926 "Counter": "0,1,2,3", 927 "EventCode": "0xCB", 928 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 929 "PEBS": "1", 930 "SampleAfterValue": "40000", 931 "UMask": "0x4" 932 }, 933 { 934 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 935 "Counter": "0,1,2,3", 936 "EventCode": "0xCB", 937 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 938 "PEBS": "1", 939 "SampleAfterValue": "40000", 940 "UMask": "0x8" 941 }, 942 { 943 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 944 "Counter": "0,1,2,3", 945 "EventCode": "0xF", 946 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 947 "PEBS": "1", 948 "SampleAfterValue": "10000", 949 "UMask": "0x20" 950 }, 951 { 952 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 953 "Counter": "0,1,2,3", 954 "EventCode": "0xF", 955 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 956 "PEBS": "1", 957 "SampleAfterValue": "40000", 958 "UMask": "0x2" 959 }, 960 { 961 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 962 "Counter": "0,1,2,3", 963 "EventCode": "0xF", 964 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 965 "PEBS": "1", 966 "SampleAfterValue": "20000", 967 "UMask": "0x8" 968 }, 969 { 970 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 971 "Counter": "0,1,2,3", 972 "EventCode": "0xF", 973 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 974 "PEBS": "1", 975 "SampleAfterValue": "10000", 976 "UMask": "0x10" 977 }, 978 { 979 "BriefDescription": "Load instructions retired IO (Precise Event)", 980 "Counter": "0,1,2,3", 981 "EventCode": "0xF", 982 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 983 "PEBS": "1", 984 "SampleAfterValue": "4000", 985 "UMask": "0x80" 986 }, 987 { 988 "BriefDescription": "Offcore L1 data cache writebacks", 989 "Counter": "0,1,2,3", 990 "EventCode": "0xB0", 991 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 992 "SampleAfterValue": "100000", 993 "UMask": "0x40" 994 }, 995 { 996 "BriefDescription": "Offcore requests blocked due to Super Queue full", 997 "Counter": "0,1,2,3", 998 "EventCode": "0xB2", 999 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 1000 "SampleAfterValue": "100000", 1001 "UMask": "0x1" 1002 }, 1003 { 1004 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 1005 "Counter": "2", 1006 "EventCode": "0xB7", 1007 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 1008 "MSRIndex": "0x1A6", 1009 "MSRValue": "0x7F11", 1010 "SampleAfterValue": "100000", 1011 "UMask": "0x1" 1012 }, 1013 { 1014 "BriefDescription": "All offcore data reads", 1015 "Counter": "2", 1016 "EventCode": "0xB7", 1017 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 1018 "MSRIndex": "0x1A6", 1019 "MSRValue": "0xFF11", 1020 "SampleAfterValue": "100000", 1021 "UMask": "0x1" 1022 }, 1023 { 1024 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 1025 "Counter": "2", 1026 "EventCode": "0xB7", 1027 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 1028 "MSRIndex": "0x1A6", 1029 "MSRValue": "0x8011", 1030 "SampleAfterValue": "100000", 1031 "UMask": "0x1" 1032 }, 1033 { 1034 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1035 "Counter": "2", 1036 "EventCode": "0xB7", 1037 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1038 "MSRIndex": "0x1A6", 1039 "MSRValue": "0x111", 1040 "SampleAfterValue": "100000", 1041 "UMask": "0x1" 1042 }, 1043 { 1044 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1045 "Counter": "2", 1046 "EventCode": "0xB7", 1047 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1048 "MSRIndex": "0x1A6", 1049 "MSRValue": "0x211", 1050 "SampleAfterValue": "100000", 1051 "UMask": "0x1" 1052 }, 1053 { 1054 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1055 "Counter": "2", 1056 "EventCode": "0xB7", 1057 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1058 "MSRIndex": "0x1A6", 1059 "MSRValue": "0x411", 1060 "SampleAfterValue": "100000", 1061 "UMask": "0x1" 1062 }, 1063 { 1064 "BriefDescription": "Offcore data reads satisfied by the LLC", 1065 "Counter": "2", 1066 "EventCode": "0xB7", 1067 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1068 "MSRIndex": "0x1A6", 1069 "MSRValue": "0x711", 1070 "SampleAfterValue": "100000", 1071 "UMask": "0x1" 1072 }, 1073 { 1074 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1075 "Counter": "2", 1076 "EventCode": "0xB7", 1077 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1078 "MSRIndex": "0x1A6", 1079 "MSRValue": "0x4711", 1080 "SampleAfterValue": "100000", 1081 "UMask": "0x1" 1082 }, 1083 { 1084 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1085 "Counter": "2", 1086 "EventCode": "0xB7", 1087 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1088 "MSRIndex": "0x1A6", 1089 "MSRValue": "0x1811", 1090 "SampleAfterValue": "100000", 1091 "UMask": "0x1" 1092 }, 1093 { 1094 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1095 "Counter": "2", 1096 "EventCode": "0xB7", 1097 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1098 "MSRIndex": "0x1A6", 1099 "MSRValue": "0x3811", 1100 "SampleAfterValue": "100000", 1101 "UMask": "0x1" 1102 }, 1103 { 1104 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1105 "Counter": "2", 1106 "EventCode": "0xB7", 1107 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1108 "MSRIndex": "0x1A6", 1109 "MSRValue": "0x1011", 1110 "SampleAfterValue": "100000", 1111 "UMask": "0x1" 1112 }, 1113 { 1114 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1115 "Counter": "2", 1116 "EventCode": "0xB7", 1117 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1118 "MSRIndex": "0x1A6", 1119 "MSRValue": "0x811", 1120 "SampleAfterValue": "100000", 1121 "UMask": "0x1" 1122 }, 1123 { 1124 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1125 "Counter": "2", 1126 "EventCode": "0xB7", 1127 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1128 "MSRIndex": "0x1A6", 1129 "MSRValue": "0x7F44", 1130 "SampleAfterValue": "100000", 1131 "UMask": "0x1" 1132 }, 1133 { 1134 "BriefDescription": "All offcore code reads", 1135 "Counter": "2", 1136 "EventCode": "0xB7", 1137 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1138 "MSRIndex": "0x1A6", 1139 "MSRValue": "0xFF44", 1140 "SampleAfterValue": "100000", 1141 "UMask": "0x1" 1142 }, 1143 { 1144 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1145 "Counter": "2", 1146 "EventCode": "0xB7", 1147 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1148 "MSRIndex": "0x1A6", 1149 "MSRValue": "0x8044", 1150 "SampleAfterValue": "100000", 1151 "UMask": "0x1" 1152 }, 1153 { 1154 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1155 "Counter": "2", 1156 "EventCode": "0xB7", 1157 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1158 "MSRIndex": "0x1A6", 1159 "MSRValue": "0x144", 1160 "SampleAfterValue": "100000", 1161 "UMask": "0x1" 1162 }, 1163 { 1164 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1165 "Counter": "2", 1166 "EventCode": "0xB7", 1167 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1168 "MSRIndex": "0x1A6", 1169 "MSRValue": "0x244", 1170 "SampleAfterValue": "100000", 1171 "UMask": "0x1" 1172 }, 1173 { 1174 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1175 "Counter": "2", 1176 "EventCode": "0xB7", 1177 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1178 "MSRIndex": "0x1A6", 1179 "MSRValue": "0x444", 1180 "SampleAfterValue": "100000", 1181 "UMask": "0x1" 1182 }, 1183 { 1184 "BriefDescription": "Offcore code reads satisfied by the LLC", 1185 "Counter": "2", 1186 "EventCode": "0xB7", 1187 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1188 "MSRIndex": "0x1A6", 1189 "MSRValue": "0x744", 1190 "SampleAfterValue": "100000", 1191 "UMask": "0x1" 1192 }, 1193 { 1194 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1195 "Counter": "2", 1196 "EventCode": "0xB7", 1197 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1198 "MSRIndex": "0x1A6", 1199 "MSRValue": "0x4744", 1200 "SampleAfterValue": "100000", 1201 "UMask": "0x1" 1202 }, 1203 { 1204 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1205 "Counter": "2", 1206 "EventCode": "0xB7", 1207 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1208 "MSRIndex": "0x1A6", 1209 "MSRValue": "0x1844", 1210 "SampleAfterValue": "100000", 1211 "UMask": "0x1" 1212 }, 1213 { 1214 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1215 "Counter": "2", 1216 "EventCode": "0xB7", 1217 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1218 "MSRIndex": "0x1A6", 1219 "MSRValue": "0x3844", 1220 "SampleAfterValue": "100000", 1221 "UMask": "0x1" 1222 }, 1223 { 1224 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1225 "Counter": "2", 1226 "EventCode": "0xB7", 1227 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1228 "MSRIndex": "0x1A6", 1229 "MSRValue": "0x1044", 1230 "SampleAfterValue": "100000", 1231 "UMask": "0x1" 1232 }, 1233 { 1234 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1235 "Counter": "2", 1236 "EventCode": "0xB7", 1237 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1238 "MSRIndex": "0x1A6", 1239 "MSRValue": "0x844", 1240 "SampleAfterValue": "100000", 1241 "UMask": "0x1" 1242 }, 1243 { 1244 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1245 "Counter": "2", 1246 "EventCode": "0xB7", 1247 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1248 "MSRIndex": "0x1A6", 1249 "MSRValue": "0x7FFF", 1250 "SampleAfterValue": "100000", 1251 "UMask": "0x1" 1252 }, 1253 { 1254 "BriefDescription": "All offcore requests", 1255 "Counter": "2", 1256 "EventCode": "0xB7", 1257 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1258 "MSRIndex": "0x1A6", 1259 "MSRValue": "0xFFFF", 1260 "SampleAfterValue": "100000", 1261 "UMask": "0x1" 1262 }, 1263 { 1264 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1265 "Counter": "2", 1266 "EventCode": "0xB7", 1267 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1268 "MSRIndex": "0x1A6", 1269 "MSRValue": "0x80FF", 1270 "SampleAfterValue": "100000", 1271 "UMask": "0x1" 1272 }, 1273 { 1274 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1275 "Counter": "2", 1276 "EventCode": "0xB7", 1277 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1278 "MSRIndex": "0x1A6", 1279 "MSRValue": "0x1FF", 1280 "SampleAfterValue": "100000", 1281 "UMask": "0x1" 1282 }, 1283 { 1284 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1285 "Counter": "2", 1286 "EventCode": "0xB7", 1287 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1288 "MSRIndex": "0x1A6", 1289 "MSRValue": "0x2FF", 1290 "SampleAfterValue": "100000", 1291 "UMask": "0x1" 1292 }, 1293 { 1294 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1295 "Counter": "2", 1296 "EventCode": "0xB7", 1297 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1298 "MSRIndex": "0x1A6", 1299 "MSRValue": "0x4FF", 1300 "SampleAfterValue": "100000", 1301 "UMask": "0x1" 1302 }, 1303 { 1304 "BriefDescription": "Offcore requests satisfied by the LLC", 1305 "Counter": "2", 1306 "EventCode": "0xB7", 1307 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1308 "MSRIndex": "0x1A6", 1309 "MSRValue": "0x7FF", 1310 "SampleAfterValue": "100000", 1311 "UMask": "0x1" 1312 }, 1313 { 1314 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1315 "Counter": "2", 1316 "EventCode": "0xB7", 1317 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1318 "MSRIndex": "0x1A6", 1319 "MSRValue": "0x47FF", 1320 "SampleAfterValue": "100000", 1321 "UMask": "0x1" 1322 }, 1323 { 1324 "BriefDescription": "Offcore requests satisfied by a remote cache", 1325 "Counter": "2", 1326 "EventCode": "0xB7", 1327 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1328 "MSRIndex": "0x1A6", 1329 "MSRValue": "0x18FF", 1330 "SampleAfterValue": "100000", 1331 "UMask": "0x1" 1332 }, 1333 { 1334 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1335 "Counter": "2", 1336 "EventCode": "0xB7", 1337 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1338 "MSRIndex": "0x1A6", 1339 "MSRValue": "0x38FF", 1340 "SampleAfterValue": "100000", 1341 "UMask": "0x1" 1342 }, 1343 { 1344 "BriefDescription": "Offcore requests that HIT in a remote cache", 1345 "Counter": "2", 1346 "EventCode": "0xB7", 1347 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1348 "MSRIndex": "0x1A6", 1349 "MSRValue": "0x10FF", 1350 "SampleAfterValue": "100000", 1351 "UMask": "0x1" 1352 }, 1353 { 1354 "BriefDescription": "Offcore requests that HITM in a remote cache", 1355 "Counter": "2", 1356 "EventCode": "0xB7", 1357 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1358 "MSRIndex": "0x1A6", 1359 "MSRValue": "0x8FF", 1360 "SampleAfterValue": "100000", 1361 "UMask": "0x1" 1362 }, 1363 { 1364 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1365 "Counter": "2", 1366 "EventCode": "0xB7", 1367 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1368 "MSRIndex": "0x1A6", 1369 "MSRValue": "0x7F22", 1370 "SampleAfterValue": "100000", 1371 "UMask": "0x1" 1372 }, 1373 { 1374 "BriefDescription": "All offcore RFO requests", 1375 "Counter": "2", 1376 "EventCode": "0xB7", 1377 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1378 "MSRIndex": "0x1A6", 1379 "MSRValue": "0xFF22", 1380 "SampleAfterValue": "100000", 1381 "UMask": "0x1" 1382 }, 1383 { 1384 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1385 "Counter": "2", 1386 "EventCode": "0xB7", 1387 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1388 "MSRIndex": "0x1A6", 1389 "MSRValue": "0x8022", 1390 "SampleAfterValue": "100000", 1391 "UMask": "0x1" 1392 }, 1393 { 1394 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1395 "Counter": "2", 1396 "EventCode": "0xB7", 1397 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1398 "MSRIndex": "0x1A6", 1399 "MSRValue": "0x122", 1400 "SampleAfterValue": "100000", 1401 "UMask": "0x1" 1402 }, 1403 { 1404 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1405 "Counter": "2", 1406 "EventCode": "0xB7", 1407 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1408 "MSRIndex": "0x1A6", 1409 "MSRValue": "0x222", 1410 "SampleAfterValue": "100000", 1411 "UMask": "0x1" 1412 }, 1413 { 1414 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1415 "Counter": "2", 1416 "EventCode": "0xB7", 1417 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1418 "MSRIndex": "0x1A6", 1419 "MSRValue": "0x422", 1420 "SampleAfterValue": "100000", 1421 "UMask": "0x1" 1422 }, 1423 { 1424 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1425 "Counter": "2", 1426 "EventCode": "0xB7", 1427 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1428 "MSRIndex": "0x1A6", 1429 "MSRValue": "0x722", 1430 "SampleAfterValue": "100000", 1431 "UMask": "0x1" 1432 }, 1433 { 1434 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1435 "Counter": "2", 1436 "EventCode": "0xB7", 1437 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1438 "MSRIndex": "0x1A6", 1439 "MSRValue": "0x4722", 1440 "SampleAfterValue": "100000", 1441 "UMask": "0x1" 1442 }, 1443 { 1444 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1445 "Counter": "2", 1446 "EventCode": "0xB7", 1447 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1448 "MSRIndex": "0x1A6", 1449 "MSRValue": "0x1822", 1450 "SampleAfterValue": "100000", 1451 "UMask": "0x1" 1452 }, 1453 { 1454 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1455 "Counter": "2", 1456 "EventCode": "0xB7", 1457 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1458 "MSRIndex": "0x1A6", 1459 "MSRValue": "0x3822", 1460 "SampleAfterValue": "100000", 1461 "UMask": "0x1" 1462 }, 1463 { 1464 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1465 "Counter": "2", 1466 "EventCode": "0xB7", 1467 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1468 "MSRIndex": "0x1A6", 1469 "MSRValue": "0x1022", 1470 "SampleAfterValue": "100000", 1471 "UMask": "0x1" 1472 }, 1473 { 1474 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1475 "Counter": "2", 1476 "EventCode": "0xB7", 1477 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1478 "MSRIndex": "0x1A6", 1479 "MSRValue": "0x822", 1480 "SampleAfterValue": "100000", 1481 "UMask": "0x1" 1482 }, 1483 { 1484 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1485 "Counter": "2", 1486 "EventCode": "0xB7", 1487 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1488 "MSRIndex": "0x1A6", 1489 "MSRValue": "0x7F08", 1490 "SampleAfterValue": "100000", 1491 "UMask": "0x1" 1492 }, 1493 { 1494 "BriefDescription": "All offcore writebacks", 1495 "Counter": "2", 1496 "EventCode": "0xB7", 1497 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1498 "MSRIndex": "0x1A6", 1499 "MSRValue": "0xFF08", 1500 "SampleAfterValue": "100000", 1501 "UMask": "0x1" 1502 }, 1503 { 1504 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1505 "Counter": "2", 1506 "EventCode": "0xB7", 1507 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1508 "MSRIndex": "0x1A6", 1509 "MSRValue": "0x8008", 1510 "SampleAfterValue": "100000", 1511 "UMask": "0x1" 1512 }, 1513 { 1514 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1515 "Counter": "2", 1516 "EventCode": "0xB7", 1517 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1518 "MSRIndex": "0x1A6", 1519 "MSRValue": "0x108", 1520 "SampleAfterValue": "100000", 1521 "UMask": "0x1" 1522 }, 1523 { 1524 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1525 "Counter": "2", 1526 "EventCode": "0xB7", 1527 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1528 "MSRIndex": "0x1A6", 1529 "MSRValue": "0x408", 1530 "SampleAfterValue": "100000", 1531 "UMask": "0x1" 1532 }, 1533 { 1534 "BriefDescription": "Offcore writebacks to the LLC", 1535 "Counter": "2", 1536 "EventCode": "0xB7", 1537 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1538 "MSRIndex": "0x1A6", 1539 "MSRValue": "0x708", 1540 "SampleAfterValue": "100000", 1541 "UMask": "0x1" 1542 }, 1543 { 1544 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1545 "Counter": "2", 1546 "EventCode": "0xB7", 1547 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1548 "MSRIndex": "0x1A6", 1549 "MSRValue": "0x4708", 1550 "SampleAfterValue": "100000", 1551 "UMask": "0x1" 1552 }, 1553 { 1554 "BriefDescription": "Offcore writebacks to a remote cache", 1555 "Counter": "2", 1556 "EventCode": "0xB7", 1557 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1558 "MSRIndex": "0x1A6", 1559 "MSRValue": "0x1808", 1560 "SampleAfterValue": "100000", 1561 "UMask": "0x1" 1562 }, 1563 { 1564 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1565 "Counter": "2", 1566 "EventCode": "0xB7", 1567 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1568 "MSRIndex": "0x1A6", 1569 "MSRValue": "0x3808", 1570 "SampleAfterValue": "100000", 1571 "UMask": "0x1" 1572 }, 1573 { 1574 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1575 "Counter": "2", 1576 "EventCode": "0xB7", 1577 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1578 "MSRIndex": "0x1A6", 1579 "MSRValue": "0x1008", 1580 "SampleAfterValue": "100000", 1581 "UMask": "0x1" 1582 }, 1583 { 1584 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1585 "Counter": "2", 1586 "EventCode": "0xB7", 1587 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1588 "MSRIndex": "0x1A6", 1589 "MSRValue": "0x808", 1590 "SampleAfterValue": "100000", 1591 "UMask": "0x1" 1592 }, 1593 { 1594 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1595 "Counter": "2", 1596 "EventCode": "0xB7", 1597 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1598 "MSRIndex": "0x1A6", 1599 "MSRValue": "0x7F77", 1600 "SampleAfterValue": "100000", 1601 "UMask": "0x1" 1602 }, 1603 { 1604 "BriefDescription": "All offcore code or data read requests", 1605 "Counter": "2", 1606 "EventCode": "0xB7", 1607 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1608 "MSRIndex": "0x1A6", 1609 "MSRValue": "0xFF77", 1610 "SampleAfterValue": "100000", 1611 "UMask": "0x1" 1612 }, 1613 { 1614 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1615 "Counter": "2", 1616 "EventCode": "0xB7", 1617 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1618 "MSRIndex": "0x1A6", 1619 "MSRValue": "0x8077", 1620 "SampleAfterValue": "100000", 1621 "UMask": "0x1" 1622 }, 1623 { 1624 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1625 "Counter": "2", 1626 "EventCode": "0xB7", 1627 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1628 "MSRIndex": "0x1A6", 1629 "MSRValue": "0x177", 1630 "SampleAfterValue": "100000", 1631 "UMask": "0x1" 1632 }, 1633 { 1634 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1635 "Counter": "2", 1636 "EventCode": "0xB7", 1637 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1638 "MSRIndex": "0x1A6", 1639 "MSRValue": "0x277", 1640 "SampleAfterValue": "100000", 1641 "UMask": "0x1" 1642 }, 1643 { 1644 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1645 "Counter": "2", 1646 "EventCode": "0xB7", 1647 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1648 "MSRIndex": "0x1A6", 1649 "MSRValue": "0x477", 1650 "SampleAfterValue": "100000", 1651 "UMask": "0x1" 1652 }, 1653 { 1654 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1655 "Counter": "2", 1656 "EventCode": "0xB7", 1657 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1658 "MSRIndex": "0x1A6", 1659 "MSRValue": "0x777", 1660 "SampleAfterValue": "100000", 1661 "UMask": "0x1" 1662 }, 1663 { 1664 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1665 "Counter": "2", 1666 "EventCode": "0xB7", 1667 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1668 "MSRIndex": "0x1A6", 1669 "MSRValue": "0x4777", 1670 "SampleAfterValue": "100000", 1671 "UMask": "0x1" 1672 }, 1673 { 1674 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1675 "Counter": "2", 1676 "EventCode": "0xB7", 1677 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1678 "MSRIndex": "0x1A6", 1679 "MSRValue": "0x1877", 1680 "SampleAfterValue": "100000", 1681 "UMask": "0x1" 1682 }, 1683 { 1684 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1685 "Counter": "2", 1686 "EventCode": "0xB7", 1687 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1688 "MSRIndex": "0x1A6", 1689 "MSRValue": "0x3877", 1690 "SampleAfterValue": "100000", 1691 "UMask": "0x1" 1692 }, 1693 { 1694 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1695 "Counter": "2", 1696 "EventCode": "0xB7", 1697 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1698 "MSRIndex": "0x1A6", 1699 "MSRValue": "0x1077", 1700 "SampleAfterValue": "100000", 1701 "UMask": "0x1" 1702 }, 1703 { 1704 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1705 "Counter": "2", 1706 "EventCode": "0xB7", 1707 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1708 "MSRIndex": "0x1A6", 1709 "MSRValue": "0x877", 1710 "SampleAfterValue": "100000", 1711 "UMask": "0x1" 1712 }, 1713 { 1714 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1715 "Counter": "2", 1716 "EventCode": "0xB7", 1717 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1718 "MSRIndex": "0x1A6", 1719 "MSRValue": "0x7F33", 1720 "SampleAfterValue": "100000", 1721 "UMask": "0x1" 1722 }, 1723 { 1724 "BriefDescription": "Offcore request = all data, response = any location", 1725 "Counter": "2", 1726 "EventCode": "0xB7", 1727 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1728 "MSRIndex": "0x1A6", 1729 "MSRValue": "0xFF33", 1730 "SampleAfterValue": "100000", 1731 "UMask": "0x1" 1732 }, 1733 { 1734 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1735 "Counter": "2", 1736 "EventCode": "0xB7", 1737 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1738 "MSRIndex": "0x1A6", 1739 "MSRValue": "0x8033", 1740 "SampleAfterValue": "100000", 1741 "UMask": "0x1" 1742 }, 1743 { 1744 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1745 "Counter": "2", 1746 "EventCode": "0xB7", 1747 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1748 "MSRIndex": "0x1A6", 1749 "MSRValue": "0x133", 1750 "SampleAfterValue": "100000", 1751 "UMask": "0x1" 1752 }, 1753 { 1754 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1755 "Counter": "2", 1756 "EventCode": "0xB7", 1757 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1758 "MSRIndex": "0x1A6", 1759 "MSRValue": "0x233", 1760 "SampleAfterValue": "100000", 1761 "UMask": "0x1" 1762 }, 1763 { 1764 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1765 "Counter": "2", 1766 "EventCode": "0xB7", 1767 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1768 "MSRIndex": "0x1A6", 1769 "MSRValue": "0x433", 1770 "SampleAfterValue": "100000", 1771 "UMask": "0x1" 1772 }, 1773 { 1774 "BriefDescription": "Offcore request = all data, response = local cache", 1775 "Counter": "2", 1776 "EventCode": "0xB7", 1777 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1778 "MSRIndex": "0x1A6", 1779 "MSRValue": "0x733", 1780 "SampleAfterValue": "100000", 1781 "UMask": "0x1" 1782 }, 1783 { 1784 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1785 "Counter": "2", 1786 "EventCode": "0xB7", 1787 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1788 "MSRIndex": "0x1A6", 1789 "MSRValue": "0x4733", 1790 "SampleAfterValue": "100000", 1791 "UMask": "0x1" 1792 }, 1793 { 1794 "BriefDescription": "Offcore request = all data, response = remote cache", 1795 "Counter": "2", 1796 "EventCode": "0xB7", 1797 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1798 "MSRIndex": "0x1A6", 1799 "MSRValue": "0x1833", 1800 "SampleAfterValue": "100000", 1801 "UMask": "0x1" 1802 }, 1803 { 1804 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1805 "Counter": "2", 1806 "EventCode": "0xB7", 1807 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1808 "MSRIndex": "0x1A6", 1809 "MSRValue": "0x3833", 1810 "SampleAfterValue": "100000", 1811 "UMask": "0x1" 1812 }, 1813 { 1814 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1815 "Counter": "2", 1816 "EventCode": "0xB7", 1817 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1818 "MSRIndex": "0x1A6", 1819 "MSRValue": "0x1033", 1820 "SampleAfterValue": "100000", 1821 "UMask": "0x1" 1822 }, 1823 { 1824 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1825 "Counter": "2", 1826 "EventCode": "0xB7", 1827 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1828 "MSRIndex": "0x1A6", 1829 "MSRValue": "0x833", 1830 "SampleAfterValue": "100000", 1831 "UMask": "0x1" 1832 }, 1833 { 1834 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1835 "Counter": "2", 1836 "EventCode": "0xB7", 1837 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1838 "MSRIndex": "0x1A6", 1839 "MSRValue": "0x7F03", 1840 "SampleAfterValue": "100000", 1841 "UMask": "0x1" 1842 }, 1843 { 1844 "BriefDescription": "All offcore demand data requests", 1845 "Counter": "2", 1846 "EventCode": "0xB7", 1847 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1848 "MSRIndex": "0x1A6", 1849 "MSRValue": "0xFF03", 1850 "SampleAfterValue": "100000", 1851 "UMask": "0x1" 1852 }, 1853 { 1854 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1855 "Counter": "2", 1856 "EventCode": "0xB7", 1857 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1858 "MSRIndex": "0x1A6", 1859 "MSRValue": "0x8003", 1860 "SampleAfterValue": "100000", 1861 "UMask": "0x1" 1862 }, 1863 { 1864 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1865 "Counter": "2", 1866 "EventCode": "0xB7", 1867 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1868 "MSRIndex": "0x1A6", 1869 "MSRValue": "0x103", 1870 "SampleAfterValue": "100000", 1871 "UMask": "0x1" 1872 }, 1873 { 1874 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1875 "Counter": "2", 1876 "EventCode": "0xB7", 1877 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1878 "MSRIndex": "0x1A6", 1879 "MSRValue": "0x203", 1880 "SampleAfterValue": "100000", 1881 "UMask": "0x1" 1882 }, 1883 { 1884 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1885 "Counter": "2", 1886 "EventCode": "0xB7", 1887 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1888 "MSRIndex": "0x1A6", 1889 "MSRValue": "0x403", 1890 "SampleAfterValue": "100000", 1891 "UMask": "0x1" 1892 }, 1893 { 1894 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1895 "Counter": "2", 1896 "EventCode": "0xB7", 1897 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1898 "MSRIndex": "0x1A6", 1899 "MSRValue": "0x703", 1900 "SampleAfterValue": "100000", 1901 "UMask": "0x1" 1902 }, 1903 { 1904 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1905 "Counter": "2", 1906 "EventCode": "0xB7", 1907 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1908 "MSRIndex": "0x1A6", 1909 "MSRValue": "0x4703", 1910 "SampleAfterValue": "100000", 1911 "UMask": "0x1" 1912 }, 1913 { 1914 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1915 "Counter": "2", 1916 "EventCode": "0xB7", 1917 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1918 "MSRIndex": "0x1A6", 1919 "MSRValue": "0x1803", 1920 "SampleAfterValue": "100000", 1921 "UMask": "0x1" 1922 }, 1923 { 1924 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1925 "Counter": "2", 1926 "EventCode": "0xB7", 1927 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1928 "MSRIndex": "0x1A6", 1929 "MSRValue": "0x3803", 1930 "SampleAfterValue": "100000", 1931 "UMask": "0x1" 1932 }, 1933 { 1934 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1935 "Counter": "2", 1936 "EventCode": "0xB7", 1937 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1938 "MSRIndex": "0x1A6", 1939 "MSRValue": "0x1003", 1940 "SampleAfterValue": "100000", 1941 "UMask": "0x1" 1942 }, 1943 { 1944 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1945 "Counter": "2", 1946 "EventCode": "0xB7", 1947 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1948 "MSRIndex": "0x1A6", 1949 "MSRValue": "0x803", 1950 "SampleAfterValue": "100000", 1951 "UMask": "0x1" 1952 }, 1953 { 1954 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1955 "Counter": "2", 1956 "EventCode": "0xB7", 1957 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1958 "MSRIndex": "0x1A6", 1959 "MSRValue": "0x7F01", 1960 "SampleAfterValue": "100000", 1961 "UMask": "0x1" 1962 }, 1963 { 1964 "BriefDescription": "All offcore demand data reads", 1965 "Counter": "2", 1966 "EventCode": "0xB7", 1967 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1968 "MSRIndex": "0x1A6", 1969 "MSRValue": "0xFF01", 1970 "SampleAfterValue": "100000", 1971 "UMask": "0x1" 1972 }, 1973 { 1974 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1975 "Counter": "2", 1976 "EventCode": "0xB7", 1977 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1978 "MSRIndex": "0x1A6", 1979 "MSRValue": "0x8001", 1980 "SampleAfterValue": "100000", 1981 "UMask": "0x1" 1982 }, 1983 { 1984 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1985 "Counter": "2", 1986 "EventCode": "0xB7", 1987 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1988 "MSRIndex": "0x1A6", 1989 "MSRValue": "0x101", 1990 "SampleAfterValue": "100000", 1991 "UMask": "0x1" 1992 }, 1993 { 1994 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1995 "Counter": "2", 1996 "EventCode": "0xB7", 1997 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1998 "MSRIndex": "0x1A6", 1999 "MSRValue": "0x201", 2000 "SampleAfterValue": "100000", 2001 "UMask": "0x1" 2002 }, 2003 { 2004 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 2005 "Counter": "2", 2006 "EventCode": "0xB7", 2007 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2008 "MSRIndex": "0x1A6", 2009 "MSRValue": "0x401", 2010 "SampleAfterValue": "100000", 2011 "UMask": "0x1" 2012 }, 2013 { 2014 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 2015 "Counter": "2", 2016 "EventCode": "0xB7", 2017 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 2018 "MSRIndex": "0x1A6", 2019 "MSRValue": "0x701", 2020 "SampleAfterValue": "100000", 2021 "UMask": "0x1" 2022 }, 2023 { 2024 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 2025 "Counter": "2", 2026 "EventCode": "0xB7", 2027 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 2028 "MSRIndex": "0x1A6", 2029 "MSRValue": "0x4701", 2030 "SampleAfterValue": "100000", 2031 "UMask": "0x1" 2032 }, 2033 { 2034 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2035 "Counter": "2", 2036 "EventCode": "0xB7", 2037 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2038 "MSRIndex": "0x1A6", 2039 "MSRValue": "0x1801", 2040 "SampleAfterValue": "100000", 2041 "UMask": "0x1" 2042 }, 2043 { 2044 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2045 "Counter": "2", 2046 "EventCode": "0xB7", 2047 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2048 "MSRIndex": "0x1A6", 2049 "MSRValue": "0x3801", 2050 "SampleAfterValue": "100000", 2051 "UMask": "0x1" 2052 }, 2053 { 2054 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2055 "Counter": "2", 2056 "EventCode": "0xB7", 2057 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2058 "MSRIndex": "0x1A6", 2059 "MSRValue": "0x1001", 2060 "SampleAfterValue": "100000", 2061 "UMask": "0x1" 2062 }, 2063 { 2064 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2065 "Counter": "2", 2066 "EventCode": "0xB7", 2067 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2068 "MSRIndex": "0x1A6", 2069 "MSRValue": "0x801", 2070 "SampleAfterValue": "100000", 2071 "UMask": "0x1" 2072 }, 2073 { 2074 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2075 "Counter": "2", 2076 "EventCode": "0xB7", 2077 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2078 "MSRIndex": "0x1A6", 2079 "MSRValue": "0x7F04", 2080 "SampleAfterValue": "100000", 2081 "UMask": "0x1" 2082 }, 2083 { 2084 "BriefDescription": "All offcore demand code reads", 2085 "Counter": "2", 2086 "EventCode": "0xB7", 2087 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2088 "MSRIndex": "0x1A6", 2089 "MSRValue": "0xFF04", 2090 "SampleAfterValue": "100000", 2091 "UMask": "0x1" 2092 }, 2093 { 2094 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2095 "Counter": "2", 2096 "EventCode": "0xB7", 2097 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2098 "MSRIndex": "0x1A6", 2099 "MSRValue": "0x8004", 2100 "SampleAfterValue": "100000", 2101 "UMask": "0x1" 2102 }, 2103 { 2104 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2105 "Counter": "2", 2106 "EventCode": "0xB7", 2107 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2108 "MSRIndex": "0x1A6", 2109 "MSRValue": "0x104", 2110 "SampleAfterValue": "100000", 2111 "UMask": "0x1" 2112 }, 2113 { 2114 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2115 "Counter": "2", 2116 "EventCode": "0xB7", 2117 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2118 "MSRIndex": "0x1A6", 2119 "MSRValue": "0x204", 2120 "SampleAfterValue": "100000", 2121 "UMask": "0x1" 2122 }, 2123 { 2124 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2125 "Counter": "2", 2126 "EventCode": "0xB7", 2127 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2128 "MSRIndex": "0x1A6", 2129 "MSRValue": "0x404", 2130 "SampleAfterValue": "100000", 2131 "UMask": "0x1" 2132 }, 2133 { 2134 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2135 "Counter": "2", 2136 "EventCode": "0xB7", 2137 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2138 "MSRIndex": "0x1A6", 2139 "MSRValue": "0x704", 2140 "SampleAfterValue": "100000", 2141 "UMask": "0x1" 2142 }, 2143 { 2144 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2145 "Counter": "2", 2146 "EventCode": "0xB7", 2147 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2148 "MSRIndex": "0x1A6", 2149 "MSRValue": "0x4704", 2150 "SampleAfterValue": "100000", 2151 "UMask": "0x1" 2152 }, 2153 { 2154 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2155 "Counter": "2", 2156 "EventCode": "0xB7", 2157 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2158 "MSRIndex": "0x1A6", 2159 "MSRValue": "0x1804", 2160 "SampleAfterValue": "100000", 2161 "UMask": "0x1" 2162 }, 2163 { 2164 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2165 "Counter": "2", 2166 "EventCode": "0xB7", 2167 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2168 "MSRIndex": "0x1A6", 2169 "MSRValue": "0x3804", 2170 "SampleAfterValue": "100000", 2171 "UMask": "0x1" 2172 }, 2173 { 2174 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2175 "Counter": "2", 2176 "EventCode": "0xB7", 2177 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2178 "MSRIndex": "0x1A6", 2179 "MSRValue": "0x1004", 2180 "SampleAfterValue": "100000", 2181 "UMask": "0x1" 2182 }, 2183 { 2184 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2185 "Counter": "2", 2186 "EventCode": "0xB7", 2187 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2188 "MSRIndex": "0x1A6", 2189 "MSRValue": "0x804", 2190 "SampleAfterValue": "100000", 2191 "UMask": "0x1" 2192 }, 2193 { 2194 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2195 "Counter": "2", 2196 "EventCode": "0xB7", 2197 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2198 "MSRIndex": "0x1A6", 2199 "MSRValue": "0x7F02", 2200 "SampleAfterValue": "100000", 2201 "UMask": "0x1" 2202 }, 2203 { 2204 "BriefDescription": "All offcore demand RFO requests", 2205 "Counter": "2", 2206 "EventCode": "0xB7", 2207 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2208 "MSRIndex": "0x1A6", 2209 "MSRValue": "0xFF02", 2210 "SampleAfterValue": "100000", 2211 "UMask": "0x1" 2212 }, 2213 { 2214 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2215 "Counter": "2", 2216 "EventCode": "0xB7", 2217 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2218 "MSRIndex": "0x1A6", 2219 "MSRValue": "0x8002", 2220 "SampleAfterValue": "100000", 2221 "UMask": "0x1" 2222 }, 2223 { 2224 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2225 "Counter": "2", 2226 "EventCode": "0xB7", 2227 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2228 "MSRIndex": "0x1A6", 2229 "MSRValue": "0x102", 2230 "SampleAfterValue": "100000", 2231 "UMask": "0x1" 2232 }, 2233 { 2234 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2235 "Counter": "2", 2236 "EventCode": "0xB7", 2237 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2238 "MSRIndex": "0x1A6", 2239 "MSRValue": "0x202", 2240 "SampleAfterValue": "100000", 2241 "UMask": "0x1" 2242 }, 2243 { 2244 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2245 "Counter": "2", 2246 "EventCode": "0xB7", 2247 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2248 "MSRIndex": "0x1A6", 2249 "MSRValue": "0x402", 2250 "SampleAfterValue": "100000", 2251 "UMask": "0x1" 2252 }, 2253 { 2254 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2255 "Counter": "2", 2256 "EventCode": "0xB7", 2257 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2258 "MSRIndex": "0x1A6", 2259 "MSRValue": "0x702", 2260 "SampleAfterValue": "100000", 2261 "UMask": "0x1" 2262 }, 2263 { 2264 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2265 "Counter": "2", 2266 "EventCode": "0xB7", 2267 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2268 "MSRIndex": "0x1A6", 2269 "MSRValue": "0x4702", 2270 "SampleAfterValue": "100000", 2271 "UMask": "0x1" 2272 }, 2273 { 2274 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2275 "Counter": "2", 2276 "EventCode": "0xB7", 2277 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2278 "MSRIndex": "0x1A6", 2279 "MSRValue": "0x1802", 2280 "SampleAfterValue": "100000", 2281 "UMask": "0x1" 2282 }, 2283 { 2284 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2285 "Counter": "2", 2286 "EventCode": "0xB7", 2287 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2288 "MSRIndex": "0x1A6", 2289 "MSRValue": "0x3802", 2290 "SampleAfterValue": "100000", 2291 "UMask": "0x1" 2292 }, 2293 { 2294 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2295 "Counter": "2", 2296 "EventCode": "0xB7", 2297 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2298 "MSRIndex": "0x1A6", 2299 "MSRValue": "0x1002", 2300 "SampleAfterValue": "100000", 2301 "UMask": "0x1" 2302 }, 2303 { 2304 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2305 "Counter": "2", 2306 "EventCode": "0xB7", 2307 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2308 "MSRIndex": "0x1A6", 2309 "MSRValue": "0x802", 2310 "SampleAfterValue": "100000", 2311 "UMask": "0x1" 2312 }, 2313 { 2314 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2315 "Counter": "2", 2316 "EventCode": "0xB7", 2317 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2318 "MSRIndex": "0x1A6", 2319 "MSRValue": "0x7F80", 2320 "SampleAfterValue": "100000", 2321 "UMask": "0x1" 2322 }, 2323 { 2324 "BriefDescription": "All offcore other requests", 2325 "Counter": "2", 2326 "EventCode": "0xB7", 2327 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2328 "MSRIndex": "0x1A6", 2329 "MSRValue": "0xFF80", 2330 "SampleAfterValue": "100000", 2331 "UMask": "0x1" 2332 }, 2333 { 2334 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2335 "Counter": "2", 2336 "EventCode": "0xB7", 2337 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2338 "MSRIndex": "0x1A6", 2339 "MSRValue": "0x8080", 2340 "SampleAfterValue": "100000", 2341 "UMask": "0x1" 2342 }, 2343 { 2344 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2345 "Counter": "2", 2346 "EventCode": "0xB7", 2347 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2348 "MSRIndex": "0x1A6", 2349 "MSRValue": "0x180", 2350 "SampleAfterValue": "100000", 2351 "UMask": "0x1" 2352 }, 2353 { 2354 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2355 "Counter": "2", 2356 "EventCode": "0xB7", 2357 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2358 "MSRIndex": "0x1A6", 2359 "MSRValue": "0x280", 2360 "SampleAfterValue": "100000", 2361 "UMask": "0x1" 2362 }, 2363 { 2364 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2365 "Counter": "2", 2366 "EventCode": "0xB7", 2367 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2368 "MSRIndex": "0x1A6", 2369 "MSRValue": "0x480", 2370 "SampleAfterValue": "100000", 2371 "UMask": "0x1" 2372 }, 2373 { 2374 "BriefDescription": "Offcore other requests satisfied by the LLC", 2375 "Counter": "2", 2376 "EventCode": "0xB7", 2377 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2378 "MSRIndex": "0x1A6", 2379 "MSRValue": "0x780", 2380 "SampleAfterValue": "100000", 2381 "UMask": "0x1" 2382 }, 2383 { 2384 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2385 "Counter": "2", 2386 "EventCode": "0xB7", 2387 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2388 "MSRIndex": "0x1A6", 2389 "MSRValue": "0x4780", 2390 "SampleAfterValue": "100000", 2391 "UMask": "0x1" 2392 }, 2393 { 2394 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2395 "Counter": "2", 2396 "EventCode": "0xB7", 2397 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2398 "MSRIndex": "0x1A6", 2399 "MSRValue": "0x1880", 2400 "SampleAfterValue": "100000", 2401 "UMask": "0x1" 2402 }, 2403 { 2404 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2405 "Counter": "2", 2406 "EventCode": "0xB7", 2407 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2408 "MSRIndex": "0x1A6", 2409 "MSRValue": "0x3880", 2410 "SampleAfterValue": "100000", 2411 "UMask": "0x1" 2412 }, 2413 { 2414 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2415 "Counter": "2", 2416 "EventCode": "0xB7", 2417 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2418 "MSRIndex": "0x1A6", 2419 "MSRValue": "0x1080", 2420 "SampleAfterValue": "100000", 2421 "UMask": "0x1" 2422 }, 2423 { 2424 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2425 "Counter": "2", 2426 "EventCode": "0xB7", 2427 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2428 "MSRIndex": "0x1A6", 2429 "MSRValue": "0x880", 2430 "SampleAfterValue": "100000", 2431 "UMask": "0x1" 2432 }, 2433 { 2434 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2435 "Counter": "2", 2436 "EventCode": "0xB7", 2437 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2438 "MSRIndex": "0x1A6", 2439 "MSRValue": "0x7F30", 2440 "SampleAfterValue": "100000", 2441 "UMask": "0x1" 2442 }, 2443 { 2444 "BriefDescription": "All offcore prefetch data requests", 2445 "Counter": "2", 2446 "EventCode": "0xB7", 2447 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2448 "MSRIndex": "0x1A6", 2449 "MSRValue": "0xFF30", 2450 "SampleAfterValue": "100000", 2451 "UMask": "0x1" 2452 }, 2453 { 2454 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2455 "Counter": "2", 2456 "EventCode": "0xB7", 2457 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2458 "MSRIndex": "0x1A6", 2459 "MSRValue": "0x8030", 2460 "SampleAfterValue": "100000", 2461 "UMask": "0x1" 2462 }, 2463 { 2464 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2465 "Counter": "2", 2466 "EventCode": "0xB7", 2467 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2468 "MSRIndex": "0x1A6", 2469 "MSRValue": "0x130", 2470 "SampleAfterValue": "100000", 2471 "UMask": "0x1" 2472 }, 2473 { 2474 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2475 "Counter": "2", 2476 "EventCode": "0xB7", 2477 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2478 "MSRIndex": "0x1A6", 2479 "MSRValue": "0x230", 2480 "SampleAfterValue": "100000", 2481 "UMask": "0x1" 2482 }, 2483 { 2484 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2485 "Counter": "2", 2486 "EventCode": "0xB7", 2487 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2488 "MSRIndex": "0x1A6", 2489 "MSRValue": "0x430", 2490 "SampleAfterValue": "100000", 2491 "UMask": "0x1" 2492 }, 2493 { 2494 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2495 "Counter": "2", 2496 "EventCode": "0xB7", 2497 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2498 "MSRIndex": "0x1A6", 2499 "MSRValue": "0x730", 2500 "SampleAfterValue": "100000", 2501 "UMask": "0x1" 2502 }, 2503 { 2504 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2505 "Counter": "2", 2506 "EventCode": "0xB7", 2507 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2508 "MSRIndex": "0x1A6", 2509 "MSRValue": "0x4730", 2510 "SampleAfterValue": "100000", 2511 "UMask": "0x1" 2512 }, 2513 { 2514 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2515 "Counter": "2", 2516 "EventCode": "0xB7", 2517 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2518 "MSRIndex": "0x1A6", 2519 "MSRValue": "0x1830", 2520 "SampleAfterValue": "100000", 2521 "UMask": "0x1" 2522 }, 2523 { 2524 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2525 "Counter": "2", 2526 "EventCode": "0xB7", 2527 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2528 "MSRIndex": "0x1A6", 2529 "MSRValue": "0x3830", 2530 "SampleAfterValue": "100000", 2531 "UMask": "0x1" 2532 }, 2533 { 2534 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2535 "Counter": "2", 2536 "EventCode": "0xB7", 2537 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2538 "MSRIndex": "0x1A6", 2539 "MSRValue": "0x1030", 2540 "SampleAfterValue": "100000", 2541 "UMask": "0x1" 2542 }, 2543 { 2544 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2545 "Counter": "2", 2546 "EventCode": "0xB7", 2547 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2548 "MSRIndex": "0x1A6", 2549 "MSRValue": "0x830", 2550 "SampleAfterValue": "100000", 2551 "UMask": "0x1" 2552 }, 2553 { 2554 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2555 "Counter": "2", 2556 "EventCode": "0xB7", 2557 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2558 "MSRIndex": "0x1A6", 2559 "MSRValue": "0x7F10", 2560 "SampleAfterValue": "100000", 2561 "UMask": "0x1" 2562 }, 2563 { 2564 "BriefDescription": "All offcore prefetch data reads", 2565 "Counter": "2", 2566 "EventCode": "0xB7", 2567 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2568 "MSRIndex": "0x1A6", 2569 "MSRValue": "0xFF10", 2570 "SampleAfterValue": "100000", 2571 "UMask": "0x1" 2572 }, 2573 { 2574 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2575 "Counter": "2", 2576 "EventCode": "0xB7", 2577 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2578 "MSRIndex": "0x1A6", 2579 "MSRValue": "0x8010", 2580 "SampleAfterValue": "100000", 2581 "UMask": "0x1" 2582 }, 2583 { 2584 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2585 "Counter": "2", 2586 "EventCode": "0xB7", 2587 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2588 "MSRIndex": "0x1A6", 2589 "MSRValue": "0x110", 2590 "SampleAfterValue": "100000", 2591 "UMask": "0x1" 2592 }, 2593 { 2594 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2595 "Counter": "2", 2596 "EventCode": "0xB7", 2597 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2598 "MSRIndex": "0x1A6", 2599 "MSRValue": "0x210", 2600 "SampleAfterValue": "100000", 2601 "UMask": "0x1" 2602 }, 2603 { 2604 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2605 "Counter": "2", 2606 "EventCode": "0xB7", 2607 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2608 "MSRIndex": "0x1A6", 2609 "MSRValue": "0x410", 2610 "SampleAfterValue": "100000", 2611 "UMask": "0x1" 2612 }, 2613 { 2614 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2615 "Counter": "2", 2616 "EventCode": "0xB7", 2617 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2618 "MSRIndex": "0x1A6", 2619 "MSRValue": "0x710", 2620 "SampleAfterValue": "100000", 2621 "UMask": "0x1" 2622 }, 2623 { 2624 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2625 "Counter": "2", 2626 "EventCode": "0xB7", 2627 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2628 "MSRIndex": "0x1A6", 2629 "MSRValue": "0x4710", 2630 "SampleAfterValue": "100000", 2631 "UMask": "0x1" 2632 }, 2633 { 2634 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2635 "Counter": "2", 2636 "EventCode": "0xB7", 2637 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2638 "MSRIndex": "0x1A6", 2639 "MSRValue": "0x1810", 2640 "SampleAfterValue": "100000", 2641 "UMask": "0x1" 2642 }, 2643 { 2644 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2645 "Counter": "2", 2646 "EventCode": "0xB7", 2647 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2648 "MSRIndex": "0x1A6", 2649 "MSRValue": "0x3810", 2650 "SampleAfterValue": "100000", 2651 "UMask": "0x1" 2652 }, 2653 { 2654 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2655 "Counter": "2", 2656 "EventCode": "0xB7", 2657 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2658 "MSRIndex": "0x1A6", 2659 "MSRValue": "0x1010", 2660 "SampleAfterValue": "100000", 2661 "UMask": "0x1" 2662 }, 2663 { 2664 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2665 "Counter": "2", 2666 "EventCode": "0xB7", 2667 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2668 "MSRIndex": "0x1A6", 2669 "MSRValue": "0x810", 2670 "SampleAfterValue": "100000", 2671 "UMask": "0x1" 2672 }, 2673 { 2674 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2675 "Counter": "2", 2676 "EventCode": "0xB7", 2677 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2678 "MSRIndex": "0x1A6", 2679 "MSRValue": "0x7F40", 2680 "SampleAfterValue": "100000", 2681 "UMask": "0x1" 2682 }, 2683 { 2684 "BriefDescription": "All offcore prefetch code reads", 2685 "Counter": "2", 2686 "EventCode": "0xB7", 2687 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2688 "MSRIndex": "0x1A6", 2689 "MSRValue": "0xFF40", 2690 "SampleAfterValue": "100000", 2691 "UMask": "0x1" 2692 }, 2693 { 2694 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2695 "Counter": "2", 2696 "EventCode": "0xB7", 2697 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2698 "MSRIndex": "0x1A6", 2699 "MSRValue": "0x8040", 2700 "SampleAfterValue": "100000", 2701 "UMask": "0x1" 2702 }, 2703 { 2704 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2705 "Counter": "2", 2706 "EventCode": "0xB7", 2707 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2708 "MSRIndex": "0x1A6", 2709 "MSRValue": "0x140", 2710 "SampleAfterValue": "100000", 2711 "UMask": "0x1" 2712 }, 2713 { 2714 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2715 "Counter": "2", 2716 "EventCode": "0xB7", 2717 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2718 "MSRIndex": "0x1A6", 2719 "MSRValue": "0x240", 2720 "SampleAfterValue": "100000", 2721 "UMask": "0x1" 2722 }, 2723 { 2724 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2725 "Counter": "2", 2726 "EventCode": "0xB7", 2727 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2728 "MSRIndex": "0x1A6", 2729 "MSRValue": "0x440", 2730 "SampleAfterValue": "100000", 2731 "UMask": "0x1" 2732 }, 2733 { 2734 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2735 "Counter": "2", 2736 "EventCode": "0xB7", 2737 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2738 "MSRIndex": "0x1A6", 2739 "MSRValue": "0x740", 2740 "SampleAfterValue": "100000", 2741 "UMask": "0x1" 2742 }, 2743 { 2744 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2745 "Counter": "2", 2746 "EventCode": "0xB7", 2747 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2748 "MSRIndex": "0x1A6", 2749 "MSRValue": "0x4740", 2750 "SampleAfterValue": "100000", 2751 "UMask": "0x1" 2752 }, 2753 { 2754 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2755 "Counter": "2", 2756 "EventCode": "0xB7", 2757 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2758 "MSRIndex": "0x1A6", 2759 "MSRValue": "0x1840", 2760 "SampleAfterValue": "100000", 2761 "UMask": "0x1" 2762 }, 2763 { 2764 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2765 "Counter": "2", 2766 "EventCode": "0xB7", 2767 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2768 "MSRIndex": "0x1A6", 2769 "MSRValue": "0x3840", 2770 "SampleAfterValue": "100000", 2771 "UMask": "0x1" 2772 }, 2773 { 2774 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2775 "Counter": "2", 2776 "EventCode": "0xB7", 2777 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2778 "MSRIndex": "0x1A6", 2779 "MSRValue": "0x1040", 2780 "SampleAfterValue": "100000", 2781 "UMask": "0x1" 2782 }, 2783 { 2784 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2785 "Counter": "2", 2786 "EventCode": "0xB7", 2787 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2788 "MSRIndex": "0x1A6", 2789 "MSRValue": "0x840", 2790 "SampleAfterValue": "100000", 2791 "UMask": "0x1" 2792 }, 2793 { 2794 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2795 "Counter": "2", 2796 "EventCode": "0xB7", 2797 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2798 "MSRIndex": "0x1A6", 2799 "MSRValue": "0x7F20", 2800 "SampleAfterValue": "100000", 2801 "UMask": "0x1" 2802 }, 2803 { 2804 "BriefDescription": "All offcore prefetch RFO requests", 2805 "Counter": "2", 2806 "EventCode": "0xB7", 2807 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2808 "MSRIndex": "0x1A6", 2809 "MSRValue": "0xFF20", 2810 "SampleAfterValue": "100000", 2811 "UMask": "0x1" 2812 }, 2813 { 2814 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2815 "Counter": "2", 2816 "EventCode": "0xB7", 2817 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2818 "MSRIndex": "0x1A6", 2819 "MSRValue": "0x8020", 2820 "SampleAfterValue": "100000", 2821 "UMask": "0x1" 2822 }, 2823 { 2824 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2825 "Counter": "2", 2826 "EventCode": "0xB7", 2827 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2828 "MSRIndex": "0x1A6", 2829 "MSRValue": "0x120", 2830 "SampleAfterValue": "100000", 2831 "UMask": "0x1" 2832 }, 2833 { 2834 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2835 "Counter": "2", 2836 "EventCode": "0xB7", 2837 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2838 "MSRIndex": "0x1A6", 2839 "MSRValue": "0x220", 2840 "SampleAfterValue": "100000", 2841 "UMask": "0x1" 2842 }, 2843 { 2844 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2845 "Counter": "2", 2846 "EventCode": "0xB7", 2847 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2848 "MSRIndex": "0x1A6", 2849 "MSRValue": "0x420", 2850 "SampleAfterValue": "100000", 2851 "UMask": "0x1" 2852 }, 2853 { 2854 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2855 "Counter": "2", 2856 "EventCode": "0xB7", 2857 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2858 "MSRIndex": "0x1A6", 2859 "MSRValue": "0x720", 2860 "SampleAfterValue": "100000", 2861 "UMask": "0x1" 2862 }, 2863 { 2864 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2865 "Counter": "2", 2866 "EventCode": "0xB7", 2867 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2868 "MSRIndex": "0x1A6", 2869 "MSRValue": "0x4720", 2870 "SampleAfterValue": "100000", 2871 "UMask": "0x1" 2872 }, 2873 { 2874 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2875 "Counter": "2", 2876 "EventCode": "0xB7", 2877 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2878 "MSRIndex": "0x1A6", 2879 "MSRValue": "0x1820", 2880 "SampleAfterValue": "100000", 2881 "UMask": "0x1" 2882 }, 2883 { 2884 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2885 "Counter": "2", 2886 "EventCode": "0xB7", 2887 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2888 "MSRIndex": "0x1A6", 2889 "MSRValue": "0x3820", 2890 "SampleAfterValue": "100000", 2891 "UMask": "0x1" 2892 }, 2893 { 2894 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2895 "Counter": "2", 2896 "EventCode": "0xB7", 2897 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2898 "MSRIndex": "0x1A6", 2899 "MSRValue": "0x1020", 2900 "SampleAfterValue": "100000", 2901 "UMask": "0x1" 2902 }, 2903 { 2904 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2905 "Counter": "2", 2906 "EventCode": "0xB7", 2907 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2908 "MSRIndex": "0x1A6", 2909 "MSRValue": "0x820", 2910 "SampleAfterValue": "100000", 2911 "UMask": "0x1" 2912 }, 2913 { 2914 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2915 "Counter": "2", 2916 "EventCode": "0xB7", 2917 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2918 "MSRIndex": "0x1A6", 2919 "MSRValue": "0x7F70", 2920 "SampleAfterValue": "100000", 2921 "UMask": "0x1" 2922 }, 2923 { 2924 "BriefDescription": "All offcore prefetch requests", 2925 "Counter": "2", 2926 "EventCode": "0xB7", 2927 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2928 "MSRIndex": "0x1A6", 2929 "MSRValue": "0xFF70", 2930 "SampleAfterValue": "100000", 2931 "UMask": "0x1" 2932 }, 2933 { 2934 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2935 "Counter": "2", 2936 "EventCode": "0xB7", 2937 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2938 "MSRIndex": "0x1A6", 2939 "MSRValue": "0x8070", 2940 "SampleAfterValue": "100000", 2941 "UMask": "0x1" 2942 }, 2943 { 2944 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2945 "Counter": "2", 2946 "EventCode": "0xB7", 2947 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2948 "MSRIndex": "0x1A6", 2949 "MSRValue": "0x170", 2950 "SampleAfterValue": "100000", 2951 "UMask": "0x1" 2952 }, 2953 { 2954 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2955 "Counter": "2", 2956 "EventCode": "0xB7", 2957 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2958 "MSRIndex": "0x1A6", 2959 "MSRValue": "0x270", 2960 "SampleAfterValue": "100000", 2961 "UMask": "0x1" 2962 }, 2963 { 2964 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2965 "Counter": "2", 2966 "EventCode": "0xB7", 2967 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2968 "MSRIndex": "0x1A6", 2969 "MSRValue": "0x470", 2970 "SampleAfterValue": "100000", 2971 "UMask": "0x1" 2972 }, 2973 { 2974 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2975 "Counter": "2", 2976 "EventCode": "0xB7", 2977 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2978 "MSRIndex": "0x1A6", 2979 "MSRValue": "0x770", 2980 "SampleAfterValue": "100000", 2981 "UMask": "0x1" 2982 }, 2983 { 2984 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2985 "Counter": "2", 2986 "EventCode": "0xB7", 2987 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2988 "MSRIndex": "0x1A6", 2989 "MSRValue": "0x4770", 2990 "SampleAfterValue": "100000", 2991 "UMask": "0x1" 2992 }, 2993 { 2994 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2995 "Counter": "2", 2996 "EventCode": "0xB7", 2997 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2998 "MSRIndex": "0x1A6", 2999 "MSRValue": "0x1870", 3000 "SampleAfterValue": "100000", 3001 "UMask": "0x1" 3002 }, 3003 { 3004 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 3005 "Counter": "2", 3006 "EventCode": "0xB7", 3007 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 3008 "MSRIndex": "0x1A6", 3009 "MSRValue": "0x3870", 3010 "SampleAfterValue": "100000", 3011 "UMask": "0x1" 3012 }, 3013 { 3014 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 3015 "Counter": "2", 3016 "EventCode": "0xB7", 3017 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 3018 "MSRIndex": "0x1A6", 3019 "MSRValue": "0x1070", 3020 "SampleAfterValue": "100000", 3021 "UMask": "0x1" 3022 }, 3023 { 3024 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 3025 "Counter": "2", 3026 "EventCode": "0xB7", 3027 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 3028 "MSRIndex": "0x1A6", 3029 "MSRValue": "0x870", 3030 "SampleAfterValue": "100000", 3031 "UMask": "0x1" 3032 }, 3033 { 3034 "BriefDescription": "Super Queue lock splits across a cache line", 3035 "Counter": "0,1,2,3", 3036 "EventCode": "0xF4", 3037 "EventName": "SQ_MISC.SPLIT_LOCK", 3038 "SampleAfterValue": "2000000", 3039 "UMask": "0x10" 3040 }, 3041 { 3042 "BriefDescription": "Loads delayed with at-Retirement block code", 3043 "Counter": "0,1,2,3", 3044 "EventCode": "0x6", 3045 "EventName": "STORE_BLOCKS.AT_RET", 3046 "SampleAfterValue": "200000", 3047 "UMask": "0x4" 3048 }, 3049 { 3050 "BriefDescription": "Cacheable loads delayed with L1D block code", 3051 "Counter": "0,1,2,3", 3052 "EventCode": "0x6", 3053 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3054 "SampleAfterValue": "200000", 3055 "UMask": "0x8" 3056 } 3057] 3058