1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "Counter": "0,1", 5 "EventCode": "0x63", 6 "EventName": "CACHE_LOCK_CYCLES.L1D", 7 "SampleAfterValue": "2000000", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Cycles L1D and L2 locked", 12 "Counter": "0,1", 13 "EventCode": "0x63", 14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 15 "SampleAfterValue": "2000000", 16 "UMask": "0x1" 17 }, 18 { 19 "BriefDescription": "L1D cache lines replaced in M state", 20 "Counter": "0,1", 21 "EventCode": "0x51", 22 "EventName": "L1D.M_EVICT", 23 "SampleAfterValue": "2000000", 24 "UMask": "0x4" 25 }, 26 { 27 "BriefDescription": "L1D cache lines allocated in the M state", 28 "Counter": "0,1", 29 "EventCode": "0x51", 30 "EventName": "L1D.M_REPL", 31 "SampleAfterValue": "2000000", 32 "UMask": "0x2" 33 }, 34 { 35 "BriefDescription": "L1D snoop eviction of cache lines in M state", 36 "Counter": "0,1", 37 "EventCode": "0x51", 38 "EventName": "L1D.M_SNOOP_EVICT", 39 "SampleAfterValue": "2000000", 40 "UMask": "0x8" 41 }, 42 { 43 "BriefDescription": "L1 data cache lines allocated", 44 "Counter": "0,1", 45 "EventCode": "0x51", 46 "EventName": "L1D.REPL", 47 "SampleAfterValue": "2000000", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "All references to the L1 data cache", 52 "Counter": "0,1", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.ANY", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "L1 data cacheable reads and writes", 60 "Counter": "0,1", 61 "EventCode": "0x43", 62 "EventName": "L1D_ALL_REF.CACHEABLE", 63 "SampleAfterValue": "2000000", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "L1 data cache read in E state", 68 "Counter": "0,1", 69 "EventCode": "0x40", 70 "EventName": "L1D_CACHE_LD.E_STATE", 71 "SampleAfterValue": "2000000", 72 "UMask": "0x4" 73 }, 74 { 75 "BriefDescription": "L1 data cache read in I state (misses)", 76 "Counter": "0,1", 77 "EventCode": "0x40", 78 "EventName": "L1D_CACHE_LD.I_STATE", 79 "SampleAfterValue": "2000000", 80 "UMask": "0x1" 81 }, 82 { 83 "BriefDescription": "L1 data cache reads", 84 "Counter": "0,1", 85 "EventCode": "0x40", 86 "EventName": "L1D_CACHE_LD.MESI", 87 "SampleAfterValue": "2000000", 88 "UMask": "0xf" 89 }, 90 { 91 "BriefDescription": "L1 data cache read in M state", 92 "Counter": "0,1", 93 "EventCode": "0x40", 94 "EventName": "L1D_CACHE_LD.M_STATE", 95 "SampleAfterValue": "2000000", 96 "UMask": "0x8" 97 }, 98 { 99 "BriefDescription": "L1 data cache read in S state", 100 "Counter": "0,1", 101 "EventCode": "0x40", 102 "EventName": "L1D_CACHE_LD.S_STATE", 103 "SampleAfterValue": "2000000", 104 "UMask": "0x2" 105 }, 106 { 107 "BriefDescription": "L1 data cache load locks in E state", 108 "Counter": "0,1", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.E_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x4" 113 }, 114 { 115 "BriefDescription": "L1 data cache load lock hits", 116 "Counter": "0,1", 117 "EventCode": "0x42", 118 "EventName": "L1D_CACHE_LOCK.HIT", 119 "SampleAfterValue": "2000000", 120 "UMask": "0x1" 121 }, 122 { 123 "BriefDescription": "L1 data cache load locks in M state", 124 "Counter": "0,1", 125 "EventCode": "0x42", 126 "EventName": "L1D_CACHE_LOCK.M_STATE", 127 "SampleAfterValue": "2000000", 128 "UMask": "0x8" 129 }, 130 { 131 "BriefDescription": "L1 data cache load locks in S state", 132 "Counter": "0,1", 133 "EventCode": "0x42", 134 "EventName": "L1D_CACHE_LOCK.S_STATE", 135 "SampleAfterValue": "2000000", 136 "UMask": "0x2" 137 }, 138 { 139 "BriefDescription": "L1D load lock accepted in fill buffer", 140 "Counter": "0,1", 141 "EventCode": "0x53", 142 "EventName": "L1D_CACHE_LOCK_FB_HIT", 143 "SampleAfterValue": "2000000", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 148 "Counter": "0,1", 149 "EventCode": "0x52", 150 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 151 "SampleAfterValue": "2000000", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "L1 data cache stores in E state", 156 "Counter": "0,1", 157 "EventCode": "0x41", 158 "EventName": "L1D_CACHE_ST.E_STATE", 159 "SampleAfterValue": "2000000", 160 "UMask": "0x4" 161 }, 162 { 163 "BriefDescription": "L1 data cache stores in M state", 164 "Counter": "0,1", 165 "EventCode": "0x41", 166 "EventName": "L1D_CACHE_ST.M_STATE", 167 "SampleAfterValue": "2000000", 168 "UMask": "0x8" 169 }, 170 { 171 "BriefDescription": "L1 data cache stores in S state", 172 "Counter": "0,1", 173 "EventCode": "0x41", 174 "EventName": "L1D_CACHE_ST.S_STATE", 175 "SampleAfterValue": "2000000", 176 "UMask": "0x2" 177 }, 178 { 179 "BriefDescription": "L1D hardware prefetch misses", 180 "Counter": "0,1", 181 "EventCode": "0x4E", 182 "EventName": "L1D_PREFETCH.MISS", 183 "SampleAfterValue": "200000", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "L1D hardware prefetch requests", 188 "Counter": "0,1", 189 "EventCode": "0x4E", 190 "EventName": "L1D_PREFETCH.REQUESTS", 191 "SampleAfterValue": "200000", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "L1D hardware prefetch requests triggered", 196 "Counter": "0,1", 197 "EventCode": "0x4E", 198 "EventName": "L1D_PREFETCH.TRIGGERS", 199 "SampleAfterValue": "200000", 200 "UMask": "0x4" 201 }, 202 { 203 "BriefDescription": "L1 writebacks to L2 in E state", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x28", 206 "EventName": "L1D_WB_L2.E_STATE", 207 "SampleAfterValue": "100000", 208 "UMask": "0x4" 209 }, 210 { 211 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 212 "Counter": "0,1,2,3", 213 "EventCode": "0x28", 214 "EventName": "L1D_WB_L2.I_STATE", 215 "SampleAfterValue": "100000", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "All L1 writebacks to L2", 220 "Counter": "0,1,2,3", 221 "EventCode": "0x28", 222 "EventName": "L1D_WB_L2.MESI", 223 "SampleAfterValue": "100000", 224 "UMask": "0xf" 225 }, 226 { 227 "BriefDescription": "L1 writebacks to L2 in M state", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x28", 230 "EventName": "L1D_WB_L2.M_STATE", 231 "SampleAfterValue": "100000", 232 "UMask": "0x8" 233 }, 234 { 235 "BriefDescription": "L1 writebacks to L2 in S state", 236 "Counter": "0,1,2,3", 237 "EventCode": "0x28", 238 "EventName": "L1D_WB_L2.S_STATE", 239 "SampleAfterValue": "100000", 240 "UMask": "0x2" 241 }, 242 { 243 "BriefDescription": "All L2 data requests", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x26", 246 "EventName": "L2_DATA_RQSTS.ANY", 247 "SampleAfterValue": "200000", 248 "UMask": "0xff" 249 }, 250 { 251 "BriefDescription": "L2 data demand loads in E state", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x26", 254 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 255 "SampleAfterValue": "200000", 256 "UMask": "0x4" 257 }, 258 { 259 "BriefDescription": "L2 data demand loads in I state (misses)", 260 "Counter": "0,1,2,3", 261 "EventCode": "0x26", 262 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 263 "SampleAfterValue": "200000", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "L2 data demand requests", 268 "Counter": "0,1,2,3", 269 "EventCode": "0x26", 270 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 271 "SampleAfterValue": "200000", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "L2 data demand loads in M state", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 279 "SampleAfterValue": "200000", 280 "UMask": "0x8" 281 }, 282 { 283 "BriefDescription": "L2 data demand loads in S state", 284 "Counter": "0,1,2,3", 285 "EventCode": "0x26", 286 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 287 "SampleAfterValue": "200000", 288 "UMask": "0x2" 289 }, 290 { 291 "BriefDescription": "L2 data prefetches in E state", 292 "Counter": "0,1,2,3", 293 "EventCode": "0x26", 294 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 295 "SampleAfterValue": "200000", 296 "UMask": "0x40" 297 }, 298 { 299 "BriefDescription": "L2 data prefetches in the I state (misses)", 300 "Counter": "0,1,2,3", 301 "EventCode": "0x26", 302 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 303 "SampleAfterValue": "200000", 304 "UMask": "0x10" 305 }, 306 { 307 "BriefDescription": "All L2 data prefetches", 308 "Counter": "0,1,2,3", 309 "EventCode": "0x26", 310 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 311 "SampleAfterValue": "200000", 312 "UMask": "0xf0" 313 }, 314 { 315 "BriefDescription": "L2 data prefetches in M state", 316 "Counter": "0,1,2,3", 317 "EventCode": "0x26", 318 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 319 "SampleAfterValue": "200000", 320 "UMask": "0x80" 321 }, 322 { 323 "BriefDescription": "L2 data prefetches in the S state", 324 "Counter": "0,1,2,3", 325 "EventCode": "0x26", 326 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 327 "SampleAfterValue": "200000", 328 "UMask": "0x20" 329 }, 330 { 331 "BriefDescription": "L2 lines allocated", 332 "Counter": "0,1,2,3", 333 "EventCode": "0xF1", 334 "EventName": "L2_LINES_IN.ANY", 335 "SampleAfterValue": "100000", 336 "UMask": "0x7" 337 }, 338 { 339 "BriefDescription": "L2 lines allocated in the E state", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xF1", 342 "EventName": "L2_LINES_IN.E_STATE", 343 "SampleAfterValue": "100000", 344 "UMask": "0x4" 345 }, 346 { 347 "BriefDescription": "L2 lines allocated in the S state", 348 "Counter": "0,1,2,3", 349 "EventCode": "0xF1", 350 "EventName": "L2_LINES_IN.S_STATE", 351 "SampleAfterValue": "100000", 352 "UMask": "0x2" 353 }, 354 { 355 "BriefDescription": "L2 lines evicted", 356 "Counter": "0,1,2,3", 357 "EventCode": "0xF2", 358 "EventName": "L2_LINES_OUT.ANY", 359 "SampleAfterValue": "100000", 360 "UMask": "0xf" 361 }, 362 { 363 "BriefDescription": "L2 lines evicted by a demand request", 364 "Counter": "0,1,2,3", 365 "EventCode": "0xF2", 366 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 367 "SampleAfterValue": "100000", 368 "UMask": "0x1" 369 }, 370 { 371 "BriefDescription": "L2 modified lines evicted by a demand request", 372 "Counter": "0,1,2,3", 373 "EventCode": "0xF2", 374 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 375 "SampleAfterValue": "100000", 376 "UMask": "0x2" 377 }, 378 { 379 "BriefDescription": "L2 lines evicted by a prefetch request", 380 "Counter": "0,1,2,3", 381 "EventCode": "0xF2", 382 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 383 "SampleAfterValue": "100000", 384 "UMask": "0x4" 385 }, 386 { 387 "BriefDescription": "L2 modified lines evicted by a prefetch request", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xF2", 390 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 391 "SampleAfterValue": "100000", 392 "UMask": "0x8" 393 }, 394 { 395 "BriefDescription": "L2 instruction fetches", 396 "Counter": "0,1,2,3", 397 "EventCode": "0x24", 398 "EventName": "L2_RQSTS.IFETCHES", 399 "SampleAfterValue": "200000", 400 "UMask": "0x30" 401 }, 402 { 403 "BriefDescription": "L2 instruction fetch hits", 404 "Counter": "0,1,2,3", 405 "EventCode": "0x24", 406 "EventName": "L2_RQSTS.IFETCH_HIT", 407 "SampleAfterValue": "200000", 408 "UMask": "0x10" 409 }, 410 { 411 "BriefDescription": "L2 instruction fetch misses", 412 "Counter": "0,1,2,3", 413 "EventCode": "0x24", 414 "EventName": "L2_RQSTS.IFETCH_MISS", 415 "SampleAfterValue": "200000", 416 "UMask": "0x20" 417 }, 418 { 419 "BriefDescription": "L2 load hits", 420 "Counter": "0,1,2,3", 421 "EventCode": "0x24", 422 "EventName": "L2_RQSTS.LD_HIT", 423 "SampleAfterValue": "200000", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "L2 load misses", 428 "Counter": "0,1,2,3", 429 "EventCode": "0x24", 430 "EventName": "L2_RQSTS.LD_MISS", 431 "SampleAfterValue": "200000", 432 "UMask": "0x2" 433 }, 434 { 435 "BriefDescription": "L2 requests", 436 "Counter": "0,1,2,3", 437 "EventCode": "0x24", 438 "EventName": "L2_RQSTS.LOADS", 439 "SampleAfterValue": "200000", 440 "UMask": "0x3" 441 }, 442 { 443 "BriefDescription": "All L2 misses", 444 "Counter": "0,1,2,3", 445 "EventCode": "0x24", 446 "EventName": "L2_RQSTS.MISS", 447 "SampleAfterValue": "200000", 448 "UMask": "0xaa" 449 }, 450 { 451 "BriefDescription": "All L2 prefetches", 452 "Counter": "0,1,2,3", 453 "EventCode": "0x24", 454 "EventName": "L2_RQSTS.PREFETCHES", 455 "SampleAfterValue": "200000", 456 "UMask": "0xc0" 457 }, 458 { 459 "BriefDescription": "L2 prefetch hits", 460 "Counter": "0,1,2,3", 461 "EventCode": "0x24", 462 "EventName": "L2_RQSTS.PREFETCH_HIT", 463 "SampleAfterValue": "200000", 464 "UMask": "0x40" 465 }, 466 { 467 "BriefDescription": "L2 prefetch misses", 468 "Counter": "0,1,2,3", 469 "EventCode": "0x24", 470 "EventName": "L2_RQSTS.PREFETCH_MISS", 471 "SampleAfterValue": "200000", 472 "UMask": "0x80" 473 }, 474 { 475 "BriefDescription": "All L2 requests", 476 "Counter": "0,1,2,3", 477 "EventCode": "0x24", 478 "EventName": "L2_RQSTS.REFERENCES", 479 "SampleAfterValue": "200000", 480 "UMask": "0xff" 481 }, 482 { 483 "BriefDescription": "L2 RFO requests", 484 "Counter": "0,1,2,3", 485 "EventCode": "0x24", 486 "EventName": "L2_RQSTS.RFOS", 487 "SampleAfterValue": "200000", 488 "UMask": "0xc" 489 }, 490 { 491 "BriefDescription": "L2 RFO hits", 492 "Counter": "0,1,2,3", 493 "EventCode": "0x24", 494 "EventName": "L2_RQSTS.RFO_HIT", 495 "SampleAfterValue": "200000", 496 "UMask": "0x4" 497 }, 498 { 499 "BriefDescription": "L2 RFO misses", 500 "Counter": "0,1,2,3", 501 "EventCode": "0x24", 502 "EventName": "L2_RQSTS.RFO_MISS", 503 "SampleAfterValue": "200000", 504 "UMask": "0x8" 505 }, 506 { 507 "BriefDescription": "All L2 transactions", 508 "Counter": "0,1,2,3", 509 "EventCode": "0xF0", 510 "EventName": "L2_TRANSACTIONS.ANY", 511 "SampleAfterValue": "200000", 512 "UMask": "0x80" 513 }, 514 { 515 "BriefDescription": "L2 fill transactions", 516 "Counter": "0,1,2,3", 517 "EventCode": "0xF0", 518 "EventName": "L2_TRANSACTIONS.FILL", 519 "SampleAfterValue": "200000", 520 "UMask": "0x20" 521 }, 522 { 523 "BriefDescription": "L2 instruction fetch transactions", 524 "Counter": "0,1,2,3", 525 "EventCode": "0xF0", 526 "EventName": "L2_TRANSACTIONS.IFETCH", 527 "SampleAfterValue": "200000", 528 "UMask": "0x4" 529 }, 530 { 531 "BriefDescription": "L1D writeback to L2 transactions", 532 "Counter": "0,1,2,3", 533 "EventCode": "0xF0", 534 "EventName": "L2_TRANSACTIONS.L1D_WB", 535 "SampleAfterValue": "200000", 536 "UMask": "0x10" 537 }, 538 { 539 "BriefDescription": "L2 Load transactions", 540 "Counter": "0,1,2,3", 541 "EventCode": "0xF0", 542 "EventName": "L2_TRANSACTIONS.LOAD", 543 "SampleAfterValue": "200000", 544 "UMask": "0x1" 545 }, 546 { 547 "BriefDescription": "L2 prefetch transactions", 548 "Counter": "0,1,2,3", 549 "EventCode": "0xF0", 550 "EventName": "L2_TRANSACTIONS.PREFETCH", 551 "SampleAfterValue": "200000", 552 "UMask": "0x8" 553 }, 554 { 555 "BriefDescription": "L2 RFO transactions", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xF0", 558 "EventName": "L2_TRANSACTIONS.RFO", 559 "SampleAfterValue": "200000", 560 "UMask": "0x2" 561 }, 562 { 563 "BriefDescription": "L2 writeback to LLC transactions", 564 "Counter": "0,1,2,3", 565 "EventCode": "0xF0", 566 "EventName": "L2_TRANSACTIONS.WB", 567 "SampleAfterValue": "200000", 568 "UMask": "0x40" 569 }, 570 { 571 "BriefDescription": "L2 demand lock RFOs in E state", 572 "Counter": "0,1,2,3", 573 "EventCode": "0x27", 574 "EventName": "L2_WRITE.LOCK.E_STATE", 575 "SampleAfterValue": "100000", 576 "UMask": "0x40" 577 }, 578 { 579 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 580 "Counter": "0,1,2,3", 581 "EventCode": "0x27", 582 "EventName": "L2_WRITE.LOCK.HIT", 583 "SampleAfterValue": "100000", 584 "UMask": "0xe0" 585 }, 586 { 587 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 588 "Counter": "0,1,2,3", 589 "EventCode": "0x27", 590 "EventName": "L2_WRITE.LOCK.I_STATE", 591 "SampleAfterValue": "100000", 592 "UMask": "0x10" 593 }, 594 { 595 "BriefDescription": "All demand L2 lock RFOs", 596 "Counter": "0,1,2,3", 597 "EventCode": "0x27", 598 "EventName": "L2_WRITE.LOCK.MESI", 599 "SampleAfterValue": "100000", 600 "UMask": "0xf0" 601 }, 602 { 603 "BriefDescription": "L2 demand lock RFOs in M state", 604 "Counter": "0,1,2,3", 605 "EventCode": "0x27", 606 "EventName": "L2_WRITE.LOCK.M_STATE", 607 "SampleAfterValue": "100000", 608 "UMask": "0x80" 609 }, 610 { 611 "BriefDescription": "L2 demand lock RFOs in S state", 612 "Counter": "0,1,2,3", 613 "EventCode": "0x27", 614 "EventName": "L2_WRITE.LOCK.S_STATE", 615 "SampleAfterValue": "100000", 616 "UMask": "0x20" 617 }, 618 { 619 "BriefDescription": "All L2 demand store RFOs that hit the cache", 620 "Counter": "0,1,2,3", 621 "EventCode": "0x27", 622 "EventName": "L2_WRITE.RFO.HIT", 623 "SampleAfterValue": "100000", 624 "UMask": "0xe" 625 }, 626 { 627 "BriefDescription": "L2 demand store RFOs in I state (misses)", 628 "Counter": "0,1,2,3", 629 "EventCode": "0x27", 630 "EventName": "L2_WRITE.RFO.I_STATE", 631 "SampleAfterValue": "100000", 632 "UMask": "0x1" 633 }, 634 { 635 "BriefDescription": "All L2 demand store RFOs", 636 "Counter": "0,1,2,3", 637 "EventCode": "0x27", 638 "EventName": "L2_WRITE.RFO.MESI", 639 "SampleAfterValue": "100000", 640 "UMask": "0xf" 641 }, 642 { 643 "BriefDescription": "L2 demand store RFOs in M state", 644 "Counter": "0,1,2,3", 645 "EventCode": "0x27", 646 "EventName": "L2_WRITE.RFO.M_STATE", 647 "SampleAfterValue": "100000", 648 "UMask": "0x8" 649 }, 650 { 651 "BriefDescription": "L2 demand store RFOs in S state", 652 "Counter": "0,1,2,3", 653 "EventCode": "0x27", 654 "EventName": "L2_WRITE.RFO.S_STATE", 655 "SampleAfterValue": "100000", 656 "UMask": "0x2" 657 }, 658 { 659 "BriefDescription": "Longest latency cache miss", 660 "Counter": "0,1,2,3", 661 "EventCode": "0x2E", 662 "EventName": "LONGEST_LAT_CACHE.MISS", 663 "SampleAfterValue": "100000", 664 "UMask": "0x41" 665 }, 666 { 667 "BriefDescription": "Longest latency cache reference", 668 "Counter": "0,1,2,3", 669 "EventCode": "0x2E", 670 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 671 "SampleAfterValue": "200000", 672 "UMask": "0x4f" 673 }, 674 { 675 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 676 "Counter": "3", 677 "EventCode": "0xB", 678 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 679 "MSRIndex": "0x3F6", 680 "PEBS": "2", 681 "SampleAfterValue": "2000000", 682 "UMask": "0x10" 683 }, 684 { 685 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 686 "Counter": "3", 687 "EventCode": "0xB", 688 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 689 "MSRIndex": "0x3F6", 690 "MSRValue": "0x400", 691 "PEBS": "2", 692 "SampleAfterValue": "100", 693 "UMask": "0x10" 694 }, 695 { 696 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 697 "Counter": "3", 698 "EventCode": "0xB", 699 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 700 "MSRIndex": "0x3F6", 701 "MSRValue": "0x80", 702 "PEBS": "2", 703 "SampleAfterValue": "1000", 704 "UMask": "0x10" 705 }, 706 { 707 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 708 "Counter": "3", 709 "EventCode": "0xB", 710 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 711 "MSRIndex": "0x3F6", 712 "MSRValue": "0x10", 713 "PEBS": "2", 714 "SampleAfterValue": "10000", 715 "UMask": "0x10" 716 }, 717 { 718 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 719 "Counter": "3", 720 "EventCode": "0xB", 721 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 722 "MSRIndex": "0x3F6", 723 "MSRValue": "0x4000", 724 "PEBS": "2", 725 "SampleAfterValue": "5", 726 "UMask": "0x10" 727 }, 728 { 729 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 730 "Counter": "3", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x800", 735 "PEBS": "2", 736 "SampleAfterValue": "50", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 741 "Counter": "3", 742 "EventCode": "0xB", 743 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 744 "MSRIndex": "0x3F6", 745 "MSRValue": "0x100", 746 "PEBS": "2", 747 "SampleAfterValue": "500", 748 "UMask": "0x10" 749 }, 750 { 751 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 752 "Counter": "3", 753 "EventCode": "0xB", 754 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 755 "MSRIndex": "0x3F6", 756 "MSRValue": "0x20", 757 "PEBS": "2", 758 "SampleAfterValue": "5000", 759 "UMask": "0x10" 760 }, 761 { 762 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 763 "Counter": "3", 764 "EventCode": "0xB", 765 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 766 "MSRIndex": "0x3F6", 767 "MSRValue": "0x8000", 768 "PEBS": "2", 769 "SampleAfterValue": "3", 770 "UMask": "0x10" 771 }, 772 { 773 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 774 "Counter": "3", 775 "EventCode": "0xB", 776 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 777 "MSRIndex": "0x3F6", 778 "MSRValue": "0x4", 779 "PEBS": "2", 780 "SampleAfterValue": "50000", 781 "UMask": "0x10" 782 }, 783 { 784 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 785 "Counter": "3", 786 "EventCode": "0xB", 787 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 788 "MSRIndex": "0x3F6", 789 "MSRValue": "0x1000", 790 "PEBS": "2", 791 "SampleAfterValue": "20", 792 "UMask": "0x10" 793 }, 794 { 795 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 796 "Counter": "3", 797 "EventCode": "0xB", 798 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 799 "MSRIndex": "0x3F6", 800 "MSRValue": "0x200", 801 "PEBS": "2", 802 "SampleAfterValue": "200", 803 "UMask": "0x10" 804 }, 805 { 806 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 807 "Counter": "3", 808 "EventCode": "0xB", 809 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 810 "MSRIndex": "0x3F6", 811 "MSRValue": "0x40", 812 "PEBS": "2", 813 "SampleAfterValue": "2000", 814 "UMask": "0x10" 815 }, 816 { 817 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 818 "Counter": "3", 819 "EventCode": "0xB", 820 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 821 "MSRIndex": "0x3F6", 822 "MSRValue": "0x8", 823 "PEBS": "2", 824 "SampleAfterValue": "20000", 825 "UMask": "0x10" 826 }, 827 { 828 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 829 "Counter": "3", 830 "EventCode": "0xB", 831 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 832 "MSRIndex": "0x3F6", 833 "MSRValue": "0x2000", 834 "PEBS": "2", 835 "SampleAfterValue": "10", 836 "UMask": "0x10" 837 }, 838 { 839 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 840 "Counter": "0,1,2,3", 841 "EventCode": "0xB", 842 "EventName": "MEM_INST_RETIRED.LOADS", 843 "PEBS": "1", 844 "SampleAfterValue": "2000000", 845 "UMask": "0x1" 846 }, 847 { 848 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 849 "Counter": "0,1,2,3", 850 "EventCode": "0xB", 851 "EventName": "MEM_INST_RETIRED.STORES", 852 "PEBS": "1", 853 "SampleAfterValue": "2000000", 854 "UMask": "0x2" 855 }, 856 { 857 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 858 "Counter": "0,1,2,3", 859 "EventCode": "0xCB", 860 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 861 "PEBS": "1", 862 "SampleAfterValue": "200000", 863 "UMask": "0x40" 864 }, 865 { 866 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 867 "Counter": "0,1,2,3", 868 "EventCode": "0xCB", 869 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 870 "PEBS": "1", 871 "SampleAfterValue": "2000000", 872 "UMask": "0x1" 873 }, 874 { 875 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 876 "Counter": "0,1,2,3", 877 "EventCode": "0xCB", 878 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 879 "PEBS": "1", 880 "SampleAfterValue": "200000", 881 "UMask": "0x2" 882 }, 883 { 884 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 885 "Counter": "0,1,2,3", 886 "EventCode": "0xCB", 887 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 888 "PEBS": "1", 889 "SampleAfterValue": "10000", 890 "UMask": "0x10" 891 }, 892 { 893 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 894 "Counter": "0,1,2,3", 895 "EventCode": "0xCB", 896 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 897 "PEBS": "1", 898 "SampleAfterValue": "40000", 899 "UMask": "0x4" 900 }, 901 { 902 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 903 "Counter": "0,1,2,3", 904 "EventCode": "0xCB", 905 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 906 "PEBS": "1", 907 "SampleAfterValue": "40000", 908 "UMask": "0x8" 909 }, 910 { 911 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 912 "Counter": "0,1,2,3", 913 "EventCode": "0xF", 914 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 915 "PEBS": "1", 916 "SampleAfterValue": "10000", 917 "UMask": "0x20" 918 }, 919 { 920 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 921 "Counter": "0,1,2,3", 922 "EventCode": "0xF", 923 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 924 "PEBS": "1", 925 "SampleAfterValue": "40000", 926 "UMask": "0x2" 927 }, 928 { 929 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 930 "Counter": "0,1,2,3", 931 "EventCode": "0xF", 932 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 933 "PEBS": "1", 934 "SampleAfterValue": "20000", 935 "UMask": "0x8" 936 }, 937 { 938 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 939 "Counter": "0,1,2,3", 940 "EventCode": "0xF", 941 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 942 "PEBS": "1", 943 "SampleAfterValue": "10000", 944 "UMask": "0x10" 945 }, 946 { 947 "BriefDescription": "Load instructions retired IO (Precise Event)", 948 "Counter": "0,1,2,3", 949 "EventCode": "0xF", 950 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 951 "PEBS": "1", 952 "SampleAfterValue": "4000", 953 "UMask": "0x80" 954 }, 955 { 956 "BriefDescription": "Offcore L1 data cache writebacks", 957 "Counter": "0,1,2,3", 958 "EventCode": "0xB0", 959 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 960 "SampleAfterValue": "100000", 961 "UMask": "0x40" 962 }, 963 { 964 "BriefDescription": "Offcore requests blocked due to Super Queue full", 965 "Counter": "0,1,2,3", 966 "EventCode": "0xB2", 967 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 968 "SampleAfterValue": "100000", 969 "UMask": "0x1" 970 }, 971 { 972 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 973 "Counter": "2", 974 "EventCode": "0xB7", 975 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 976 "MSRIndex": "0x1A6", 977 "MSRValue": "0x7F11", 978 "SampleAfterValue": "100000", 979 "UMask": "0x1" 980 }, 981 { 982 "BriefDescription": "All offcore data reads", 983 "Counter": "2", 984 "EventCode": "0xB7", 985 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 986 "MSRIndex": "0x1A6", 987 "MSRValue": "0xFF11", 988 "SampleAfterValue": "100000", 989 "UMask": "0x1" 990 }, 991 { 992 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 993 "Counter": "2", 994 "EventCode": "0xB7", 995 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 996 "MSRIndex": "0x1A6", 997 "MSRValue": "0x8011", 998 "SampleAfterValue": "100000", 999 "UMask": "0x1" 1000 }, 1001 { 1002 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 1003 "Counter": "2", 1004 "EventCode": "0xB7", 1005 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 1006 "MSRIndex": "0x1A6", 1007 "MSRValue": "0x111", 1008 "SampleAfterValue": "100000", 1009 "UMask": "0x1" 1010 }, 1011 { 1012 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 1013 "Counter": "2", 1014 "EventCode": "0xB7", 1015 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 1016 "MSRIndex": "0x1A6", 1017 "MSRValue": "0x211", 1018 "SampleAfterValue": "100000", 1019 "UMask": "0x1" 1020 }, 1021 { 1022 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 1023 "Counter": "2", 1024 "EventCode": "0xB7", 1025 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 1026 "MSRIndex": "0x1A6", 1027 "MSRValue": "0x411", 1028 "SampleAfterValue": "100000", 1029 "UMask": "0x1" 1030 }, 1031 { 1032 "BriefDescription": "Offcore data reads satisfied by the LLC", 1033 "Counter": "2", 1034 "EventCode": "0xB7", 1035 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 1036 "MSRIndex": "0x1A6", 1037 "MSRValue": "0x711", 1038 "SampleAfterValue": "100000", 1039 "UMask": "0x1" 1040 }, 1041 { 1042 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 1043 "Counter": "2", 1044 "EventCode": "0xB7", 1045 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 1046 "MSRIndex": "0x1A6", 1047 "MSRValue": "0x4711", 1048 "SampleAfterValue": "100000", 1049 "UMask": "0x1" 1050 }, 1051 { 1052 "BriefDescription": "Offcore data reads satisfied by a remote cache", 1053 "Counter": "2", 1054 "EventCode": "0xB7", 1055 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 1056 "MSRIndex": "0x1A6", 1057 "MSRValue": "0x1811", 1058 "SampleAfterValue": "100000", 1059 "UMask": "0x1" 1060 }, 1061 { 1062 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 1063 "Counter": "2", 1064 "EventCode": "0xB7", 1065 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 1066 "MSRIndex": "0x1A6", 1067 "MSRValue": "0x3811", 1068 "SampleAfterValue": "100000", 1069 "UMask": "0x1" 1070 }, 1071 { 1072 "BriefDescription": "Offcore data reads that HIT in a remote cache", 1073 "Counter": "2", 1074 "EventCode": "0xB7", 1075 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 1076 "MSRIndex": "0x1A6", 1077 "MSRValue": "0x1011", 1078 "SampleAfterValue": "100000", 1079 "UMask": "0x1" 1080 }, 1081 { 1082 "BriefDescription": "Offcore data reads that HITM in a remote cache", 1083 "Counter": "2", 1084 "EventCode": "0xB7", 1085 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 1086 "MSRIndex": "0x1A6", 1087 "MSRValue": "0x811", 1088 "SampleAfterValue": "100000", 1089 "UMask": "0x1" 1090 }, 1091 { 1092 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 1093 "Counter": "2", 1094 "EventCode": "0xB7", 1095 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 1096 "MSRIndex": "0x1A6", 1097 "MSRValue": "0x7F44", 1098 "SampleAfterValue": "100000", 1099 "UMask": "0x1" 1100 }, 1101 { 1102 "BriefDescription": "All offcore code reads", 1103 "Counter": "2", 1104 "EventCode": "0xB7", 1105 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 1106 "MSRIndex": "0x1A6", 1107 "MSRValue": "0xFF44", 1108 "SampleAfterValue": "100000", 1109 "UMask": "0x1" 1110 }, 1111 { 1112 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 1113 "Counter": "2", 1114 "EventCode": "0xB7", 1115 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 1116 "MSRIndex": "0x1A6", 1117 "MSRValue": "0x8044", 1118 "SampleAfterValue": "100000", 1119 "UMask": "0x1" 1120 }, 1121 { 1122 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 1123 "Counter": "2", 1124 "EventCode": "0xB7", 1125 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 1126 "MSRIndex": "0x1A6", 1127 "MSRValue": "0x144", 1128 "SampleAfterValue": "100000", 1129 "UMask": "0x1" 1130 }, 1131 { 1132 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1133 "Counter": "2", 1134 "EventCode": "0xB7", 1135 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1136 "MSRIndex": "0x1A6", 1137 "MSRValue": "0x244", 1138 "SampleAfterValue": "100000", 1139 "UMask": "0x1" 1140 }, 1141 { 1142 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1143 "Counter": "2", 1144 "EventCode": "0xB7", 1145 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1146 "MSRIndex": "0x1A6", 1147 "MSRValue": "0x444", 1148 "SampleAfterValue": "100000", 1149 "UMask": "0x1" 1150 }, 1151 { 1152 "BriefDescription": "Offcore code reads satisfied by the LLC", 1153 "Counter": "2", 1154 "EventCode": "0xB7", 1155 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1156 "MSRIndex": "0x1A6", 1157 "MSRValue": "0x744", 1158 "SampleAfterValue": "100000", 1159 "UMask": "0x1" 1160 }, 1161 { 1162 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1163 "Counter": "2", 1164 "EventCode": "0xB7", 1165 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1166 "MSRIndex": "0x1A6", 1167 "MSRValue": "0x4744", 1168 "SampleAfterValue": "100000", 1169 "UMask": "0x1" 1170 }, 1171 { 1172 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1173 "Counter": "2", 1174 "EventCode": "0xB7", 1175 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1176 "MSRIndex": "0x1A6", 1177 "MSRValue": "0x1844", 1178 "SampleAfterValue": "100000", 1179 "UMask": "0x1" 1180 }, 1181 { 1182 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1183 "Counter": "2", 1184 "EventCode": "0xB7", 1185 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1186 "MSRIndex": "0x1A6", 1187 "MSRValue": "0x3844", 1188 "SampleAfterValue": "100000", 1189 "UMask": "0x1" 1190 }, 1191 { 1192 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1193 "Counter": "2", 1194 "EventCode": "0xB7", 1195 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1196 "MSRIndex": "0x1A6", 1197 "MSRValue": "0x1044", 1198 "SampleAfterValue": "100000", 1199 "UMask": "0x1" 1200 }, 1201 { 1202 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1203 "Counter": "2", 1204 "EventCode": "0xB7", 1205 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1206 "MSRIndex": "0x1A6", 1207 "MSRValue": "0x844", 1208 "SampleAfterValue": "100000", 1209 "UMask": "0x1" 1210 }, 1211 { 1212 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1213 "Counter": "2", 1214 "EventCode": "0xB7", 1215 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1216 "MSRIndex": "0x1A6", 1217 "MSRValue": "0x7FFF", 1218 "SampleAfterValue": "100000", 1219 "UMask": "0x1" 1220 }, 1221 { 1222 "BriefDescription": "All offcore requests", 1223 "Counter": "2", 1224 "EventCode": "0xB7", 1225 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1226 "MSRIndex": "0x1A6", 1227 "MSRValue": "0xFFFF", 1228 "SampleAfterValue": "100000", 1229 "UMask": "0x1" 1230 }, 1231 { 1232 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1233 "Counter": "2", 1234 "EventCode": "0xB7", 1235 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1236 "MSRIndex": "0x1A6", 1237 "MSRValue": "0x80FF", 1238 "SampleAfterValue": "100000", 1239 "UMask": "0x1" 1240 }, 1241 { 1242 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1243 "Counter": "2", 1244 "EventCode": "0xB7", 1245 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1246 "MSRIndex": "0x1A6", 1247 "MSRValue": "0x1FF", 1248 "SampleAfterValue": "100000", 1249 "UMask": "0x1" 1250 }, 1251 { 1252 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1253 "Counter": "2", 1254 "EventCode": "0xB7", 1255 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1256 "MSRIndex": "0x1A6", 1257 "MSRValue": "0x2FF", 1258 "SampleAfterValue": "100000", 1259 "UMask": "0x1" 1260 }, 1261 { 1262 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1263 "Counter": "2", 1264 "EventCode": "0xB7", 1265 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1266 "MSRIndex": "0x1A6", 1267 "MSRValue": "0x4FF", 1268 "SampleAfterValue": "100000", 1269 "UMask": "0x1" 1270 }, 1271 { 1272 "BriefDescription": "Offcore requests satisfied by the LLC", 1273 "Counter": "2", 1274 "EventCode": "0xB7", 1275 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1276 "MSRIndex": "0x1A6", 1277 "MSRValue": "0x7FF", 1278 "SampleAfterValue": "100000", 1279 "UMask": "0x1" 1280 }, 1281 { 1282 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1283 "Counter": "2", 1284 "EventCode": "0xB7", 1285 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1286 "MSRIndex": "0x1A6", 1287 "MSRValue": "0x47FF", 1288 "SampleAfterValue": "100000", 1289 "UMask": "0x1" 1290 }, 1291 { 1292 "BriefDescription": "Offcore requests satisfied by a remote cache", 1293 "Counter": "2", 1294 "EventCode": "0xB7", 1295 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1296 "MSRIndex": "0x1A6", 1297 "MSRValue": "0x18FF", 1298 "SampleAfterValue": "100000", 1299 "UMask": "0x1" 1300 }, 1301 { 1302 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1303 "Counter": "2", 1304 "EventCode": "0xB7", 1305 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1306 "MSRIndex": "0x1A6", 1307 "MSRValue": "0x38FF", 1308 "SampleAfterValue": "100000", 1309 "UMask": "0x1" 1310 }, 1311 { 1312 "BriefDescription": "Offcore requests that HIT in a remote cache", 1313 "Counter": "2", 1314 "EventCode": "0xB7", 1315 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1316 "MSRIndex": "0x1A6", 1317 "MSRValue": "0x10FF", 1318 "SampleAfterValue": "100000", 1319 "UMask": "0x1" 1320 }, 1321 { 1322 "BriefDescription": "Offcore requests that HITM in a remote cache", 1323 "Counter": "2", 1324 "EventCode": "0xB7", 1325 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1326 "MSRIndex": "0x1A6", 1327 "MSRValue": "0x8FF", 1328 "SampleAfterValue": "100000", 1329 "UMask": "0x1" 1330 }, 1331 { 1332 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1333 "Counter": "2", 1334 "EventCode": "0xB7", 1335 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1336 "MSRIndex": "0x1A6", 1337 "MSRValue": "0x7F22", 1338 "SampleAfterValue": "100000", 1339 "UMask": "0x1" 1340 }, 1341 { 1342 "BriefDescription": "All offcore RFO requests", 1343 "Counter": "2", 1344 "EventCode": "0xB7", 1345 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1346 "MSRIndex": "0x1A6", 1347 "MSRValue": "0xFF22", 1348 "SampleAfterValue": "100000", 1349 "UMask": "0x1" 1350 }, 1351 { 1352 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1353 "Counter": "2", 1354 "EventCode": "0xB7", 1355 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1356 "MSRIndex": "0x1A6", 1357 "MSRValue": "0x8022", 1358 "SampleAfterValue": "100000", 1359 "UMask": "0x1" 1360 }, 1361 { 1362 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1363 "Counter": "2", 1364 "EventCode": "0xB7", 1365 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1366 "MSRIndex": "0x1A6", 1367 "MSRValue": "0x122", 1368 "SampleAfterValue": "100000", 1369 "UMask": "0x1" 1370 }, 1371 { 1372 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1373 "Counter": "2", 1374 "EventCode": "0xB7", 1375 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1376 "MSRIndex": "0x1A6", 1377 "MSRValue": "0x222", 1378 "SampleAfterValue": "100000", 1379 "UMask": "0x1" 1380 }, 1381 { 1382 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1383 "Counter": "2", 1384 "EventCode": "0xB7", 1385 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1386 "MSRIndex": "0x1A6", 1387 "MSRValue": "0x422", 1388 "SampleAfterValue": "100000", 1389 "UMask": "0x1" 1390 }, 1391 { 1392 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1393 "Counter": "2", 1394 "EventCode": "0xB7", 1395 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1396 "MSRIndex": "0x1A6", 1397 "MSRValue": "0x722", 1398 "SampleAfterValue": "100000", 1399 "UMask": "0x1" 1400 }, 1401 { 1402 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1403 "Counter": "2", 1404 "EventCode": "0xB7", 1405 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1406 "MSRIndex": "0x1A6", 1407 "MSRValue": "0x4722", 1408 "SampleAfterValue": "100000", 1409 "UMask": "0x1" 1410 }, 1411 { 1412 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1413 "Counter": "2", 1414 "EventCode": "0xB7", 1415 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1416 "MSRIndex": "0x1A6", 1417 "MSRValue": "0x1822", 1418 "SampleAfterValue": "100000", 1419 "UMask": "0x1" 1420 }, 1421 { 1422 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1423 "Counter": "2", 1424 "EventCode": "0xB7", 1425 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1426 "MSRIndex": "0x1A6", 1427 "MSRValue": "0x3822", 1428 "SampleAfterValue": "100000", 1429 "UMask": "0x1" 1430 }, 1431 { 1432 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1433 "Counter": "2", 1434 "EventCode": "0xB7", 1435 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1436 "MSRIndex": "0x1A6", 1437 "MSRValue": "0x1022", 1438 "SampleAfterValue": "100000", 1439 "UMask": "0x1" 1440 }, 1441 { 1442 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1443 "Counter": "2", 1444 "EventCode": "0xB7", 1445 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1446 "MSRIndex": "0x1A6", 1447 "MSRValue": "0x822", 1448 "SampleAfterValue": "100000", 1449 "UMask": "0x1" 1450 }, 1451 { 1452 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1453 "Counter": "2", 1454 "EventCode": "0xB7", 1455 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1456 "MSRIndex": "0x1A6", 1457 "MSRValue": "0x7F08", 1458 "SampleAfterValue": "100000", 1459 "UMask": "0x1" 1460 }, 1461 { 1462 "BriefDescription": "All offcore writebacks", 1463 "Counter": "2", 1464 "EventCode": "0xB7", 1465 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1466 "MSRIndex": "0x1A6", 1467 "MSRValue": "0xFF08", 1468 "SampleAfterValue": "100000", 1469 "UMask": "0x1" 1470 }, 1471 { 1472 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1473 "Counter": "2", 1474 "EventCode": "0xB7", 1475 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1476 "MSRIndex": "0x1A6", 1477 "MSRValue": "0x8008", 1478 "SampleAfterValue": "100000", 1479 "UMask": "0x1" 1480 }, 1481 { 1482 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1483 "Counter": "2", 1484 "EventCode": "0xB7", 1485 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1486 "MSRIndex": "0x1A6", 1487 "MSRValue": "0x108", 1488 "SampleAfterValue": "100000", 1489 "UMask": "0x1" 1490 }, 1491 { 1492 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1493 "Counter": "2", 1494 "EventCode": "0xB7", 1495 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1496 "MSRIndex": "0x1A6", 1497 "MSRValue": "0x408", 1498 "SampleAfterValue": "100000", 1499 "UMask": "0x1" 1500 }, 1501 { 1502 "BriefDescription": "Offcore writebacks to the LLC", 1503 "Counter": "2", 1504 "EventCode": "0xB7", 1505 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1506 "MSRIndex": "0x1A6", 1507 "MSRValue": "0x708", 1508 "SampleAfterValue": "100000", 1509 "UMask": "0x1" 1510 }, 1511 { 1512 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1513 "Counter": "2", 1514 "EventCode": "0xB7", 1515 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1516 "MSRIndex": "0x1A6", 1517 "MSRValue": "0x4708", 1518 "SampleAfterValue": "100000", 1519 "UMask": "0x1" 1520 }, 1521 { 1522 "BriefDescription": "Offcore writebacks to a remote cache", 1523 "Counter": "2", 1524 "EventCode": "0xB7", 1525 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1526 "MSRIndex": "0x1A6", 1527 "MSRValue": "0x1808", 1528 "SampleAfterValue": "100000", 1529 "UMask": "0x1" 1530 }, 1531 { 1532 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1533 "Counter": "2", 1534 "EventCode": "0xB7", 1535 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1536 "MSRIndex": "0x1A6", 1537 "MSRValue": "0x3808", 1538 "SampleAfterValue": "100000", 1539 "UMask": "0x1" 1540 }, 1541 { 1542 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1543 "Counter": "2", 1544 "EventCode": "0xB7", 1545 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1546 "MSRIndex": "0x1A6", 1547 "MSRValue": "0x1008", 1548 "SampleAfterValue": "100000", 1549 "UMask": "0x1" 1550 }, 1551 { 1552 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1553 "Counter": "2", 1554 "EventCode": "0xB7", 1555 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1556 "MSRIndex": "0x1A6", 1557 "MSRValue": "0x808", 1558 "SampleAfterValue": "100000", 1559 "UMask": "0x1" 1560 }, 1561 { 1562 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1563 "Counter": "2", 1564 "EventCode": "0xB7", 1565 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1566 "MSRIndex": "0x1A6", 1567 "MSRValue": "0x7F77", 1568 "SampleAfterValue": "100000", 1569 "UMask": "0x1" 1570 }, 1571 { 1572 "BriefDescription": "All offcore code or data read requests", 1573 "Counter": "2", 1574 "EventCode": "0xB7", 1575 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1576 "MSRIndex": "0x1A6", 1577 "MSRValue": "0xFF77", 1578 "SampleAfterValue": "100000", 1579 "UMask": "0x1" 1580 }, 1581 { 1582 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1583 "Counter": "2", 1584 "EventCode": "0xB7", 1585 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1586 "MSRIndex": "0x1A6", 1587 "MSRValue": "0x8077", 1588 "SampleAfterValue": "100000", 1589 "UMask": "0x1" 1590 }, 1591 { 1592 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1593 "Counter": "2", 1594 "EventCode": "0xB7", 1595 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1596 "MSRIndex": "0x1A6", 1597 "MSRValue": "0x177", 1598 "SampleAfterValue": "100000", 1599 "UMask": "0x1" 1600 }, 1601 { 1602 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1603 "Counter": "2", 1604 "EventCode": "0xB7", 1605 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1606 "MSRIndex": "0x1A6", 1607 "MSRValue": "0x277", 1608 "SampleAfterValue": "100000", 1609 "UMask": "0x1" 1610 }, 1611 { 1612 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1613 "Counter": "2", 1614 "EventCode": "0xB7", 1615 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1616 "MSRIndex": "0x1A6", 1617 "MSRValue": "0x477", 1618 "SampleAfterValue": "100000", 1619 "UMask": "0x1" 1620 }, 1621 { 1622 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1623 "Counter": "2", 1624 "EventCode": "0xB7", 1625 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1626 "MSRIndex": "0x1A6", 1627 "MSRValue": "0x777", 1628 "SampleAfterValue": "100000", 1629 "UMask": "0x1" 1630 }, 1631 { 1632 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1633 "Counter": "2", 1634 "EventCode": "0xB7", 1635 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1636 "MSRIndex": "0x1A6", 1637 "MSRValue": "0x4777", 1638 "SampleAfterValue": "100000", 1639 "UMask": "0x1" 1640 }, 1641 { 1642 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1643 "Counter": "2", 1644 "EventCode": "0xB7", 1645 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1646 "MSRIndex": "0x1A6", 1647 "MSRValue": "0x1877", 1648 "SampleAfterValue": "100000", 1649 "UMask": "0x1" 1650 }, 1651 { 1652 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1653 "Counter": "2", 1654 "EventCode": "0xB7", 1655 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1656 "MSRIndex": "0x1A6", 1657 "MSRValue": "0x3877", 1658 "SampleAfterValue": "100000", 1659 "UMask": "0x1" 1660 }, 1661 { 1662 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1663 "Counter": "2", 1664 "EventCode": "0xB7", 1665 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1666 "MSRIndex": "0x1A6", 1667 "MSRValue": "0x1077", 1668 "SampleAfterValue": "100000", 1669 "UMask": "0x1" 1670 }, 1671 { 1672 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1673 "Counter": "2", 1674 "EventCode": "0xB7", 1675 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1676 "MSRIndex": "0x1A6", 1677 "MSRValue": "0x877", 1678 "SampleAfterValue": "100000", 1679 "UMask": "0x1" 1680 }, 1681 { 1682 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1683 "Counter": "2", 1684 "EventCode": "0xB7", 1685 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1686 "MSRIndex": "0x1A6", 1687 "MSRValue": "0x7F33", 1688 "SampleAfterValue": "100000", 1689 "UMask": "0x1" 1690 }, 1691 { 1692 "BriefDescription": "Offcore request = all data, response = any location", 1693 "Counter": "2", 1694 "EventCode": "0xB7", 1695 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1696 "MSRIndex": "0x1A6", 1697 "MSRValue": "0xFF33", 1698 "SampleAfterValue": "100000", 1699 "UMask": "0x1" 1700 }, 1701 { 1702 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1703 "Counter": "2", 1704 "EventCode": "0xB7", 1705 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1706 "MSRIndex": "0x1A6", 1707 "MSRValue": "0x8033", 1708 "SampleAfterValue": "100000", 1709 "UMask": "0x1" 1710 }, 1711 { 1712 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1713 "Counter": "2", 1714 "EventCode": "0xB7", 1715 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1716 "MSRIndex": "0x1A6", 1717 "MSRValue": "0x133", 1718 "SampleAfterValue": "100000", 1719 "UMask": "0x1" 1720 }, 1721 { 1722 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1723 "Counter": "2", 1724 "EventCode": "0xB7", 1725 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1726 "MSRIndex": "0x1A6", 1727 "MSRValue": "0x233", 1728 "SampleAfterValue": "100000", 1729 "UMask": "0x1" 1730 }, 1731 { 1732 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1733 "Counter": "2", 1734 "EventCode": "0xB7", 1735 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1736 "MSRIndex": "0x1A6", 1737 "MSRValue": "0x433", 1738 "SampleAfterValue": "100000", 1739 "UMask": "0x1" 1740 }, 1741 { 1742 "BriefDescription": "Offcore request = all data, response = local cache", 1743 "Counter": "2", 1744 "EventCode": "0xB7", 1745 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1746 "MSRIndex": "0x1A6", 1747 "MSRValue": "0x733", 1748 "SampleAfterValue": "100000", 1749 "UMask": "0x1" 1750 }, 1751 { 1752 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1753 "Counter": "2", 1754 "EventCode": "0xB7", 1755 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1756 "MSRIndex": "0x1A6", 1757 "MSRValue": "0x4733", 1758 "SampleAfterValue": "100000", 1759 "UMask": "0x1" 1760 }, 1761 { 1762 "BriefDescription": "Offcore request = all data, response = remote cache", 1763 "Counter": "2", 1764 "EventCode": "0xB7", 1765 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1766 "MSRIndex": "0x1A6", 1767 "MSRValue": "0x1833", 1768 "SampleAfterValue": "100000", 1769 "UMask": "0x1" 1770 }, 1771 { 1772 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1773 "Counter": "2", 1774 "EventCode": "0xB7", 1775 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1776 "MSRIndex": "0x1A6", 1777 "MSRValue": "0x3833", 1778 "SampleAfterValue": "100000", 1779 "UMask": "0x1" 1780 }, 1781 { 1782 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1783 "Counter": "2", 1784 "EventCode": "0xB7", 1785 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1786 "MSRIndex": "0x1A6", 1787 "MSRValue": "0x1033", 1788 "SampleAfterValue": "100000", 1789 "UMask": "0x1" 1790 }, 1791 { 1792 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1793 "Counter": "2", 1794 "EventCode": "0xB7", 1795 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1796 "MSRIndex": "0x1A6", 1797 "MSRValue": "0x833", 1798 "SampleAfterValue": "100000", 1799 "UMask": "0x1" 1800 }, 1801 { 1802 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1803 "Counter": "2", 1804 "EventCode": "0xB7", 1805 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1806 "MSRIndex": "0x1A6", 1807 "MSRValue": "0x7F03", 1808 "SampleAfterValue": "100000", 1809 "UMask": "0x1" 1810 }, 1811 { 1812 "BriefDescription": "All offcore demand data requests", 1813 "Counter": "2", 1814 "EventCode": "0xB7", 1815 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1816 "MSRIndex": "0x1A6", 1817 "MSRValue": "0xFF03", 1818 "SampleAfterValue": "100000", 1819 "UMask": "0x1" 1820 }, 1821 { 1822 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1823 "Counter": "2", 1824 "EventCode": "0xB7", 1825 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1826 "MSRIndex": "0x1A6", 1827 "MSRValue": "0x8003", 1828 "SampleAfterValue": "100000", 1829 "UMask": "0x1" 1830 }, 1831 { 1832 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1833 "Counter": "2", 1834 "EventCode": "0xB7", 1835 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1836 "MSRIndex": "0x1A6", 1837 "MSRValue": "0x103", 1838 "SampleAfterValue": "100000", 1839 "UMask": "0x1" 1840 }, 1841 { 1842 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1843 "Counter": "2", 1844 "EventCode": "0xB7", 1845 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1846 "MSRIndex": "0x1A6", 1847 "MSRValue": "0x203", 1848 "SampleAfterValue": "100000", 1849 "UMask": "0x1" 1850 }, 1851 { 1852 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1853 "Counter": "2", 1854 "EventCode": "0xB7", 1855 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1856 "MSRIndex": "0x1A6", 1857 "MSRValue": "0x403", 1858 "SampleAfterValue": "100000", 1859 "UMask": "0x1" 1860 }, 1861 { 1862 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1863 "Counter": "2", 1864 "EventCode": "0xB7", 1865 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1866 "MSRIndex": "0x1A6", 1867 "MSRValue": "0x703", 1868 "SampleAfterValue": "100000", 1869 "UMask": "0x1" 1870 }, 1871 { 1872 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1873 "Counter": "2", 1874 "EventCode": "0xB7", 1875 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1876 "MSRIndex": "0x1A6", 1877 "MSRValue": "0x4703", 1878 "SampleAfterValue": "100000", 1879 "UMask": "0x1" 1880 }, 1881 { 1882 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1883 "Counter": "2", 1884 "EventCode": "0xB7", 1885 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1886 "MSRIndex": "0x1A6", 1887 "MSRValue": "0x1803", 1888 "SampleAfterValue": "100000", 1889 "UMask": "0x1" 1890 }, 1891 { 1892 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1893 "Counter": "2", 1894 "EventCode": "0xB7", 1895 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1896 "MSRIndex": "0x1A6", 1897 "MSRValue": "0x3803", 1898 "SampleAfterValue": "100000", 1899 "UMask": "0x1" 1900 }, 1901 { 1902 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1903 "Counter": "2", 1904 "EventCode": "0xB7", 1905 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1906 "MSRIndex": "0x1A6", 1907 "MSRValue": "0x1003", 1908 "SampleAfterValue": "100000", 1909 "UMask": "0x1" 1910 }, 1911 { 1912 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1913 "Counter": "2", 1914 "EventCode": "0xB7", 1915 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1916 "MSRIndex": "0x1A6", 1917 "MSRValue": "0x803", 1918 "SampleAfterValue": "100000", 1919 "UMask": "0x1" 1920 }, 1921 { 1922 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1923 "Counter": "2", 1924 "EventCode": "0xB7", 1925 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1926 "MSRIndex": "0x1A6", 1927 "MSRValue": "0x7F01", 1928 "SampleAfterValue": "100000", 1929 "UMask": "0x1" 1930 }, 1931 { 1932 "BriefDescription": "All offcore demand data reads", 1933 "Counter": "2", 1934 "EventCode": "0xB7", 1935 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1936 "MSRIndex": "0x1A6", 1937 "MSRValue": "0xFF01", 1938 "SampleAfterValue": "100000", 1939 "UMask": "0x1" 1940 }, 1941 { 1942 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1943 "Counter": "2", 1944 "EventCode": "0xB7", 1945 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1946 "MSRIndex": "0x1A6", 1947 "MSRValue": "0x8001", 1948 "SampleAfterValue": "100000", 1949 "UMask": "0x1" 1950 }, 1951 { 1952 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1953 "Counter": "2", 1954 "EventCode": "0xB7", 1955 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1956 "MSRIndex": "0x1A6", 1957 "MSRValue": "0x101", 1958 "SampleAfterValue": "100000", 1959 "UMask": "0x1" 1960 }, 1961 { 1962 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1963 "Counter": "2", 1964 "EventCode": "0xB7", 1965 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1966 "MSRIndex": "0x1A6", 1967 "MSRValue": "0x201", 1968 "SampleAfterValue": "100000", 1969 "UMask": "0x1" 1970 }, 1971 { 1972 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1973 "Counter": "2", 1974 "EventCode": "0xB7", 1975 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1976 "MSRIndex": "0x1A6", 1977 "MSRValue": "0x401", 1978 "SampleAfterValue": "100000", 1979 "UMask": "0x1" 1980 }, 1981 { 1982 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1983 "Counter": "2", 1984 "EventCode": "0xB7", 1985 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1986 "MSRIndex": "0x1A6", 1987 "MSRValue": "0x701", 1988 "SampleAfterValue": "100000", 1989 "UMask": "0x1" 1990 }, 1991 { 1992 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1993 "Counter": "2", 1994 "EventCode": "0xB7", 1995 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1996 "MSRIndex": "0x1A6", 1997 "MSRValue": "0x4701", 1998 "SampleAfterValue": "100000", 1999 "UMask": "0x1" 2000 }, 2001 { 2002 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 2003 "Counter": "2", 2004 "EventCode": "0xB7", 2005 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 2006 "MSRIndex": "0x1A6", 2007 "MSRValue": "0x1801", 2008 "SampleAfterValue": "100000", 2009 "UMask": "0x1" 2010 }, 2011 { 2012 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 2013 "Counter": "2", 2014 "EventCode": "0xB7", 2015 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 2016 "MSRIndex": "0x1A6", 2017 "MSRValue": "0x3801", 2018 "SampleAfterValue": "100000", 2019 "UMask": "0x1" 2020 }, 2021 { 2022 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 2023 "Counter": "2", 2024 "EventCode": "0xB7", 2025 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 2026 "MSRIndex": "0x1A6", 2027 "MSRValue": "0x1001", 2028 "SampleAfterValue": "100000", 2029 "UMask": "0x1" 2030 }, 2031 { 2032 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 2033 "Counter": "2", 2034 "EventCode": "0xB7", 2035 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 2036 "MSRIndex": "0x1A6", 2037 "MSRValue": "0x801", 2038 "SampleAfterValue": "100000", 2039 "UMask": "0x1" 2040 }, 2041 { 2042 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 2043 "Counter": "2", 2044 "EventCode": "0xB7", 2045 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 2046 "MSRIndex": "0x1A6", 2047 "MSRValue": "0x7F04", 2048 "SampleAfterValue": "100000", 2049 "UMask": "0x1" 2050 }, 2051 { 2052 "BriefDescription": "All offcore demand code reads", 2053 "Counter": "2", 2054 "EventCode": "0xB7", 2055 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 2056 "MSRIndex": "0x1A6", 2057 "MSRValue": "0xFF04", 2058 "SampleAfterValue": "100000", 2059 "UMask": "0x1" 2060 }, 2061 { 2062 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 2063 "Counter": "2", 2064 "EventCode": "0xB7", 2065 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 2066 "MSRIndex": "0x1A6", 2067 "MSRValue": "0x8004", 2068 "SampleAfterValue": "100000", 2069 "UMask": "0x1" 2070 }, 2071 { 2072 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 2073 "Counter": "2", 2074 "EventCode": "0xB7", 2075 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 2076 "MSRIndex": "0x1A6", 2077 "MSRValue": "0x104", 2078 "SampleAfterValue": "100000", 2079 "UMask": "0x1" 2080 }, 2081 { 2082 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 2083 "Counter": "2", 2084 "EventCode": "0xB7", 2085 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2086 "MSRIndex": "0x1A6", 2087 "MSRValue": "0x204", 2088 "SampleAfterValue": "100000", 2089 "UMask": "0x1" 2090 }, 2091 { 2092 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 2093 "Counter": "2", 2094 "EventCode": "0xB7", 2095 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2096 "MSRIndex": "0x1A6", 2097 "MSRValue": "0x404", 2098 "SampleAfterValue": "100000", 2099 "UMask": "0x1" 2100 }, 2101 { 2102 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 2103 "Counter": "2", 2104 "EventCode": "0xB7", 2105 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 2106 "MSRIndex": "0x1A6", 2107 "MSRValue": "0x704", 2108 "SampleAfterValue": "100000", 2109 "UMask": "0x1" 2110 }, 2111 { 2112 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 2113 "Counter": "2", 2114 "EventCode": "0xB7", 2115 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 2116 "MSRIndex": "0x1A6", 2117 "MSRValue": "0x4704", 2118 "SampleAfterValue": "100000", 2119 "UMask": "0x1" 2120 }, 2121 { 2122 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 2123 "Counter": "2", 2124 "EventCode": "0xB7", 2125 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 2126 "MSRIndex": "0x1A6", 2127 "MSRValue": "0x1804", 2128 "SampleAfterValue": "100000", 2129 "UMask": "0x1" 2130 }, 2131 { 2132 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 2133 "Counter": "2", 2134 "EventCode": "0xB7", 2135 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 2136 "MSRIndex": "0x1A6", 2137 "MSRValue": "0x3804", 2138 "SampleAfterValue": "100000", 2139 "UMask": "0x1" 2140 }, 2141 { 2142 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 2143 "Counter": "2", 2144 "EventCode": "0xB7", 2145 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 2146 "MSRIndex": "0x1A6", 2147 "MSRValue": "0x1004", 2148 "SampleAfterValue": "100000", 2149 "UMask": "0x1" 2150 }, 2151 { 2152 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 2153 "Counter": "2", 2154 "EventCode": "0xB7", 2155 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 2156 "MSRIndex": "0x1A6", 2157 "MSRValue": "0x804", 2158 "SampleAfterValue": "100000", 2159 "UMask": "0x1" 2160 }, 2161 { 2162 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 2163 "Counter": "2", 2164 "EventCode": "0xB7", 2165 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 2166 "MSRIndex": "0x1A6", 2167 "MSRValue": "0x7F02", 2168 "SampleAfterValue": "100000", 2169 "UMask": "0x1" 2170 }, 2171 { 2172 "BriefDescription": "All offcore demand RFO requests", 2173 "Counter": "2", 2174 "EventCode": "0xB7", 2175 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 2176 "MSRIndex": "0x1A6", 2177 "MSRValue": "0xFF02", 2178 "SampleAfterValue": "100000", 2179 "UMask": "0x1" 2180 }, 2181 { 2182 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 2183 "Counter": "2", 2184 "EventCode": "0xB7", 2185 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 2186 "MSRIndex": "0x1A6", 2187 "MSRValue": "0x8002", 2188 "SampleAfterValue": "100000", 2189 "UMask": "0x1" 2190 }, 2191 { 2192 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 2193 "Counter": "2", 2194 "EventCode": "0xB7", 2195 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 2196 "MSRIndex": "0x1A6", 2197 "MSRValue": "0x102", 2198 "SampleAfterValue": "100000", 2199 "UMask": "0x1" 2200 }, 2201 { 2202 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 2203 "Counter": "2", 2204 "EventCode": "0xB7", 2205 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 2206 "MSRIndex": "0x1A6", 2207 "MSRValue": "0x202", 2208 "SampleAfterValue": "100000", 2209 "UMask": "0x1" 2210 }, 2211 { 2212 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 2213 "Counter": "2", 2214 "EventCode": "0xB7", 2215 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 2216 "MSRIndex": "0x1A6", 2217 "MSRValue": "0x402", 2218 "SampleAfterValue": "100000", 2219 "UMask": "0x1" 2220 }, 2221 { 2222 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 2223 "Counter": "2", 2224 "EventCode": "0xB7", 2225 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 2226 "MSRIndex": "0x1A6", 2227 "MSRValue": "0x702", 2228 "SampleAfterValue": "100000", 2229 "UMask": "0x1" 2230 }, 2231 { 2232 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 2233 "Counter": "2", 2234 "EventCode": "0xB7", 2235 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 2236 "MSRIndex": "0x1A6", 2237 "MSRValue": "0x4702", 2238 "SampleAfterValue": "100000", 2239 "UMask": "0x1" 2240 }, 2241 { 2242 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2243 "Counter": "2", 2244 "EventCode": "0xB7", 2245 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2246 "MSRIndex": "0x1A6", 2247 "MSRValue": "0x1802", 2248 "SampleAfterValue": "100000", 2249 "UMask": "0x1" 2250 }, 2251 { 2252 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2253 "Counter": "2", 2254 "EventCode": "0xB7", 2255 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2256 "MSRIndex": "0x1A6", 2257 "MSRValue": "0x3802", 2258 "SampleAfterValue": "100000", 2259 "UMask": "0x1" 2260 }, 2261 { 2262 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2263 "Counter": "2", 2264 "EventCode": "0xB7", 2265 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2266 "MSRIndex": "0x1A6", 2267 "MSRValue": "0x1002", 2268 "SampleAfterValue": "100000", 2269 "UMask": "0x1" 2270 }, 2271 { 2272 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2273 "Counter": "2", 2274 "EventCode": "0xB7", 2275 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2276 "MSRIndex": "0x1A6", 2277 "MSRValue": "0x802", 2278 "SampleAfterValue": "100000", 2279 "UMask": "0x1" 2280 }, 2281 { 2282 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2283 "Counter": "2", 2284 "EventCode": "0xB7", 2285 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2286 "MSRIndex": "0x1A6", 2287 "MSRValue": "0x7F80", 2288 "SampleAfterValue": "100000", 2289 "UMask": "0x1" 2290 }, 2291 { 2292 "BriefDescription": "All offcore other requests", 2293 "Counter": "2", 2294 "EventCode": "0xB7", 2295 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2296 "MSRIndex": "0x1A6", 2297 "MSRValue": "0xFF80", 2298 "SampleAfterValue": "100000", 2299 "UMask": "0x1" 2300 }, 2301 { 2302 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2303 "Counter": "2", 2304 "EventCode": "0xB7", 2305 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2306 "MSRIndex": "0x1A6", 2307 "MSRValue": "0x8080", 2308 "SampleAfterValue": "100000", 2309 "UMask": "0x1" 2310 }, 2311 { 2312 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2313 "Counter": "2", 2314 "EventCode": "0xB7", 2315 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2316 "MSRIndex": "0x1A6", 2317 "MSRValue": "0x180", 2318 "SampleAfterValue": "100000", 2319 "UMask": "0x1" 2320 }, 2321 { 2322 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2323 "Counter": "2", 2324 "EventCode": "0xB7", 2325 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2326 "MSRIndex": "0x1A6", 2327 "MSRValue": "0x280", 2328 "SampleAfterValue": "100000", 2329 "UMask": "0x1" 2330 }, 2331 { 2332 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2333 "Counter": "2", 2334 "EventCode": "0xB7", 2335 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2336 "MSRIndex": "0x1A6", 2337 "MSRValue": "0x480", 2338 "SampleAfterValue": "100000", 2339 "UMask": "0x1" 2340 }, 2341 { 2342 "BriefDescription": "Offcore other requests satisfied by the LLC", 2343 "Counter": "2", 2344 "EventCode": "0xB7", 2345 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2346 "MSRIndex": "0x1A6", 2347 "MSRValue": "0x780", 2348 "SampleAfterValue": "100000", 2349 "UMask": "0x1" 2350 }, 2351 { 2352 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2353 "Counter": "2", 2354 "EventCode": "0xB7", 2355 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2356 "MSRIndex": "0x1A6", 2357 "MSRValue": "0x4780", 2358 "SampleAfterValue": "100000", 2359 "UMask": "0x1" 2360 }, 2361 { 2362 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2363 "Counter": "2", 2364 "EventCode": "0xB7", 2365 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2366 "MSRIndex": "0x1A6", 2367 "MSRValue": "0x1880", 2368 "SampleAfterValue": "100000", 2369 "UMask": "0x1" 2370 }, 2371 { 2372 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2373 "Counter": "2", 2374 "EventCode": "0xB7", 2375 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2376 "MSRIndex": "0x1A6", 2377 "MSRValue": "0x3880", 2378 "SampleAfterValue": "100000", 2379 "UMask": "0x1" 2380 }, 2381 { 2382 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2383 "Counter": "2", 2384 "EventCode": "0xB7", 2385 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2386 "MSRIndex": "0x1A6", 2387 "MSRValue": "0x1080", 2388 "SampleAfterValue": "100000", 2389 "UMask": "0x1" 2390 }, 2391 { 2392 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2393 "Counter": "2", 2394 "EventCode": "0xB7", 2395 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2396 "MSRIndex": "0x1A6", 2397 "MSRValue": "0x880", 2398 "SampleAfterValue": "100000", 2399 "UMask": "0x1" 2400 }, 2401 { 2402 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2403 "Counter": "2", 2404 "EventCode": "0xB7", 2405 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2406 "MSRIndex": "0x1A6", 2407 "MSRValue": "0x7F30", 2408 "SampleAfterValue": "100000", 2409 "UMask": "0x1" 2410 }, 2411 { 2412 "BriefDescription": "All offcore prefetch data requests", 2413 "Counter": "2", 2414 "EventCode": "0xB7", 2415 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2416 "MSRIndex": "0x1A6", 2417 "MSRValue": "0xFF30", 2418 "SampleAfterValue": "100000", 2419 "UMask": "0x1" 2420 }, 2421 { 2422 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2423 "Counter": "2", 2424 "EventCode": "0xB7", 2425 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2426 "MSRIndex": "0x1A6", 2427 "MSRValue": "0x8030", 2428 "SampleAfterValue": "100000", 2429 "UMask": "0x1" 2430 }, 2431 { 2432 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2433 "Counter": "2", 2434 "EventCode": "0xB7", 2435 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2436 "MSRIndex": "0x1A6", 2437 "MSRValue": "0x130", 2438 "SampleAfterValue": "100000", 2439 "UMask": "0x1" 2440 }, 2441 { 2442 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2443 "Counter": "2", 2444 "EventCode": "0xB7", 2445 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2446 "MSRIndex": "0x1A6", 2447 "MSRValue": "0x230", 2448 "SampleAfterValue": "100000", 2449 "UMask": "0x1" 2450 }, 2451 { 2452 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2453 "Counter": "2", 2454 "EventCode": "0xB7", 2455 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2456 "MSRIndex": "0x1A6", 2457 "MSRValue": "0x430", 2458 "SampleAfterValue": "100000", 2459 "UMask": "0x1" 2460 }, 2461 { 2462 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2463 "Counter": "2", 2464 "EventCode": "0xB7", 2465 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2466 "MSRIndex": "0x1A6", 2467 "MSRValue": "0x730", 2468 "SampleAfterValue": "100000", 2469 "UMask": "0x1" 2470 }, 2471 { 2472 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2473 "Counter": "2", 2474 "EventCode": "0xB7", 2475 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2476 "MSRIndex": "0x1A6", 2477 "MSRValue": "0x4730", 2478 "SampleAfterValue": "100000", 2479 "UMask": "0x1" 2480 }, 2481 { 2482 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2483 "Counter": "2", 2484 "EventCode": "0xB7", 2485 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2486 "MSRIndex": "0x1A6", 2487 "MSRValue": "0x1830", 2488 "SampleAfterValue": "100000", 2489 "UMask": "0x1" 2490 }, 2491 { 2492 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2493 "Counter": "2", 2494 "EventCode": "0xB7", 2495 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2496 "MSRIndex": "0x1A6", 2497 "MSRValue": "0x3830", 2498 "SampleAfterValue": "100000", 2499 "UMask": "0x1" 2500 }, 2501 { 2502 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2503 "Counter": "2", 2504 "EventCode": "0xB7", 2505 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2506 "MSRIndex": "0x1A6", 2507 "MSRValue": "0x1030", 2508 "SampleAfterValue": "100000", 2509 "UMask": "0x1" 2510 }, 2511 { 2512 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2513 "Counter": "2", 2514 "EventCode": "0xB7", 2515 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2516 "MSRIndex": "0x1A6", 2517 "MSRValue": "0x830", 2518 "SampleAfterValue": "100000", 2519 "UMask": "0x1" 2520 }, 2521 { 2522 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2523 "Counter": "2", 2524 "EventCode": "0xB7", 2525 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2526 "MSRIndex": "0x1A6", 2527 "MSRValue": "0x7F10", 2528 "SampleAfterValue": "100000", 2529 "UMask": "0x1" 2530 }, 2531 { 2532 "BriefDescription": "All offcore prefetch data reads", 2533 "Counter": "2", 2534 "EventCode": "0xB7", 2535 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2536 "MSRIndex": "0x1A6", 2537 "MSRValue": "0xFF10", 2538 "SampleAfterValue": "100000", 2539 "UMask": "0x1" 2540 }, 2541 { 2542 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2543 "Counter": "2", 2544 "EventCode": "0xB7", 2545 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2546 "MSRIndex": "0x1A6", 2547 "MSRValue": "0x8010", 2548 "SampleAfterValue": "100000", 2549 "UMask": "0x1" 2550 }, 2551 { 2552 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2553 "Counter": "2", 2554 "EventCode": "0xB7", 2555 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2556 "MSRIndex": "0x1A6", 2557 "MSRValue": "0x110", 2558 "SampleAfterValue": "100000", 2559 "UMask": "0x1" 2560 }, 2561 { 2562 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2563 "Counter": "2", 2564 "EventCode": "0xB7", 2565 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2566 "MSRIndex": "0x1A6", 2567 "MSRValue": "0x210", 2568 "SampleAfterValue": "100000", 2569 "UMask": "0x1" 2570 }, 2571 { 2572 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2573 "Counter": "2", 2574 "EventCode": "0xB7", 2575 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2576 "MSRIndex": "0x1A6", 2577 "MSRValue": "0x410", 2578 "SampleAfterValue": "100000", 2579 "UMask": "0x1" 2580 }, 2581 { 2582 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2583 "Counter": "2", 2584 "EventCode": "0xB7", 2585 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2586 "MSRIndex": "0x1A6", 2587 "MSRValue": "0x710", 2588 "SampleAfterValue": "100000", 2589 "UMask": "0x1" 2590 }, 2591 { 2592 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2593 "Counter": "2", 2594 "EventCode": "0xB7", 2595 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2596 "MSRIndex": "0x1A6", 2597 "MSRValue": "0x4710", 2598 "SampleAfterValue": "100000", 2599 "UMask": "0x1" 2600 }, 2601 { 2602 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2603 "Counter": "2", 2604 "EventCode": "0xB7", 2605 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2606 "MSRIndex": "0x1A6", 2607 "MSRValue": "0x1810", 2608 "SampleAfterValue": "100000", 2609 "UMask": "0x1" 2610 }, 2611 { 2612 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2613 "Counter": "2", 2614 "EventCode": "0xB7", 2615 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2616 "MSRIndex": "0x1A6", 2617 "MSRValue": "0x3810", 2618 "SampleAfterValue": "100000", 2619 "UMask": "0x1" 2620 }, 2621 { 2622 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2623 "Counter": "2", 2624 "EventCode": "0xB7", 2625 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2626 "MSRIndex": "0x1A6", 2627 "MSRValue": "0x1010", 2628 "SampleAfterValue": "100000", 2629 "UMask": "0x1" 2630 }, 2631 { 2632 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2633 "Counter": "2", 2634 "EventCode": "0xB7", 2635 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2636 "MSRIndex": "0x1A6", 2637 "MSRValue": "0x810", 2638 "SampleAfterValue": "100000", 2639 "UMask": "0x1" 2640 }, 2641 { 2642 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2643 "Counter": "2", 2644 "EventCode": "0xB7", 2645 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2646 "MSRIndex": "0x1A6", 2647 "MSRValue": "0x7F40", 2648 "SampleAfterValue": "100000", 2649 "UMask": "0x1" 2650 }, 2651 { 2652 "BriefDescription": "All offcore prefetch code reads", 2653 "Counter": "2", 2654 "EventCode": "0xB7", 2655 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2656 "MSRIndex": "0x1A6", 2657 "MSRValue": "0xFF40", 2658 "SampleAfterValue": "100000", 2659 "UMask": "0x1" 2660 }, 2661 { 2662 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2663 "Counter": "2", 2664 "EventCode": "0xB7", 2665 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2666 "MSRIndex": "0x1A6", 2667 "MSRValue": "0x8040", 2668 "SampleAfterValue": "100000", 2669 "UMask": "0x1" 2670 }, 2671 { 2672 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2673 "Counter": "2", 2674 "EventCode": "0xB7", 2675 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2676 "MSRIndex": "0x1A6", 2677 "MSRValue": "0x140", 2678 "SampleAfterValue": "100000", 2679 "UMask": "0x1" 2680 }, 2681 { 2682 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2683 "Counter": "2", 2684 "EventCode": "0xB7", 2685 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2686 "MSRIndex": "0x1A6", 2687 "MSRValue": "0x240", 2688 "SampleAfterValue": "100000", 2689 "UMask": "0x1" 2690 }, 2691 { 2692 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2693 "Counter": "2", 2694 "EventCode": "0xB7", 2695 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2696 "MSRIndex": "0x1A6", 2697 "MSRValue": "0x440", 2698 "SampleAfterValue": "100000", 2699 "UMask": "0x1" 2700 }, 2701 { 2702 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2703 "Counter": "2", 2704 "EventCode": "0xB7", 2705 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2706 "MSRIndex": "0x1A6", 2707 "MSRValue": "0x740", 2708 "SampleAfterValue": "100000", 2709 "UMask": "0x1" 2710 }, 2711 { 2712 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2713 "Counter": "2", 2714 "EventCode": "0xB7", 2715 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2716 "MSRIndex": "0x1A6", 2717 "MSRValue": "0x4740", 2718 "SampleAfterValue": "100000", 2719 "UMask": "0x1" 2720 }, 2721 { 2722 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2723 "Counter": "2", 2724 "EventCode": "0xB7", 2725 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2726 "MSRIndex": "0x1A6", 2727 "MSRValue": "0x1840", 2728 "SampleAfterValue": "100000", 2729 "UMask": "0x1" 2730 }, 2731 { 2732 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2733 "Counter": "2", 2734 "EventCode": "0xB7", 2735 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2736 "MSRIndex": "0x1A6", 2737 "MSRValue": "0x3840", 2738 "SampleAfterValue": "100000", 2739 "UMask": "0x1" 2740 }, 2741 { 2742 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2743 "Counter": "2", 2744 "EventCode": "0xB7", 2745 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2746 "MSRIndex": "0x1A6", 2747 "MSRValue": "0x1040", 2748 "SampleAfterValue": "100000", 2749 "UMask": "0x1" 2750 }, 2751 { 2752 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2753 "Counter": "2", 2754 "EventCode": "0xB7", 2755 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2756 "MSRIndex": "0x1A6", 2757 "MSRValue": "0x840", 2758 "SampleAfterValue": "100000", 2759 "UMask": "0x1" 2760 }, 2761 { 2762 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2763 "Counter": "2", 2764 "EventCode": "0xB7", 2765 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2766 "MSRIndex": "0x1A6", 2767 "MSRValue": "0x7F20", 2768 "SampleAfterValue": "100000", 2769 "UMask": "0x1" 2770 }, 2771 { 2772 "BriefDescription": "All offcore prefetch RFO requests", 2773 "Counter": "2", 2774 "EventCode": "0xB7", 2775 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2776 "MSRIndex": "0x1A6", 2777 "MSRValue": "0xFF20", 2778 "SampleAfterValue": "100000", 2779 "UMask": "0x1" 2780 }, 2781 { 2782 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2783 "Counter": "2", 2784 "EventCode": "0xB7", 2785 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2786 "MSRIndex": "0x1A6", 2787 "MSRValue": "0x8020", 2788 "SampleAfterValue": "100000", 2789 "UMask": "0x1" 2790 }, 2791 { 2792 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2793 "Counter": "2", 2794 "EventCode": "0xB7", 2795 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2796 "MSRIndex": "0x1A6", 2797 "MSRValue": "0x120", 2798 "SampleAfterValue": "100000", 2799 "UMask": "0x1" 2800 }, 2801 { 2802 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2803 "Counter": "2", 2804 "EventCode": "0xB7", 2805 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2806 "MSRIndex": "0x1A6", 2807 "MSRValue": "0x220", 2808 "SampleAfterValue": "100000", 2809 "UMask": "0x1" 2810 }, 2811 { 2812 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2813 "Counter": "2", 2814 "EventCode": "0xB7", 2815 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2816 "MSRIndex": "0x1A6", 2817 "MSRValue": "0x420", 2818 "SampleAfterValue": "100000", 2819 "UMask": "0x1" 2820 }, 2821 { 2822 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2823 "Counter": "2", 2824 "EventCode": "0xB7", 2825 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2826 "MSRIndex": "0x1A6", 2827 "MSRValue": "0x720", 2828 "SampleAfterValue": "100000", 2829 "UMask": "0x1" 2830 }, 2831 { 2832 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2833 "Counter": "2", 2834 "EventCode": "0xB7", 2835 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2836 "MSRIndex": "0x1A6", 2837 "MSRValue": "0x4720", 2838 "SampleAfterValue": "100000", 2839 "UMask": "0x1" 2840 }, 2841 { 2842 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2843 "Counter": "2", 2844 "EventCode": "0xB7", 2845 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2846 "MSRIndex": "0x1A6", 2847 "MSRValue": "0x1820", 2848 "SampleAfterValue": "100000", 2849 "UMask": "0x1" 2850 }, 2851 { 2852 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2853 "Counter": "2", 2854 "EventCode": "0xB7", 2855 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2856 "MSRIndex": "0x1A6", 2857 "MSRValue": "0x3820", 2858 "SampleAfterValue": "100000", 2859 "UMask": "0x1" 2860 }, 2861 { 2862 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2863 "Counter": "2", 2864 "EventCode": "0xB7", 2865 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2866 "MSRIndex": "0x1A6", 2867 "MSRValue": "0x1020", 2868 "SampleAfterValue": "100000", 2869 "UMask": "0x1" 2870 }, 2871 { 2872 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2873 "Counter": "2", 2874 "EventCode": "0xB7", 2875 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2876 "MSRIndex": "0x1A6", 2877 "MSRValue": "0x820", 2878 "SampleAfterValue": "100000", 2879 "UMask": "0x1" 2880 }, 2881 { 2882 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2883 "Counter": "2", 2884 "EventCode": "0xB7", 2885 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2886 "MSRIndex": "0x1A6", 2887 "MSRValue": "0x7F70", 2888 "SampleAfterValue": "100000", 2889 "UMask": "0x1" 2890 }, 2891 { 2892 "BriefDescription": "All offcore prefetch requests", 2893 "Counter": "2", 2894 "EventCode": "0xB7", 2895 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2896 "MSRIndex": "0x1A6", 2897 "MSRValue": "0xFF70", 2898 "SampleAfterValue": "100000", 2899 "UMask": "0x1" 2900 }, 2901 { 2902 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2903 "Counter": "2", 2904 "EventCode": "0xB7", 2905 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2906 "MSRIndex": "0x1A6", 2907 "MSRValue": "0x8070", 2908 "SampleAfterValue": "100000", 2909 "UMask": "0x1" 2910 }, 2911 { 2912 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2913 "Counter": "2", 2914 "EventCode": "0xB7", 2915 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2916 "MSRIndex": "0x1A6", 2917 "MSRValue": "0x170", 2918 "SampleAfterValue": "100000", 2919 "UMask": "0x1" 2920 }, 2921 { 2922 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2923 "Counter": "2", 2924 "EventCode": "0xB7", 2925 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2926 "MSRIndex": "0x1A6", 2927 "MSRValue": "0x270", 2928 "SampleAfterValue": "100000", 2929 "UMask": "0x1" 2930 }, 2931 { 2932 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2933 "Counter": "2", 2934 "EventCode": "0xB7", 2935 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2936 "MSRIndex": "0x1A6", 2937 "MSRValue": "0x470", 2938 "SampleAfterValue": "100000", 2939 "UMask": "0x1" 2940 }, 2941 { 2942 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2943 "Counter": "2", 2944 "EventCode": "0xB7", 2945 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2946 "MSRIndex": "0x1A6", 2947 "MSRValue": "0x770", 2948 "SampleAfterValue": "100000", 2949 "UMask": "0x1" 2950 }, 2951 { 2952 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2953 "Counter": "2", 2954 "EventCode": "0xB7", 2955 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2956 "MSRIndex": "0x1A6", 2957 "MSRValue": "0x4770", 2958 "SampleAfterValue": "100000", 2959 "UMask": "0x1" 2960 }, 2961 { 2962 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2963 "Counter": "2", 2964 "EventCode": "0xB7", 2965 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2966 "MSRIndex": "0x1A6", 2967 "MSRValue": "0x1870", 2968 "SampleAfterValue": "100000", 2969 "UMask": "0x1" 2970 }, 2971 { 2972 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2973 "Counter": "2", 2974 "EventCode": "0xB7", 2975 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2976 "MSRIndex": "0x1A6", 2977 "MSRValue": "0x3870", 2978 "SampleAfterValue": "100000", 2979 "UMask": "0x1" 2980 }, 2981 { 2982 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2983 "Counter": "2", 2984 "EventCode": "0xB7", 2985 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2986 "MSRIndex": "0x1A6", 2987 "MSRValue": "0x1070", 2988 "SampleAfterValue": "100000", 2989 "UMask": "0x1" 2990 }, 2991 { 2992 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2993 "Counter": "2", 2994 "EventCode": "0xB7", 2995 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2996 "MSRIndex": "0x1A6", 2997 "MSRValue": "0x870", 2998 "SampleAfterValue": "100000", 2999 "UMask": "0x1" 3000 }, 3001 { 3002 "BriefDescription": "Super Queue lock splits across a cache line", 3003 "Counter": "0,1,2,3", 3004 "EventCode": "0xF4", 3005 "EventName": "SQ_MISC.SPLIT_LOCK", 3006 "SampleAfterValue": "2000000", 3007 "UMask": "0x10" 3008 }, 3009 { 3010 "BriefDescription": "Loads delayed with at-Retirement block code", 3011 "Counter": "0,1,2,3", 3012 "EventCode": "0x6", 3013 "EventName": "STORE_BLOCKS.AT_RET", 3014 "SampleAfterValue": "200000", 3015 "UMask": "0x4" 3016 }, 3017 { 3018 "BriefDescription": "Cacheable loads delayed with L1D block code", 3019 "Counter": "0,1,2,3", 3020 "EventCode": "0x6", 3021 "EventName": "STORE_BLOCKS.L1D_BLOCK", 3022 "SampleAfterValue": "200000", 3023 "UMask": "0x8" 3024 } 3025] 3026