1[ 2 { 3 "BriefDescription": "Cycles L1D locked", 4 "EventCode": "0x63", 5 "EventName": "CACHE_LOCK_CYCLES.L1D", 6 "SampleAfterValue": "2000000", 7 "UMask": "0x2" 8 }, 9 { 10 "BriefDescription": "Cycles L1D and L2 locked", 11 "EventCode": "0x63", 12 "EventName": "CACHE_LOCK_CYCLES.L1D_L2", 13 "SampleAfterValue": "2000000", 14 "UMask": "0x1" 15 }, 16 { 17 "BriefDescription": "L1D cache lines replaced in M state", 18 "EventCode": "0x51", 19 "EventName": "L1D.M_EVICT", 20 "SampleAfterValue": "2000000", 21 "UMask": "0x4" 22 }, 23 { 24 "BriefDescription": "L1D cache lines allocated in the M state", 25 "EventCode": "0x51", 26 "EventName": "L1D.M_REPL", 27 "SampleAfterValue": "2000000", 28 "UMask": "0x2" 29 }, 30 { 31 "BriefDescription": "L1D snoop eviction of cache lines in M state", 32 "EventCode": "0x51", 33 "EventName": "L1D.M_SNOOP_EVICT", 34 "SampleAfterValue": "2000000", 35 "UMask": "0x8" 36 }, 37 { 38 "BriefDescription": "L1 data cache lines allocated", 39 "EventCode": "0x51", 40 "EventName": "L1D.REPL", 41 "SampleAfterValue": "2000000", 42 "UMask": "0x1" 43 }, 44 { 45 "BriefDescription": "All references to the L1 data cache", 46 "EventCode": "0x43", 47 "EventName": "L1D_ALL_REF.ANY", 48 "SampleAfterValue": "2000000", 49 "UMask": "0x1" 50 }, 51 { 52 "BriefDescription": "L1 data cacheable reads and writes", 53 "EventCode": "0x43", 54 "EventName": "L1D_ALL_REF.CACHEABLE", 55 "SampleAfterValue": "2000000", 56 "UMask": "0x2" 57 }, 58 { 59 "BriefDescription": "L1 data cache read in E state", 60 "EventCode": "0x40", 61 "EventName": "L1D_CACHE_LD.E_STATE", 62 "SampleAfterValue": "2000000", 63 "UMask": "0x4" 64 }, 65 { 66 "BriefDescription": "L1 data cache read in I state (misses)", 67 "EventCode": "0x40", 68 "EventName": "L1D_CACHE_LD.I_STATE", 69 "SampleAfterValue": "2000000", 70 "UMask": "0x1" 71 }, 72 { 73 "BriefDescription": "L1 data cache reads", 74 "EventCode": "0x40", 75 "EventName": "L1D_CACHE_LD.MESI", 76 "SampleAfterValue": "2000000", 77 "UMask": "0xf" 78 }, 79 { 80 "BriefDescription": "L1 data cache read in M state", 81 "EventCode": "0x40", 82 "EventName": "L1D_CACHE_LD.M_STATE", 83 "SampleAfterValue": "2000000", 84 "UMask": "0x8" 85 }, 86 { 87 "BriefDescription": "L1 data cache read in S state", 88 "EventCode": "0x40", 89 "EventName": "L1D_CACHE_LD.S_STATE", 90 "SampleAfterValue": "2000000", 91 "UMask": "0x2" 92 }, 93 { 94 "BriefDescription": "L1 data cache load locks in E state", 95 "EventCode": "0x42", 96 "EventName": "L1D_CACHE_LOCK.E_STATE", 97 "SampleAfterValue": "2000000", 98 "UMask": "0x4" 99 }, 100 { 101 "BriefDescription": "L1 data cache load lock hits", 102 "EventCode": "0x42", 103 "EventName": "L1D_CACHE_LOCK.HIT", 104 "SampleAfterValue": "2000000", 105 "UMask": "0x1" 106 }, 107 { 108 "BriefDescription": "L1 data cache load locks in M state", 109 "EventCode": "0x42", 110 "EventName": "L1D_CACHE_LOCK.M_STATE", 111 "SampleAfterValue": "2000000", 112 "UMask": "0x8" 113 }, 114 { 115 "BriefDescription": "L1 data cache load locks in S state", 116 "EventCode": "0x42", 117 "EventName": "L1D_CACHE_LOCK.S_STATE", 118 "SampleAfterValue": "2000000", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "L1D load lock accepted in fill buffer", 123 "EventCode": "0x53", 124 "EventName": "L1D_CACHE_LOCK_FB_HIT", 125 "SampleAfterValue": "2000000", 126 "UMask": "0x1" 127 }, 128 { 129 "BriefDescription": "L1D prefetch load lock accepted in fill buffer", 130 "EventCode": "0x52", 131 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", 132 "SampleAfterValue": "2000000", 133 "UMask": "0x1" 134 }, 135 { 136 "BriefDescription": "L1 data cache stores in E state", 137 "EventCode": "0x41", 138 "EventName": "L1D_CACHE_ST.E_STATE", 139 "SampleAfterValue": "2000000", 140 "UMask": "0x4" 141 }, 142 { 143 "BriefDescription": "L1 data cache stores in M state", 144 "EventCode": "0x41", 145 "EventName": "L1D_CACHE_ST.M_STATE", 146 "SampleAfterValue": "2000000", 147 "UMask": "0x8" 148 }, 149 { 150 "BriefDescription": "L1 data cache stores in S state", 151 "EventCode": "0x41", 152 "EventName": "L1D_CACHE_ST.S_STATE", 153 "SampleAfterValue": "2000000", 154 "UMask": "0x2" 155 }, 156 { 157 "BriefDescription": "L1D hardware prefetch misses", 158 "EventCode": "0x4E", 159 "EventName": "L1D_PREFETCH.MISS", 160 "SampleAfterValue": "200000", 161 "UMask": "0x2" 162 }, 163 { 164 "BriefDescription": "L1D hardware prefetch requests", 165 "EventCode": "0x4E", 166 "EventName": "L1D_PREFETCH.REQUESTS", 167 "SampleAfterValue": "200000", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "L1D hardware prefetch requests triggered", 172 "EventCode": "0x4E", 173 "EventName": "L1D_PREFETCH.TRIGGERS", 174 "SampleAfterValue": "200000", 175 "UMask": "0x4" 176 }, 177 { 178 "BriefDescription": "L1 writebacks to L2 in E state", 179 "EventCode": "0x28", 180 "EventName": "L1D_WB_L2.E_STATE", 181 "SampleAfterValue": "100000", 182 "UMask": "0x4" 183 }, 184 { 185 "BriefDescription": "L1 writebacks to L2 in I state (misses)", 186 "EventCode": "0x28", 187 "EventName": "L1D_WB_L2.I_STATE", 188 "SampleAfterValue": "100000", 189 "UMask": "0x1" 190 }, 191 { 192 "BriefDescription": "All L1 writebacks to L2", 193 "EventCode": "0x28", 194 "EventName": "L1D_WB_L2.MESI", 195 "SampleAfterValue": "100000", 196 "UMask": "0xf" 197 }, 198 { 199 "BriefDescription": "L1 writebacks to L2 in M state", 200 "EventCode": "0x28", 201 "EventName": "L1D_WB_L2.M_STATE", 202 "SampleAfterValue": "100000", 203 "UMask": "0x8" 204 }, 205 { 206 "BriefDescription": "L1 writebacks to L2 in S state", 207 "EventCode": "0x28", 208 "EventName": "L1D_WB_L2.S_STATE", 209 "SampleAfterValue": "100000", 210 "UMask": "0x2" 211 }, 212 { 213 "BriefDescription": "All L2 data requests", 214 "EventCode": "0x26", 215 "EventName": "L2_DATA_RQSTS.ANY", 216 "SampleAfterValue": "200000", 217 "UMask": "0xff" 218 }, 219 { 220 "BriefDescription": "L2 data demand loads in E state", 221 "EventCode": "0x26", 222 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", 223 "SampleAfterValue": "200000", 224 "UMask": "0x4" 225 }, 226 { 227 "BriefDescription": "L2 data demand loads in I state (misses)", 228 "EventCode": "0x26", 229 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", 230 "SampleAfterValue": "200000", 231 "UMask": "0x1" 232 }, 233 { 234 "BriefDescription": "L2 data demand requests", 235 "EventCode": "0x26", 236 "EventName": "L2_DATA_RQSTS.DEMAND.MESI", 237 "SampleAfterValue": "200000", 238 "UMask": "0xf" 239 }, 240 { 241 "BriefDescription": "L2 data demand loads in M state", 242 "EventCode": "0x26", 243 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", 244 "SampleAfterValue": "200000", 245 "UMask": "0x8" 246 }, 247 { 248 "BriefDescription": "L2 data demand loads in S state", 249 "EventCode": "0x26", 250 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", 251 "SampleAfterValue": "200000", 252 "UMask": "0x2" 253 }, 254 { 255 "BriefDescription": "L2 data prefetches in E state", 256 "EventCode": "0x26", 257 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", 258 "SampleAfterValue": "200000", 259 "UMask": "0x40" 260 }, 261 { 262 "BriefDescription": "L2 data prefetches in the I state (misses)", 263 "EventCode": "0x26", 264 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", 265 "SampleAfterValue": "200000", 266 "UMask": "0x10" 267 }, 268 { 269 "BriefDescription": "All L2 data prefetches", 270 "EventCode": "0x26", 271 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", 272 "SampleAfterValue": "200000", 273 "UMask": "0xf0" 274 }, 275 { 276 "BriefDescription": "L2 data prefetches in M state", 277 "EventCode": "0x26", 278 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", 279 "SampleAfterValue": "200000", 280 "UMask": "0x80" 281 }, 282 { 283 "BriefDescription": "L2 data prefetches in the S state", 284 "EventCode": "0x26", 285 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", 286 "SampleAfterValue": "200000", 287 "UMask": "0x20" 288 }, 289 { 290 "BriefDescription": "L2 lines allocated", 291 "EventCode": "0xF1", 292 "EventName": "L2_LINES_IN.ANY", 293 "SampleAfterValue": "100000", 294 "UMask": "0x7" 295 }, 296 { 297 "BriefDescription": "L2 lines allocated in the E state", 298 "EventCode": "0xF1", 299 "EventName": "L2_LINES_IN.E_STATE", 300 "SampleAfterValue": "100000", 301 "UMask": "0x4" 302 }, 303 { 304 "BriefDescription": "L2 lines allocated in the S state", 305 "EventCode": "0xF1", 306 "EventName": "L2_LINES_IN.S_STATE", 307 "SampleAfterValue": "100000", 308 "UMask": "0x2" 309 }, 310 { 311 "BriefDescription": "L2 lines evicted", 312 "EventCode": "0xF2", 313 "EventName": "L2_LINES_OUT.ANY", 314 "SampleAfterValue": "100000", 315 "UMask": "0xf" 316 }, 317 { 318 "BriefDescription": "L2 lines evicted by a demand request", 319 "EventCode": "0xF2", 320 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 321 "SampleAfterValue": "100000", 322 "UMask": "0x1" 323 }, 324 { 325 "BriefDescription": "L2 modified lines evicted by a demand request", 326 "EventCode": "0xF2", 327 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 328 "SampleAfterValue": "100000", 329 "UMask": "0x2" 330 }, 331 { 332 "BriefDescription": "L2 lines evicted by a prefetch request", 333 "EventCode": "0xF2", 334 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", 335 "SampleAfterValue": "100000", 336 "UMask": "0x4" 337 }, 338 { 339 "BriefDescription": "L2 modified lines evicted by a prefetch request", 340 "EventCode": "0xF2", 341 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", 342 "SampleAfterValue": "100000", 343 "UMask": "0x8" 344 }, 345 { 346 "BriefDescription": "L2 instruction fetches", 347 "EventCode": "0x24", 348 "EventName": "L2_RQSTS.IFETCHES", 349 "SampleAfterValue": "200000", 350 "UMask": "0x30" 351 }, 352 { 353 "BriefDescription": "L2 instruction fetch hits", 354 "EventCode": "0x24", 355 "EventName": "L2_RQSTS.IFETCH_HIT", 356 "SampleAfterValue": "200000", 357 "UMask": "0x10" 358 }, 359 { 360 "BriefDescription": "L2 instruction fetch misses", 361 "EventCode": "0x24", 362 "EventName": "L2_RQSTS.IFETCH_MISS", 363 "SampleAfterValue": "200000", 364 "UMask": "0x20" 365 }, 366 { 367 "BriefDescription": "L2 load hits", 368 "EventCode": "0x24", 369 "EventName": "L2_RQSTS.LD_HIT", 370 "SampleAfterValue": "200000", 371 "UMask": "0x1" 372 }, 373 { 374 "BriefDescription": "L2 load misses", 375 "EventCode": "0x24", 376 "EventName": "L2_RQSTS.LD_MISS", 377 "SampleAfterValue": "200000", 378 "UMask": "0x2" 379 }, 380 { 381 "BriefDescription": "L2 requests", 382 "EventCode": "0x24", 383 "EventName": "L2_RQSTS.LOADS", 384 "SampleAfterValue": "200000", 385 "UMask": "0x3" 386 }, 387 { 388 "BriefDescription": "All L2 misses", 389 "EventCode": "0x24", 390 "EventName": "L2_RQSTS.MISS", 391 "SampleAfterValue": "200000", 392 "UMask": "0xaa" 393 }, 394 { 395 "BriefDescription": "All L2 prefetches", 396 "EventCode": "0x24", 397 "EventName": "L2_RQSTS.PREFETCHES", 398 "SampleAfterValue": "200000", 399 "UMask": "0xc0" 400 }, 401 { 402 "BriefDescription": "L2 prefetch hits", 403 "EventCode": "0x24", 404 "EventName": "L2_RQSTS.PREFETCH_HIT", 405 "SampleAfterValue": "200000", 406 "UMask": "0x40" 407 }, 408 { 409 "BriefDescription": "L2 prefetch misses", 410 "EventCode": "0x24", 411 "EventName": "L2_RQSTS.PREFETCH_MISS", 412 "SampleAfterValue": "200000", 413 "UMask": "0x80" 414 }, 415 { 416 "BriefDescription": "All L2 requests", 417 "EventCode": "0x24", 418 "EventName": "L2_RQSTS.REFERENCES", 419 "SampleAfterValue": "200000", 420 "UMask": "0xff" 421 }, 422 { 423 "BriefDescription": "L2 RFO requests", 424 "EventCode": "0x24", 425 "EventName": "L2_RQSTS.RFOS", 426 "SampleAfterValue": "200000", 427 "UMask": "0xc" 428 }, 429 { 430 "BriefDescription": "L2 RFO hits", 431 "EventCode": "0x24", 432 "EventName": "L2_RQSTS.RFO_HIT", 433 "SampleAfterValue": "200000", 434 "UMask": "0x4" 435 }, 436 { 437 "BriefDescription": "L2 RFO misses", 438 "EventCode": "0x24", 439 "EventName": "L2_RQSTS.RFO_MISS", 440 "SampleAfterValue": "200000", 441 "UMask": "0x8" 442 }, 443 { 444 "BriefDescription": "All L2 transactions", 445 "EventCode": "0xF0", 446 "EventName": "L2_TRANSACTIONS.ANY", 447 "SampleAfterValue": "200000", 448 "UMask": "0x80" 449 }, 450 { 451 "BriefDescription": "L2 fill transactions", 452 "EventCode": "0xF0", 453 "EventName": "L2_TRANSACTIONS.FILL", 454 "SampleAfterValue": "200000", 455 "UMask": "0x20" 456 }, 457 { 458 "BriefDescription": "L2 instruction fetch transactions", 459 "EventCode": "0xF0", 460 "EventName": "L2_TRANSACTIONS.IFETCH", 461 "SampleAfterValue": "200000", 462 "UMask": "0x4" 463 }, 464 { 465 "BriefDescription": "L1D writeback to L2 transactions", 466 "EventCode": "0xF0", 467 "EventName": "L2_TRANSACTIONS.L1D_WB", 468 "SampleAfterValue": "200000", 469 "UMask": "0x10" 470 }, 471 { 472 "BriefDescription": "L2 Load transactions", 473 "EventCode": "0xF0", 474 "EventName": "L2_TRANSACTIONS.LOAD", 475 "SampleAfterValue": "200000", 476 "UMask": "0x1" 477 }, 478 { 479 "BriefDescription": "L2 prefetch transactions", 480 "EventCode": "0xF0", 481 "EventName": "L2_TRANSACTIONS.PREFETCH", 482 "SampleAfterValue": "200000", 483 "UMask": "0x8" 484 }, 485 { 486 "BriefDescription": "L2 RFO transactions", 487 "EventCode": "0xF0", 488 "EventName": "L2_TRANSACTIONS.RFO", 489 "SampleAfterValue": "200000", 490 "UMask": "0x2" 491 }, 492 { 493 "BriefDescription": "L2 writeback to LLC transactions", 494 "EventCode": "0xF0", 495 "EventName": "L2_TRANSACTIONS.WB", 496 "SampleAfterValue": "200000", 497 "UMask": "0x40" 498 }, 499 { 500 "BriefDescription": "L2 demand lock RFOs in E state", 501 "EventCode": "0x27", 502 "EventName": "L2_WRITE.LOCK.E_STATE", 503 "SampleAfterValue": "100000", 504 "UMask": "0x40" 505 }, 506 { 507 "BriefDescription": "All demand L2 lock RFOs that hit the cache", 508 "EventCode": "0x27", 509 "EventName": "L2_WRITE.LOCK.HIT", 510 "SampleAfterValue": "100000", 511 "UMask": "0xe0" 512 }, 513 { 514 "BriefDescription": "L2 demand lock RFOs in I state (misses)", 515 "EventCode": "0x27", 516 "EventName": "L2_WRITE.LOCK.I_STATE", 517 "SampleAfterValue": "100000", 518 "UMask": "0x10" 519 }, 520 { 521 "BriefDescription": "All demand L2 lock RFOs", 522 "EventCode": "0x27", 523 "EventName": "L2_WRITE.LOCK.MESI", 524 "SampleAfterValue": "100000", 525 "UMask": "0xf0" 526 }, 527 { 528 "BriefDescription": "L2 demand lock RFOs in M state", 529 "EventCode": "0x27", 530 "EventName": "L2_WRITE.LOCK.M_STATE", 531 "SampleAfterValue": "100000", 532 "UMask": "0x80" 533 }, 534 { 535 "BriefDescription": "L2 demand lock RFOs in S state", 536 "EventCode": "0x27", 537 "EventName": "L2_WRITE.LOCK.S_STATE", 538 "SampleAfterValue": "100000", 539 "UMask": "0x20" 540 }, 541 { 542 "BriefDescription": "All L2 demand store RFOs that hit the cache", 543 "EventCode": "0x27", 544 "EventName": "L2_WRITE.RFO.HIT", 545 "SampleAfterValue": "100000", 546 "UMask": "0xe" 547 }, 548 { 549 "BriefDescription": "L2 demand store RFOs in I state (misses)", 550 "EventCode": "0x27", 551 "EventName": "L2_WRITE.RFO.I_STATE", 552 "SampleAfterValue": "100000", 553 "UMask": "0x1" 554 }, 555 { 556 "BriefDescription": "All L2 demand store RFOs", 557 "EventCode": "0x27", 558 "EventName": "L2_WRITE.RFO.MESI", 559 "SampleAfterValue": "100000", 560 "UMask": "0xf" 561 }, 562 { 563 "BriefDescription": "L2 demand store RFOs in M state", 564 "EventCode": "0x27", 565 "EventName": "L2_WRITE.RFO.M_STATE", 566 "SampleAfterValue": "100000", 567 "UMask": "0x8" 568 }, 569 { 570 "BriefDescription": "L2 demand store RFOs in S state", 571 "EventCode": "0x27", 572 "EventName": "L2_WRITE.RFO.S_STATE", 573 "SampleAfterValue": "100000", 574 "UMask": "0x2" 575 }, 576 { 577 "BriefDescription": "Longest latency cache miss", 578 "EventCode": "0x2E", 579 "EventName": "LONGEST_LAT_CACHE.MISS", 580 "SampleAfterValue": "100000", 581 "UMask": "0x41" 582 }, 583 { 584 "BriefDescription": "Longest latency cache reference", 585 "EventCode": "0x2E", 586 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 587 "SampleAfterValue": "200000", 588 "UMask": "0x4f" 589 }, 590 { 591 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", 592 "EventCode": "0xB", 593 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", 594 "MSRIndex": "0x3F6", 595 "PEBS": "2", 596 "SampleAfterValue": "2000000", 597 "UMask": "0x10" 598 }, 599 { 600 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", 601 "EventCode": "0xB", 602 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", 603 "MSRIndex": "0x3F6", 604 "MSRValue": "0x400", 605 "PEBS": "2", 606 "SampleAfterValue": "100", 607 "UMask": "0x10" 608 }, 609 { 610 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", 611 "EventCode": "0xB", 612 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", 613 "MSRIndex": "0x3F6", 614 "MSRValue": "0x80", 615 "PEBS": "2", 616 "SampleAfterValue": "1000", 617 "UMask": "0x10" 618 }, 619 { 620 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", 621 "EventCode": "0xB", 622 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", 623 "MSRIndex": "0x3F6", 624 "MSRValue": "0x10", 625 "PEBS": "2", 626 "SampleAfterValue": "10000", 627 "UMask": "0x10" 628 }, 629 { 630 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", 631 "EventCode": "0xB", 632 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", 633 "MSRIndex": "0x3F6", 634 "MSRValue": "0x4000", 635 "PEBS": "2", 636 "SampleAfterValue": "5", 637 "UMask": "0x10" 638 }, 639 { 640 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", 641 "EventCode": "0xB", 642 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", 643 "MSRIndex": "0x3F6", 644 "MSRValue": "0x800", 645 "PEBS": "2", 646 "SampleAfterValue": "50", 647 "UMask": "0x10" 648 }, 649 { 650 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", 651 "EventCode": "0xB", 652 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", 653 "MSRIndex": "0x3F6", 654 "MSRValue": "0x100", 655 "PEBS": "2", 656 "SampleAfterValue": "500", 657 "UMask": "0x10" 658 }, 659 { 660 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", 661 "EventCode": "0xB", 662 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", 663 "MSRIndex": "0x3F6", 664 "MSRValue": "0x20", 665 "PEBS": "2", 666 "SampleAfterValue": "5000", 667 "UMask": "0x10" 668 }, 669 { 670 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", 671 "EventCode": "0xB", 672 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", 673 "MSRIndex": "0x3F6", 674 "MSRValue": "0x8000", 675 "PEBS": "2", 676 "SampleAfterValue": "3", 677 "UMask": "0x10" 678 }, 679 { 680 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", 681 "EventCode": "0xB", 682 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", 683 "MSRIndex": "0x3F6", 684 "MSRValue": "0x4", 685 "PEBS": "2", 686 "SampleAfterValue": "50000", 687 "UMask": "0x10" 688 }, 689 { 690 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", 691 "EventCode": "0xB", 692 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", 693 "MSRIndex": "0x3F6", 694 "MSRValue": "0x1000", 695 "PEBS": "2", 696 "SampleAfterValue": "20", 697 "UMask": "0x10" 698 }, 699 { 700 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", 701 "EventCode": "0xB", 702 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", 703 "MSRIndex": "0x3F6", 704 "MSRValue": "0x200", 705 "PEBS": "2", 706 "SampleAfterValue": "200", 707 "UMask": "0x10" 708 }, 709 { 710 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", 711 "EventCode": "0xB", 712 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", 713 "MSRIndex": "0x3F6", 714 "MSRValue": "0x40", 715 "PEBS": "2", 716 "SampleAfterValue": "2000", 717 "UMask": "0x10" 718 }, 719 { 720 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", 721 "EventCode": "0xB", 722 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", 723 "MSRIndex": "0x3F6", 724 "MSRValue": "0x8", 725 "PEBS": "2", 726 "SampleAfterValue": "20000", 727 "UMask": "0x10" 728 }, 729 { 730 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", 731 "EventCode": "0xB", 732 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", 733 "MSRIndex": "0x3F6", 734 "MSRValue": "0x2000", 735 "PEBS": "2", 736 "SampleAfterValue": "10", 737 "UMask": "0x10" 738 }, 739 { 740 "BriefDescription": "Instructions retired which contains a load (Precise Event)", 741 "EventCode": "0xB", 742 "EventName": "MEM_INST_RETIRED.LOADS", 743 "PEBS": "1", 744 "SampleAfterValue": "2000000", 745 "UMask": "0x1" 746 }, 747 { 748 "BriefDescription": "Instructions retired which contains a store (Precise Event)", 749 "EventCode": "0xB", 750 "EventName": "MEM_INST_RETIRED.STORES", 751 "PEBS": "1", 752 "SampleAfterValue": "2000000", 753 "UMask": "0x2" 754 }, 755 { 756 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", 757 "EventCode": "0xCB", 758 "EventName": "MEM_LOAD_RETIRED.HIT_LFB", 759 "PEBS": "1", 760 "SampleAfterValue": "200000", 761 "UMask": "0x40" 762 }, 763 { 764 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", 765 "EventCode": "0xCB", 766 "EventName": "MEM_LOAD_RETIRED.L1D_HIT", 767 "PEBS": "1", 768 "SampleAfterValue": "2000000", 769 "UMask": "0x1" 770 }, 771 { 772 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", 773 "EventCode": "0xCB", 774 "EventName": "MEM_LOAD_RETIRED.L2_HIT", 775 "PEBS": "1", 776 "SampleAfterValue": "200000", 777 "UMask": "0x2" 778 }, 779 { 780 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", 781 "EventCode": "0xCB", 782 "EventName": "MEM_LOAD_RETIRED.LLC_MISS", 783 "PEBS": "1", 784 "SampleAfterValue": "10000", 785 "UMask": "0x10" 786 }, 787 { 788 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", 789 "EventCode": "0xCB", 790 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", 791 "PEBS": "1", 792 "SampleAfterValue": "40000", 793 "UMask": "0x4" 794 }, 795 { 796 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", 797 "EventCode": "0xCB", 798 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", 799 "PEBS": "1", 800 "SampleAfterValue": "40000", 801 "UMask": "0x8" 802 }, 803 { 804 "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", 805 "EventCode": "0xF", 806 "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", 807 "PEBS": "1", 808 "SampleAfterValue": "10000", 809 "UMask": "0x20" 810 }, 811 { 812 "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", 813 "EventCode": "0xF", 814 "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", 815 "PEBS": "1", 816 "SampleAfterValue": "40000", 817 "UMask": "0x2" 818 }, 819 { 820 "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", 821 "EventCode": "0xF", 822 "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", 823 "PEBS": "1", 824 "SampleAfterValue": "20000", 825 "UMask": "0x8" 826 }, 827 { 828 "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", 829 "EventCode": "0xF", 830 "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", 831 "PEBS": "1", 832 "SampleAfterValue": "10000", 833 "UMask": "0x10" 834 }, 835 { 836 "BriefDescription": "Load instructions retired IO (Precise Event)", 837 "EventCode": "0xF", 838 "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", 839 "PEBS": "1", 840 "SampleAfterValue": "4000", 841 "UMask": "0x80" 842 }, 843 { 844 "BriefDescription": "Offcore L1 data cache writebacks", 845 "EventCode": "0xB0", 846 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", 847 "SampleAfterValue": "100000", 848 "UMask": "0x40" 849 }, 850 { 851 "BriefDescription": "Offcore requests blocked due to Super Queue full", 852 "EventCode": "0xB2", 853 "EventName": "OFFCORE_REQUESTS_SQ_FULL", 854 "SampleAfterValue": "100000", 855 "UMask": "0x1" 856 }, 857 { 858 "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", 859 "EventCode": "0xB7", 860 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", 861 "MSRIndex": "0x1A6", 862 "MSRValue": "0x7F11", 863 "SampleAfterValue": "100000", 864 "UMask": "0x1" 865 }, 866 { 867 "BriefDescription": "All offcore data reads", 868 "EventCode": "0xB7", 869 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", 870 "MSRIndex": "0x1A6", 871 "MSRValue": "0xFF11", 872 "SampleAfterValue": "100000", 873 "UMask": "0x1" 874 }, 875 { 876 "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", 877 "EventCode": "0xB7", 878 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", 879 "MSRIndex": "0x1A6", 880 "MSRValue": "0x8011", 881 "SampleAfterValue": "100000", 882 "UMask": "0x1" 883 }, 884 { 885 "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", 886 "EventCode": "0xB7", 887 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", 888 "MSRIndex": "0x1A6", 889 "MSRValue": "0x111", 890 "SampleAfterValue": "100000", 891 "UMask": "0x1" 892 }, 893 { 894 "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", 895 "EventCode": "0xB7", 896 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", 897 "MSRIndex": "0x1A6", 898 "MSRValue": "0x211", 899 "SampleAfterValue": "100000", 900 "UMask": "0x1" 901 }, 902 { 903 "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", 904 "EventCode": "0xB7", 905 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", 906 "MSRIndex": "0x1A6", 907 "MSRValue": "0x411", 908 "SampleAfterValue": "100000", 909 "UMask": "0x1" 910 }, 911 { 912 "BriefDescription": "Offcore data reads satisfied by the LLC", 913 "EventCode": "0xB7", 914 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", 915 "MSRIndex": "0x1A6", 916 "MSRValue": "0x711", 917 "SampleAfterValue": "100000", 918 "UMask": "0x1" 919 }, 920 { 921 "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", 922 "EventCode": "0xB7", 923 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", 924 "MSRIndex": "0x1A6", 925 "MSRValue": "0x4711", 926 "SampleAfterValue": "100000", 927 "UMask": "0x1" 928 }, 929 { 930 "BriefDescription": "Offcore data reads satisfied by a remote cache", 931 "EventCode": "0xB7", 932 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", 933 "MSRIndex": "0x1A6", 934 "MSRValue": "0x1811", 935 "SampleAfterValue": "100000", 936 "UMask": "0x1" 937 }, 938 { 939 "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", 940 "EventCode": "0xB7", 941 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", 942 "MSRIndex": "0x1A6", 943 "MSRValue": "0x3811", 944 "SampleAfterValue": "100000", 945 "UMask": "0x1" 946 }, 947 { 948 "BriefDescription": "Offcore data reads that HIT in a remote cache", 949 "EventCode": "0xB7", 950 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", 951 "MSRIndex": "0x1A6", 952 "MSRValue": "0x1011", 953 "SampleAfterValue": "100000", 954 "UMask": "0x1" 955 }, 956 { 957 "BriefDescription": "Offcore data reads that HITM in a remote cache", 958 "EventCode": "0xB7", 959 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", 960 "MSRIndex": "0x1A6", 961 "MSRValue": "0x811", 962 "SampleAfterValue": "100000", 963 "UMask": "0x1" 964 }, 965 { 966 "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", 967 "EventCode": "0xB7", 968 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", 969 "MSRIndex": "0x1A6", 970 "MSRValue": "0x7F44", 971 "SampleAfterValue": "100000", 972 "UMask": "0x1" 973 }, 974 { 975 "BriefDescription": "All offcore code reads", 976 "EventCode": "0xB7", 977 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", 978 "MSRIndex": "0x1A6", 979 "MSRValue": "0xFF44", 980 "SampleAfterValue": "100000", 981 "UMask": "0x1" 982 }, 983 { 984 "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", 985 "EventCode": "0xB7", 986 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", 987 "MSRIndex": "0x1A6", 988 "MSRValue": "0x8044", 989 "SampleAfterValue": "100000", 990 "UMask": "0x1" 991 }, 992 { 993 "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", 994 "EventCode": "0xB7", 995 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", 996 "MSRIndex": "0x1A6", 997 "MSRValue": "0x144", 998 "SampleAfterValue": "100000", 999 "UMask": "0x1" 1000 }, 1001 { 1002 "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", 1003 "EventCode": "0xB7", 1004 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1005 "MSRIndex": "0x1A6", 1006 "MSRValue": "0x244", 1007 "SampleAfterValue": "100000", 1008 "UMask": "0x1" 1009 }, 1010 { 1011 "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", 1012 "EventCode": "0xB7", 1013 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1014 "MSRIndex": "0x1A6", 1015 "MSRValue": "0x444", 1016 "SampleAfterValue": "100000", 1017 "UMask": "0x1" 1018 }, 1019 { 1020 "BriefDescription": "Offcore code reads satisfied by the LLC", 1021 "EventCode": "0xB7", 1022 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", 1023 "MSRIndex": "0x1A6", 1024 "MSRValue": "0x744", 1025 "SampleAfterValue": "100000", 1026 "UMask": "0x1" 1027 }, 1028 { 1029 "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", 1030 "EventCode": "0xB7", 1031 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", 1032 "MSRIndex": "0x1A6", 1033 "MSRValue": "0x4744", 1034 "SampleAfterValue": "100000", 1035 "UMask": "0x1" 1036 }, 1037 { 1038 "BriefDescription": "Offcore code reads satisfied by a remote cache", 1039 "EventCode": "0xB7", 1040 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", 1041 "MSRIndex": "0x1A6", 1042 "MSRValue": "0x1844", 1043 "SampleAfterValue": "100000", 1044 "UMask": "0x1" 1045 }, 1046 { 1047 "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", 1048 "EventCode": "0xB7", 1049 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", 1050 "MSRIndex": "0x1A6", 1051 "MSRValue": "0x3844", 1052 "SampleAfterValue": "100000", 1053 "UMask": "0x1" 1054 }, 1055 { 1056 "BriefDescription": "Offcore code reads that HIT in a remote cache", 1057 "EventCode": "0xB7", 1058 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", 1059 "MSRIndex": "0x1A6", 1060 "MSRValue": "0x1044", 1061 "SampleAfterValue": "100000", 1062 "UMask": "0x1" 1063 }, 1064 { 1065 "BriefDescription": "Offcore code reads that HITM in a remote cache", 1066 "EventCode": "0xB7", 1067 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", 1068 "MSRIndex": "0x1A6", 1069 "MSRValue": "0x844", 1070 "SampleAfterValue": "100000", 1071 "UMask": "0x1" 1072 }, 1073 { 1074 "BriefDescription": "Offcore requests satisfied by any cache or DRAM", 1075 "EventCode": "0xB7", 1076 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", 1077 "MSRIndex": "0x1A6", 1078 "MSRValue": "0x7FFF", 1079 "SampleAfterValue": "100000", 1080 "UMask": "0x1" 1081 }, 1082 { 1083 "BriefDescription": "All offcore requests", 1084 "EventCode": "0xB7", 1085 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", 1086 "MSRIndex": "0x1A6", 1087 "MSRValue": "0xFFFF", 1088 "SampleAfterValue": "100000", 1089 "UMask": "0x1" 1090 }, 1091 { 1092 "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", 1093 "EventCode": "0xB7", 1094 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", 1095 "MSRIndex": "0x1A6", 1096 "MSRValue": "0x80FF", 1097 "SampleAfterValue": "100000", 1098 "UMask": "0x1" 1099 }, 1100 { 1101 "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", 1102 "EventCode": "0xB7", 1103 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", 1104 "MSRIndex": "0x1A6", 1105 "MSRValue": "0x1FF", 1106 "SampleAfterValue": "100000", 1107 "UMask": "0x1" 1108 }, 1109 { 1110 "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", 1111 "EventCode": "0xB7", 1112 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", 1113 "MSRIndex": "0x1A6", 1114 "MSRValue": "0x2FF", 1115 "SampleAfterValue": "100000", 1116 "UMask": "0x1" 1117 }, 1118 { 1119 "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", 1120 "EventCode": "0xB7", 1121 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", 1122 "MSRIndex": "0x1A6", 1123 "MSRValue": "0x4FF", 1124 "SampleAfterValue": "100000", 1125 "UMask": "0x1" 1126 }, 1127 { 1128 "BriefDescription": "Offcore requests satisfied by the LLC", 1129 "EventCode": "0xB7", 1130 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", 1131 "MSRIndex": "0x1A6", 1132 "MSRValue": "0x7FF", 1133 "SampleAfterValue": "100000", 1134 "UMask": "0x1" 1135 }, 1136 { 1137 "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", 1138 "EventCode": "0xB7", 1139 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", 1140 "MSRIndex": "0x1A6", 1141 "MSRValue": "0x47FF", 1142 "SampleAfterValue": "100000", 1143 "UMask": "0x1" 1144 }, 1145 { 1146 "BriefDescription": "Offcore requests satisfied by a remote cache", 1147 "EventCode": "0xB7", 1148 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", 1149 "MSRIndex": "0x1A6", 1150 "MSRValue": "0x18FF", 1151 "SampleAfterValue": "100000", 1152 "UMask": "0x1" 1153 }, 1154 { 1155 "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", 1156 "EventCode": "0xB7", 1157 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", 1158 "MSRIndex": "0x1A6", 1159 "MSRValue": "0x38FF", 1160 "SampleAfterValue": "100000", 1161 "UMask": "0x1" 1162 }, 1163 { 1164 "BriefDescription": "Offcore requests that HIT in a remote cache", 1165 "EventCode": "0xB7", 1166 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", 1167 "MSRIndex": "0x1A6", 1168 "MSRValue": "0x10FF", 1169 "SampleAfterValue": "100000", 1170 "UMask": "0x1" 1171 }, 1172 { 1173 "BriefDescription": "Offcore requests that HITM in a remote cache", 1174 "EventCode": "0xB7", 1175 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", 1176 "MSRIndex": "0x1A6", 1177 "MSRValue": "0x8FF", 1178 "SampleAfterValue": "100000", 1179 "UMask": "0x1" 1180 }, 1181 { 1182 "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", 1183 "EventCode": "0xB7", 1184 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", 1185 "MSRIndex": "0x1A6", 1186 "MSRValue": "0x7F22", 1187 "SampleAfterValue": "100000", 1188 "UMask": "0x1" 1189 }, 1190 { 1191 "BriefDescription": "All offcore RFO requests", 1192 "EventCode": "0xB7", 1193 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", 1194 "MSRIndex": "0x1A6", 1195 "MSRValue": "0xFF22", 1196 "SampleAfterValue": "100000", 1197 "UMask": "0x1" 1198 }, 1199 { 1200 "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", 1201 "EventCode": "0xB7", 1202 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", 1203 "MSRIndex": "0x1A6", 1204 "MSRValue": "0x8022", 1205 "SampleAfterValue": "100000", 1206 "UMask": "0x1" 1207 }, 1208 { 1209 "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", 1210 "EventCode": "0xB7", 1211 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", 1212 "MSRIndex": "0x1A6", 1213 "MSRValue": "0x122", 1214 "SampleAfterValue": "100000", 1215 "UMask": "0x1" 1216 }, 1217 { 1218 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", 1219 "EventCode": "0xB7", 1220 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", 1221 "MSRIndex": "0x1A6", 1222 "MSRValue": "0x222", 1223 "SampleAfterValue": "100000", 1224 "UMask": "0x1" 1225 }, 1226 { 1227 "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", 1228 "EventCode": "0xB7", 1229 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", 1230 "MSRIndex": "0x1A6", 1231 "MSRValue": "0x422", 1232 "SampleAfterValue": "100000", 1233 "UMask": "0x1" 1234 }, 1235 { 1236 "BriefDescription": "Offcore RFO requests satisfied by the LLC", 1237 "EventCode": "0xB7", 1238 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", 1239 "MSRIndex": "0x1A6", 1240 "MSRValue": "0x722", 1241 "SampleAfterValue": "100000", 1242 "UMask": "0x1" 1243 }, 1244 { 1245 "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", 1246 "EventCode": "0xB7", 1247 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", 1248 "MSRIndex": "0x1A6", 1249 "MSRValue": "0x4722", 1250 "SampleAfterValue": "100000", 1251 "UMask": "0x1" 1252 }, 1253 { 1254 "BriefDescription": "Offcore RFO requests satisfied by a remote cache", 1255 "EventCode": "0xB7", 1256 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", 1257 "MSRIndex": "0x1A6", 1258 "MSRValue": "0x1822", 1259 "SampleAfterValue": "100000", 1260 "UMask": "0x1" 1261 }, 1262 { 1263 "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", 1264 "EventCode": "0xB7", 1265 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", 1266 "MSRIndex": "0x1A6", 1267 "MSRValue": "0x3822", 1268 "SampleAfterValue": "100000", 1269 "UMask": "0x1" 1270 }, 1271 { 1272 "BriefDescription": "Offcore RFO requests that HIT in a remote cache", 1273 "EventCode": "0xB7", 1274 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", 1275 "MSRIndex": "0x1A6", 1276 "MSRValue": "0x1022", 1277 "SampleAfterValue": "100000", 1278 "UMask": "0x1" 1279 }, 1280 { 1281 "BriefDescription": "Offcore RFO requests that HITM in a remote cache", 1282 "EventCode": "0xB7", 1283 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", 1284 "MSRIndex": "0x1A6", 1285 "MSRValue": "0x822", 1286 "SampleAfterValue": "100000", 1287 "UMask": "0x1" 1288 }, 1289 { 1290 "BriefDescription": "Offcore writebacks to any cache or DRAM.", 1291 "EventCode": "0xB7", 1292 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", 1293 "MSRIndex": "0x1A6", 1294 "MSRValue": "0x7F08", 1295 "SampleAfterValue": "100000", 1296 "UMask": "0x1" 1297 }, 1298 { 1299 "BriefDescription": "All offcore writebacks", 1300 "EventCode": "0xB7", 1301 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", 1302 "MSRIndex": "0x1A6", 1303 "MSRValue": "0xFF08", 1304 "SampleAfterValue": "100000", 1305 "UMask": "0x1" 1306 }, 1307 { 1308 "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", 1309 "EventCode": "0xB7", 1310 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", 1311 "MSRIndex": "0x1A6", 1312 "MSRValue": "0x8008", 1313 "SampleAfterValue": "100000", 1314 "UMask": "0x1" 1315 }, 1316 { 1317 "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", 1318 "EventCode": "0xB7", 1319 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", 1320 "MSRIndex": "0x1A6", 1321 "MSRValue": "0x108", 1322 "SampleAfterValue": "100000", 1323 "UMask": "0x1" 1324 }, 1325 { 1326 "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", 1327 "EventCode": "0xB7", 1328 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", 1329 "MSRIndex": "0x1A6", 1330 "MSRValue": "0x408", 1331 "SampleAfterValue": "100000", 1332 "UMask": "0x1" 1333 }, 1334 { 1335 "BriefDescription": "Offcore writebacks to the LLC", 1336 "EventCode": "0xB7", 1337 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", 1338 "MSRIndex": "0x1A6", 1339 "MSRValue": "0x708", 1340 "SampleAfterValue": "100000", 1341 "UMask": "0x1" 1342 }, 1343 { 1344 "BriefDescription": "Offcore writebacks to the LLC or local DRAM", 1345 "EventCode": "0xB7", 1346 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", 1347 "MSRIndex": "0x1A6", 1348 "MSRValue": "0x4708", 1349 "SampleAfterValue": "100000", 1350 "UMask": "0x1" 1351 }, 1352 { 1353 "BriefDescription": "Offcore writebacks to a remote cache", 1354 "EventCode": "0xB7", 1355 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", 1356 "MSRIndex": "0x1A6", 1357 "MSRValue": "0x1808", 1358 "SampleAfterValue": "100000", 1359 "UMask": "0x1" 1360 }, 1361 { 1362 "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", 1363 "EventCode": "0xB7", 1364 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", 1365 "MSRIndex": "0x1A6", 1366 "MSRValue": "0x3808", 1367 "SampleAfterValue": "100000", 1368 "UMask": "0x1" 1369 }, 1370 { 1371 "BriefDescription": "Offcore writebacks that HIT in a remote cache", 1372 "EventCode": "0xB7", 1373 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", 1374 "MSRIndex": "0x1A6", 1375 "MSRValue": "0x1008", 1376 "SampleAfterValue": "100000", 1377 "UMask": "0x1" 1378 }, 1379 { 1380 "BriefDescription": "Offcore writebacks that HITM in a remote cache", 1381 "EventCode": "0xB7", 1382 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", 1383 "MSRIndex": "0x1A6", 1384 "MSRValue": "0x808", 1385 "SampleAfterValue": "100000", 1386 "UMask": "0x1" 1387 }, 1388 { 1389 "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", 1390 "EventCode": "0xB7", 1391 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", 1392 "MSRIndex": "0x1A6", 1393 "MSRValue": "0x7F77", 1394 "SampleAfterValue": "100000", 1395 "UMask": "0x1" 1396 }, 1397 { 1398 "BriefDescription": "All offcore code or data read requests", 1399 "EventCode": "0xB7", 1400 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", 1401 "MSRIndex": "0x1A6", 1402 "MSRValue": "0xFF77", 1403 "SampleAfterValue": "100000", 1404 "UMask": "0x1" 1405 }, 1406 { 1407 "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", 1408 "EventCode": "0xB7", 1409 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", 1410 "MSRIndex": "0x1A6", 1411 "MSRValue": "0x8077", 1412 "SampleAfterValue": "100000", 1413 "UMask": "0x1" 1414 }, 1415 { 1416 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", 1417 "EventCode": "0xB7", 1418 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", 1419 "MSRIndex": "0x1A6", 1420 "MSRValue": "0x177", 1421 "SampleAfterValue": "100000", 1422 "UMask": "0x1" 1423 }, 1424 { 1425 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", 1426 "EventCode": "0xB7", 1427 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1428 "MSRIndex": "0x1A6", 1429 "MSRValue": "0x277", 1430 "SampleAfterValue": "100000", 1431 "UMask": "0x1" 1432 }, 1433 { 1434 "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", 1435 "EventCode": "0xB7", 1436 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1437 "MSRIndex": "0x1A6", 1438 "MSRValue": "0x477", 1439 "SampleAfterValue": "100000", 1440 "UMask": "0x1" 1441 }, 1442 { 1443 "BriefDescription": "Offcore code or data read requests satisfied by the LLC", 1444 "EventCode": "0xB7", 1445 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", 1446 "MSRIndex": "0x1A6", 1447 "MSRValue": "0x777", 1448 "SampleAfterValue": "100000", 1449 "UMask": "0x1" 1450 }, 1451 { 1452 "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", 1453 "EventCode": "0xB7", 1454 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", 1455 "MSRIndex": "0x1A6", 1456 "MSRValue": "0x4777", 1457 "SampleAfterValue": "100000", 1458 "UMask": "0x1" 1459 }, 1460 { 1461 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", 1462 "EventCode": "0xB7", 1463 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", 1464 "MSRIndex": "0x1A6", 1465 "MSRValue": "0x1877", 1466 "SampleAfterValue": "100000", 1467 "UMask": "0x1" 1468 }, 1469 { 1470 "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", 1471 "EventCode": "0xB7", 1472 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", 1473 "MSRIndex": "0x1A6", 1474 "MSRValue": "0x3877", 1475 "SampleAfterValue": "100000", 1476 "UMask": "0x1" 1477 }, 1478 { 1479 "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", 1480 "EventCode": "0xB7", 1481 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", 1482 "MSRIndex": "0x1A6", 1483 "MSRValue": "0x1077", 1484 "SampleAfterValue": "100000", 1485 "UMask": "0x1" 1486 }, 1487 { 1488 "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", 1489 "EventCode": "0xB7", 1490 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", 1491 "MSRIndex": "0x1A6", 1492 "MSRValue": "0x877", 1493 "SampleAfterValue": "100000", 1494 "UMask": "0x1" 1495 }, 1496 { 1497 "BriefDescription": "Offcore request = all data, response = any cache_dram", 1498 "EventCode": "0xB7", 1499 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", 1500 "MSRIndex": "0x1A6", 1501 "MSRValue": "0x7F33", 1502 "SampleAfterValue": "100000", 1503 "UMask": "0x1" 1504 }, 1505 { 1506 "BriefDescription": "Offcore request = all data, response = any location", 1507 "EventCode": "0xB7", 1508 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", 1509 "MSRIndex": "0x1A6", 1510 "MSRValue": "0xFF33", 1511 "SampleAfterValue": "100000", 1512 "UMask": "0x1" 1513 }, 1514 { 1515 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the IO, CSR, MMIO unit", 1516 "EventCode": "0xB7", 1517 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", 1518 "MSRIndex": "0x1A6", 1519 "MSRValue": "0x8033", 1520 "SampleAfterValue": "100000", 1521 "UMask": "0x1" 1522 }, 1523 { 1524 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and not found in a sibling core", 1525 "EventCode": "0xB7", 1526 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", 1527 "MSRIndex": "0x1A6", 1528 "MSRValue": "0x133", 1529 "SampleAfterValue": "100000", 1530 "UMask": "0x1" 1531 }, 1532 { 1533 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HIT in a sibling core", 1534 "EventCode": "0xB7", 1535 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", 1536 "MSRIndex": "0x1A6", 1537 "MSRValue": "0x233", 1538 "SampleAfterValue": "100000", 1539 "UMask": "0x1" 1540 }, 1541 { 1542 "BriefDescription": "Offcore data reads, RFOs, and prefetches satisfied by the LLC and HITM in a sibling core", 1543 "EventCode": "0xB7", 1544 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", 1545 "MSRIndex": "0x1A6", 1546 "MSRValue": "0x433", 1547 "SampleAfterValue": "100000", 1548 "UMask": "0x1" 1549 }, 1550 { 1551 "BriefDescription": "Offcore request = all data, response = local cache", 1552 "EventCode": "0xB7", 1553 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", 1554 "MSRIndex": "0x1A6", 1555 "MSRValue": "0x733", 1556 "SampleAfterValue": "100000", 1557 "UMask": "0x1" 1558 }, 1559 { 1560 "BriefDescription": "Offcore request = all data, response = local cache or dram", 1561 "EventCode": "0xB7", 1562 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", 1563 "MSRIndex": "0x1A6", 1564 "MSRValue": "0x4733", 1565 "SampleAfterValue": "100000", 1566 "UMask": "0x1" 1567 }, 1568 { 1569 "BriefDescription": "Offcore request = all data, response = remote cache", 1570 "EventCode": "0xB7", 1571 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", 1572 "MSRIndex": "0x1A6", 1573 "MSRValue": "0x1833", 1574 "SampleAfterValue": "100000", 1575 "UMask": "0x1" 1576 }, 1577 { 1578 "BriefDescription": "Offcore request = all data, response = remote cache or dram", 1579 "EventCode": "0xB7", 1580 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", 1581 "MSRIndex": "0x1A6", 1582 "MSRValue": "0x3833", 1583 "SampleAfterValue": "100000", 1584 "UMask": "0x1" 1585 }, 1586 { 1587 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HIT in a remote cache", 1588 "EventCode": "0xB7", 1589 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", 1590 "MSRIndex": "0x1A6", 1591 "MSRValue": "0x1033", 1592 "SampleAfterValue": "100000", 1593 "UMask": "0x1" 1594 }, 1595 { 1596 "BriefDescription": "Offcore data reads, RFOs, and prefetches that HITM in a remote cache", 1597 "EventCode": "0xB7", 1598 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", 1599 "MSRIndex": "0x1A6", 1600 "MSRValue": "0x833", 1601 "SampleAfterValue": "100000", 1602 "UMask": "0x1" 1603 }, 1604 { 1605 "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", 1606 "EventCode": "0xB7", 1607 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", 1608 "MSRIndex": "0x1A6", 1609 "MSRValue": "0x7F03", 1610 "SampleAfterValue": "100000", 1611 "UMask": "0x1" 1612 }, 1613 { 1614 "BriefDescription": "All offcore demand data requests", 1615 "EventCode": "0xB7", 1616 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", 1617 "MSRIndex": "0x1A6", 1618 "MSRValue": "0xFF03", 1619 "SampleAfterValue": "100000", 1620 "UMask": "0x1" 1621 }, 1622 { 1623 "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", 1624 "EventCode": "0xB7", 1625 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", 1626 "MSRIndex": "0x1A6", 1627 "MSRValue": "0x8003", 1628 "SampleAfterValue": "100000", 1629 "UMask": "0x1" 1630 }, 1631 { 1632 "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", 1633 "EventCode": "0xB7", 1634 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", 1635 "MSRIndex": "0x1A6", 1636 "MSRValue": "0x103", 1637 "SampleAfterValue": "100000", 1638 "UMask": "0x1" 1639 }, 1640 { 1641 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", 1642 "EventCode": "0xB7", 1643 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", 1644 "MSRIndex": "0x1A6", 1645 "MSRValue": "0x203", 1646 "SampleAfterValue": "100000", 1647 "UMask": "0x1" 1648 }, 1649 { 1650 "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", 1651 "EventCode": "0xB7", 1652 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", 1653 "MSRIndex": "0x1A6", 1654 "MSRValue": "0x403", 1655 "SampleAfterValue": "100000", 1656 "UMask": "0x1" 1657 }, 1658 { 1659 "BriefDescription": "Offcore demand data requests satisfied by the LLC", 1660 "EventCode": "0xB7", 1661 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", 1662 "MSRIndex": "0x1A6", 1663 "MSRValue": "0x703", 1664 "SampleAfterValue": "100000", 1665 "UMask": "0x1" 1666 }, 1667 { 1668 "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", 1669 "EventCode": "0xB7", 1670 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", 1671 "MSRIndex": "0x1A6", 1672 "MSRValue": "0x4703", 1673 "SampleAfterValue": "100000", 1674 "UMask": "0x1" 1675 }, 1676 { 1677 "BriefDescription": "Offcore demand data requests satisfied by a remote cache", 1678 "EventCode": "0xB7", 1679 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", 1680 "MSRIndex": "0x1A6", 1681 "MSRValue": "0x1803", 1682 "SampleAfterValue": "100000", 1683 "UMask": "0x1" 1684 }, 1685 { 1686 "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", 1687 "EventCode": "0xB7", 1688 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", 1689 "MSRIndex": "0x1A6", 1690 "MSRValue": "0x3803", 1691 "SampleAfterValue": "100000", 1692 "UMask": "0x1" 1693 }, 1694 { 1695 "BriefDescription": "Offcore demand data requests that HIT in a remote cache", 1696 "EventCode": "0xB7", 1697 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", 1698 "MSRIndex": "0x1A6", 1699 "MSRValue": "0x1003", 1700 "SampleAfterValue": "100000", 1701 "UMask": "0x1" 1702 }, 1703 { 1704 "BriefDescription": "Offcore demand data requests that HITM in a remote cache", 1705 "EventCode": "0xB7", 1706 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", 1707 "MSRIndex": "0x1A6", 1708 "MSRValue": "0x803", 1709 "SampleAfterValue": "100000", 1710 "UMask": "0x1" 1711 }, 1712 { 1713 "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", 1714 "EventCode": "0xB7", 1715 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", 1716 "MSRIndex": "0x1A6", 1717 "MSRValue": "0x7F01", 1718 "SampleAfterValue": "100000", 1719 "UMask": "0x1" 1720 }, 1721 { 1722 "BriefDescription": "All offcore demand data reads", 1723 "EventCode": "0xB7", 1724 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", 1725 "MSRIndex": "0x1A6", 1726 "MSRValue": "0xFF01", 1727 "SampleAfterValue": "100000", 1728 "UMask": "0x1" 1729 }, 1730 { 1731 "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", 1732 "EventCode": "0xB7", 1733 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", 1734 "MSRIndex": "0x1A6", 1735 "MSRValue": "0x8001", 1736 "SampleAfterValue": "100000", 1737 "UMask": "0x1" 1738 }, 1739 { 1740 "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", 1741 "EventCode": "0xB7", 1742 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", 1743 "MSRIndex": "0x1A6", 1744 "MSRValue": "0x101", 1745 "SampleAfterValue": "100000", 1746 "UMask": "0x1" 1747 }, 1748 { 1749 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", 1750 "EventCode": "0xB7", 1751 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 1752 "MSRIndex": "0x1A6", 1753 "MSRValue": "0x201", 1754 "SampleAfterValue": "100000", 1755 "UMask": "0x1" 1756 }, 1757 { 1758 "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", 1759 "EventCode": "0xB7", 1760 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 1761 "MSRIndex": "0x1A6", 1762 "MSRValue": "0x401", 1763 "SampleAfterValue": "100000", 1764 "UMask": "0x1" 1765 }, 1766 { 1767 "BriefDescription": "Offcore demand data reads satisfied by the LLC", 1768 "EventCode": "0xB7", 1769 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", 1770 "MSRIndex": "0x1A6", 1771 "MSRValue": "0x701", 1772 "SampleAfterValue": "100000", 1773 "UMask": "0x1" 1774 }, 1775 { 1776 "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", 1777 "EventCode": "0xB7", 1778 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", 1779 "MSRIndex": "0x1A6", 1780 "MSRValue": "0x4701", 1781 "SampleAfterValue": "100000", 1782 "UMask": "0x1" 1783 }, 1784 { 1785 "BriefDescription": "Offcore demand data reads satisfied by a remote cache", 1786 "EventCode": "0xB7", 1787 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", 1788 "MSRIndex": "0x1A6", 1789 "MSRValue": "0x1801", 1790 "SampleAfterValue": "100000", 1791 "UMask": "0x1" 1792 }, 1793 { 1794 "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", 1795 "EventCode": "0xB7", 1796 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", 1797 "MSRIndex": "0x1A6", 1798 "MSRValue": "0x3801", 1799 "SampleAfterValue": "100000", 1800 "UMask": "0x1" 1801 }, 1802 { 1803 "BriefDescription": "Offcore demand data reads that HIT in a remote cache", 1804 "EventCode": "0xB7", 1805 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", 1806 "MSRIndex": "0x1A6", 1807 "MSRValue": "0x1001", 1808 "SampleAfterValue": "100000", 1809 "UMask": "0x1" 1810 }, 1811 { 1812 "BriefDescription": "Offcore demand data reads that HITM in a remote cache", 1813 "EventCode": "0xB7", 1814 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", 1815 "MSRIndex": "0x1A6", 1816 "MSRValue": "0x801", 1817 "SampleAfterValue": "100000", 1818 "UMask": "0x1" 1819 }, 1820 { 1821 "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", 1822 "EventCode": "0xB7", 1823 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", 1824 "MSRIndex": "0x1A6", 1825 "MSRValue": "0x7F04", 1826 "SampleAfterValue": "100000", 1827 "UMask": "0x1" 1828 }, 1829 { 1830 "BriefDescription": "All offcore demand code reads", 1831 "EventCode": "0xB7", 1832 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", 1833 "MSRIndex": "0x1A6", 1834 "MSRValue": "0xFF04", 1835 "SampleAfterValue": "100000", 1836 "UMask": "0x1" 1837 }, 1838 { 1839 "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", 1840 "EventCode": "0xB7", 1841 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", 1842 "MSRIndex": "0x1A6", 1843 "MSRValue": "0x8004", 1844 "SampleAfterValue": "100000", 1845 "UMask": "0x1" 1846 }, 1847 { 1848 "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", 1849 "EventCode": "0xB7", 1850 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", 1851 "MSRIndex": "0x1A6", 1852 "MSRValue": "0x104", 1853 "SampleAfterValue": "100000", 1854 "UMask": "0x1" 1855 }, 1856 { 1857 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", 1858 "EventCode": "0xB7", 1859 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", 1860 "MSRIndex": "0x1A6", 1861 "MSRValue": "0x204", 1862 "SampleAfterValue": "100000", 1863 "UMask": "0x1" 1864 }, 1865 { 1866 "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", 1867 "EventCode": "0xB7", 1868 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", 1869 "MSRIndex": "0x1A6", 1870 "MSRValue": "0x404", 1871 "SampleAfterValue": "100000", 1872 "UMask": "0x1" 1873 }, 1874 { 1875 "BriefDescription": "Offcore demand code reads satisfied by the LLC", 1876 "EventCode": "0xB7", 1877 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", 1878 "MSRIndex": "0x1A6", 1879 "MSRValue": "0x704", 1880 "SampleAfterValue": "100000", 1881 "UMask": "0x1" 1882 }, 1883 { 1884 "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", 1885 "EventCode": "0xB7", 1886 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", 1887 "MSRIndex": "0x1A6", 1888 "MSRValue": "0x4704", 1889 "SampleAfterValue": "100000", 1890 "UMask": "0x1" 1891 }, 1892 { 1893 "BriefDescription": "Offcore demand code reads satisfied by a remote cache", 1894 "EventCode": "0xB7", 1895 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", 1896 "MSRIndex": "0x1A6", 1897 "MSRValue": "0x1804", 1898 "SampleAfterValue": "100000", 1899 "UMask": "0x1" 1900 }, 1901 { 1902 "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", 1903 "EventCode": "0xB7", 1904 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", 1905 "MSRIndex": "0x1A6", 1906 "MSRValue": "0x3804", 1907 "SampleAfterValue": "100000", 1908 "UMask": "0x1" 1909 }, 1910 { 1911 "BriefDescription": "Offcore demand code reads that HIT in a remote cache", 1912 "EventCode": "0xB7", 1913 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", 1914 "MSRIndex": "0x1A6", 1915 "MSRValue": "0x1004", 1916 "SampleAfterValue": "100000", 1917 "UMask": "0x1" 1918 }, 1919 { 1920 "BriefDescription": "Offcore demand code reads that HITM in a remote cache", 1921 "EventCode": "0xB7", 1922 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", 1923 "MSRIndex": "0x1A6", 1924 "MSRValue": "0x804", 1925 "SampleAfterValue": "100000", 1926 "UMask": "0x1" 1927 }, 1928 { 1929 "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", 1930 "EventCode": "0xB7", 1931 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", 1932 "MSRIndex": "0x1A6", 1933 "MSRValue": "0x7F02", 1934 "SampleAfterValue": "100000", 1935 "UMask": "0x1" 1936 }, 1937 { 1938 "BriefDescription": "All offcore demand RFO requests", 1939 "EventCode": "0xB7", 1940 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", 1941 "MSRIndex": "0x1A6", 1942 "MSRValue": "0xFF02", 1943 "SampleAfterValue": "100000", 1944 "UMask": "0x1" 1945 }, 1946 { 1947 "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", 1948 "EventCode": "0xB7", 1949 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", 1950 "MSRIndex": "0x1A6", 1951 "MSRValue": "0x8002", 1952 "SampleAfterValue": "100000", 1953 "UMask": "0x1" 1954 }, 1955 { 1956 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", 1957 "EventCode": "0xB7", 1958 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", 1959 "MSRIndex": "0x1A6", 1960 "MSRValue": "0x102", 1961 "SampleAfterValue": "100000", 1962 "UMask": "0x1" 1963 }, 1964 { 1965 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", 1966 "EventCode": "0xB7", 1967 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", 1968 "MSRIndex": "0x1A6", 1969 "MSRValue": "0x202", 1970 "SampleAfterValue": "100000", 1971 "UMask": "0x1" 1972 }, 1973 { 1974 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", 1975 "EventCode": "0xB7", 1976 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", 1977 "MSRIndex": "0x1A6", 1978 "MSRValue": "0x402", 1979 "SampleAfterValue": "100000", 1980 "UMask": "0x1" 1981 }, 1982 { 1983 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", 1984 "EventCode": "0xB7", 1985 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", 1986 "MSRIndex": "0x1A6", 1987 "MSRValue": "0x702", 1988 "SampleAfterValue": "100000", 1989 "UMask": "0x1" 1990 }, 1991 { 1992 "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", 1993 "EventCode": "0xB7", 1994 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", 1995 "MSRIndex": "0x1A6", 1996 "MSRValue": "0x4702", 1997 "SampleAfterValue": "100000", 1998 "UMask": "0x1" 1999 }, 2000 { 2001 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", 2002 "EventCode": "0xB7", 2003 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", 2004 "MSRIndex": "0x1A6", 2005 "MSRValue": "0x1802", 2006 "SampleAfterValue": "100000", 2007 "UMask": "0x1" 2008 }, 2009 { 2010 "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", 2011 "EventCode": "0xB7", 2012 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", 2013 "MSRIndex": "0x1A6", 2014 "MSRValue": "0x3802", 2015 "SampleAfterValue": "100000", 2016 "UMask": "0x1" 2017 }, 2018 { 2019 "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", 2020 "EventCode": "0xB7", 2021 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", 2022 "MSRIndex": "0x1A6", 2023 "MSRValue": "0x1002", 2024 "SampleAfterValue": "100000", 2025 "UMask": "0x1" 2026 }, 2027 { 2028 "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", 2029 "EventCode": "0xB7", 2030 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", 2031 "MSRIndex": "0x1A6", 2032 "MSRValue": "0x802", 2033 "SampleAfterValue": "100000", 2034 "UMask": "0x1" 2035 }, 2036 { 2037 "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", 2038 "EventCode": "0xB7", 2039 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", 2040 "MSRIndex": "0x1A6", 2041 "MSRValue": "0x7F80", 2042 "SampleAfterValue": "100000", 2043 "UMask": "0x1" 2044 }, 2045 { 2046 "BriefDescription": "All offcore other requests", 2047 "EventCode": "0xB7", 2048 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", 2049 "MSRIndex": "0x1A6", 2050 "MSRValue": "0xFF80", 2051 "SampleAfterValue": "100000", 2052 "UMask": "0x1" 2053 }, 2054 { 2055 "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", 2056 "EventCode": "0xB7", 2057 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", 2058 "MSRIndex": "0x1A6", 2059 "MSRValue": "0x8080", 2060 "SampleAfterValue": "100000", 2061 "UMask": "0x1" 2062 }, 2063 { 2064 "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", 2065 "EventCode": "0xB7", 2066 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", 2067 "MSRIndex": "0x1A6", 2068 "MSRValue": "0x180", 2069 "SampleAfterValue": "100000", 2070 "UMask": "0x1" 2071 }, 2072 { 2073 "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", 2074 "EventCode": "0xB7", 2075 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", 2076 "MSRIndex": "0x1A6", 2077 "MSRValue": "0x280", 2078 "SampleAfterValue": "100000", 2079 "UMask": "0x1" 2080 }, 2081 { 2082 "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", 2083 "EventCode": "0xB7", 2084 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", 2085 "MSRIndex": "0x1A6", 2086 "MSRValue": "0x480", 2087 "SampleAfterValue": "100000", 2088 "UMask": "0x1" 2089 }, 2090 { 2091 "BriefDescription": "Offcore other requests satisfied by the LLC", 2092 "EventCode": "0xB7", 2093 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", 2094 "MSRIndex": "0x1A6", 2095 "MSRValue": "0x780", 2096 "SampleAfterValue": "100000", 2097 "UMask": "0x1" 2098 }, 2099 { 2100 "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", 2101 "EventCode": "0xB7", 2102 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", 2103 "MSRIndex": "0x1A6", 2104 "MSRValue": "0x4780", 2105 "SampleAfterValue": "100000", 2106 "UMask": "0x1" 2107 }, 2108 { 2109 "BriefDescription": "Offcore other requests satisfied by a remote cache", 2110 "EventCode": "0xB7", 2111 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", 2112 "MSRIndex": "0x1A6", 2113 "MSRValue": "0x1880", 2114 "SampleAfterValue": "100000", 2115 "UMask": "0x1" 2116 }, 2117 { 2118 "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", 2119 "EventCode": "0xB7", 2120 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", 2121 "MSRIndex": "0x1A6", 2122 "MSRValue": "0x3880", 2123 "SampleAfterValue": "100000", 2124 "UMask": "0x1" 2125 }, 2126 { 2127 "BriefDescription": "Offcore other requests that HIT in a remote cache", 2128 "EventCode": "0xB7", 2129 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", 2130 "MSRIndex": "0x1A6", 2131 "MSRValue": "0x1080", 2132 "SampleAfterValue": "100000", 2133 "UMask": "0x1" 2134 }, 2135 { 2136 "BriefDescription": "Offcore other requests that HITM in a remote cache", 2137 "EventCode": "0xB7", 2138 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", 2139 "MSRIndex": "0x1A6", 2140 "MSRValue": "0x880", 2141 "SampleAfterValue": "100000", 2142 "UMask": "0x1" 2143 }, 2144 { 2145 "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", 2146 "EventCode": "0xB7", 2147 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", 2148 "MSRIndex": "0x1A6", 2149 "MSRValue": "0x7F30", 2150 "SampleAfterValue": "100000", 2151 "UMask": "0x1" 2152 }, 2153 { 2154 "BriefDescription": "All offcore prefetch data requests", 2155 "EventCode": "0xB7", 2156 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", 2157 "MSRIndex": "0x1A6", 2158 "MSRValue": "0xFF30", 2159 "SampleAfterValue": "100000", 2160 "UMask": "0x1" 2161 }, 2162 { 2163 "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", 2164 "EventCode": "0xB7", 2165 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", 2166 "MSRIndex": "0x1A6", 2167 "MSRValue": "0x8030", 2168 "SampleAfterValue": "100000", 2169 "UMask": "0x1" 2170 }, 2171 { 2172 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", 2173 "EventCode": "0xB7", 2174 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", 2175 "MSRIndex": "0x1A6", 2176 "MSRValue": "0x130", 2177 "SampleAfterValue": "100000", 2178 "UMask": "0x1" 2179 }, 2180 { 2181 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", 2182 "EventCode": "0xB7", 2183 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", 2184 "MSRIndex": "0x1A6", 2185 "MSRValue": "0x230", 2186 "SampleAfterValue": "100000", 2187 "UMask": "0x1" 2188 }, 2189 { 2190 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", 2191 "EventCode": "0xB7", 2192 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", 2193 "MSRIndex": "0x1A6", 2194 "MSRValue": "0x430", 2195 "SampleAfterValue": "100000", 2196 "UMask": "0x1" 2197 }, 2198 { 2199 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", 2200 "EventCode": "0xB7", 2201 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", 2202 "MSRIndex": "0x1A6", 2203 "MSRValue": "0x730", 2204 "SampleAfterValue": "100000", 2205 "UMask": "0x1" 2206 }, 2207 { 2208 "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", 2209 "EventCode": "0xB7", 2210 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", 2211 "MSRIndex": "0x1A6", 2212 "MSRValue": "0x4730", 2213 "SampleAfterValue": "100000", 2214 "UMask": "0x1" 2215 }, 2216 { 2217 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", 2218 "EventCode": "0xB7", 2219 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", 2220 "MSRIndex": "0x1A6", 2221 "MSRValue": "0x1830", 2222 "SampleAfterValue": "100000", 2223 "UMask": "0x1" 2224 }, 2225 { 2226 "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", 2227 "EventCode": "0xB7", 2228 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", 2229 "MSRIndex": "0x1A6", 2230 "MSRValue": "0x3830", 2231 "SampleAfterValue": "100000", 2232 "UMask": "0x1" 2233 }, 2234 { 2235 "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", 2236 "EventCode": "0xB7", 2237 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", 2238 "MSRIndex": "0x1A6", 2239 "MSRValue": "0x1030", 2240 "SampleAfterValue": "100000", 2241 "UMask": "0x1" 2242 }, 2243 { 2244 "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", 2245 "EventCode": "0xB7", 2246 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", 2247 "MSRIndex": "0x1A6", 2248 "MSRValue": "0x830", 2249 "SampleAfterValue": "100000", 2250 "UMask": "0x1" 2251 }, 2252 { 2253 "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", 2254 "EventCode": "0xB7", 2255 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", 2256 "MSRIndex": "0x1A6", 2257 "MSRValue": "0x7F10", 2258 "SampleAfterValue": "100000", 2259 "UMask": "0x1" 2260 }, 2261 { 2262 "BriefDescription": "All offcore prefetch data reads", 2263 "EventCode": "0xB7", 2264 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", 2265 "MSRIndex": "0x1A6", 2266 "MSRValue": "0xFF10", 2267 "SampleAfterValue": "100000", 2268 "UMask": "0x1" 2269 }, 2270 { 2271 "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", 2272 "EventCode": "0xB7", 2273 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", 2274 "MSRIndex": "0x1A6", 2275 "MSRValue": "0x8010", 2276 "SampleAfterValue": "100000", 2277 "UMask": "0x1" 2278 }, 2279 { 2280 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", 2281 "EventCode": "0xB7", 2282 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", 2283 "MSRIndex": "0x1A6", 2284 "MSRValue": "0x110", 2285 "SampleAfterValue": "100000", 2286 "UMask": "0x1" 2287 }, 2288 { 2289 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", 2290 "EventCode": "0xB7", 2291 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", 2292 "MSRIndex": "0x1A6", 2293 "MSRValue": "0x210", 2294 "SampleAfterValue": "100000", 2295 "UMask": "0x1" 2296 }, 2297 { 2298 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", 2299 "EventCode": "0xB7", 2300 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", 2301 "MSRIndex": "0x1A6", 2302 "MSRValue": "0x410", 2303 "SampleAfterValue": "100000", 2304 "UMask": "0x1" 2305 }, 2306 { 2307 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", 2308 "EventCode": "0xB7", 2309 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", 2310 "MSRIndex": "0x1A6", 2311 "MSRValue": "0x710", 2312 "SampleAfterValue": "100000", 2313 "UMask": "0x1" 2314 }, 2315 { 2316 "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", 2317 "EventCode": "0xB7", 2318 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", 2319 "MSRIndex": "0x1A6", 2320 "MSRValue": "0x4710", 2321 "SampleAfterValue": "100000", 2322 "UMask": "0x1" 2323 }, 2324 { 2325 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", 2326 "EventCode": "0xB7", 2327 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", 2328 "MSRIndex": "0x1A6", 2329 "MSRValue": "0x1810", 2330 "SampleAfterValue": "100000", 2331 "UMask": "0x1" 2332 }, 2333 { 2334 "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", 2335 "EventCode": "0xB7", 2336 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", 2337 "MSRIndex": "0x1A6", 2338 "MSRValue": "0x3810", 2339 "SampleAfterValue": "100000", 2340 "UMask": "0x1" 2341 }, 2342 { 2343 "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", 2344 "EventCode": "0xB7", 2345 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", 2346 "MSRIndex": "0x1A6", 2347 "MSRValue": "0x1010", 2348 "SampleAfterValue": "100000", 2349 "UMask": "0x1" 2350 }, 2351 { 2352 "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", 2353 "EventCode": "0xB7", 2354 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", 2355 "MSRIndex": "0x1A6", 2356 "MSRValue": "0x810", 2357 "SampleAfterValue": "100000", 2358 "UMask": "0x1" 2359 }, 2360 { 2361 "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", 2362 "EventCode": "0xB7", 2363 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", 2364 "MSRIndex": "0x1A6", 2365 "MSRValue": "0x7F40", 2366 "SampleAfterValue": "100000", 2367 "UMask": "0x1" 2368 }, 2369 { 2370 "BriefDescription": "All offcore prefetch code reads", 2371 "EventCode": "0xB7", 2372 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", 2373 "MSRIndex": "0x1A6", 2374 "MSRValue": "0xFF40", 2375 "SampleAfterValue": "100000", 2376 "UMask": "0x1" 2377 }, 2378 { 2379 "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", 2380 "EventCode": "0xB7", 2381 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", 2382 "MSRIndex": "0x1A6", 2383 "MSRValue": "0x8040", 2384 "SampleAfterValue": "100000", 2385 "UMask": "0x1" 2386 }, 2387 { 2388 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", 2389 "EventCode": "0xB7", 2390 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", 2391 "MSRIndex": "0x1A6", 2392 "MSRValue": "0x140", 2393 "SampleAfterValue": "100000", 2394 "UMask": "0x1" 2395 }, 2396 { 2397 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", 2398 "EventCode": "0xB7", 2399 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", 2400 "MSRIndex": "0x1A6", 2401 "MSRValue": "0x240", 2402 "SampleAfterValue": "100000", 2403 "UMask": "0x1" 2404 }, 2405 { 2406 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", 2407 "EventCode": "0xB7", 2408 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", 2409 "MSRIndex": "0x1A6", 2410 "MSRValue": "0x440", 2411 "SampleAfterValue": "100000", 2412 "UMask": "0x1" 2413 }, 2414 { 2415 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", 2416 "EventCode": "0xB7", 2417 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", 2418 "MSRIndex": "0x1A6", 2419 "MSRValue": "0x740", 2420 "SampleAfterValue": "100000", 2421 "UMask": "0x1" 2422 }, 2423 { 2424 "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", 2425 "EventCode": "0xB7", 2426 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", 2427 "MSRIndex": "0x1A6", 2428 "MSRValue": "0x4740", 2429 "SampleAfterValue": "100000", 2430 "UMask": "0x1" 2431 }, 2432 { 2433 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", 2434 "EventCode": "0xB7", 2435 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", 2436 "MSRIndex": "0x1A6", 2437 "MSRValue": "0x1840", 2438 "SampleAfterValue": "100000", 2439 "UMask": "0x1" 2440 }, 2441 { 2442 "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", 2443 "EventCode": "0xB7", 2444 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", 2445 "MSRIndex": "0x1A6", 2446 "MSRValue": "0x3840", 2447 "SampleAfterValue": "100000", 2448 "UMask": "0x1" 2449 }, 2450 { 2451 "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", 2452 "EventCode": "0xB7", 2453 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", 2454 "MSRIndex": "0x1A6", 2455 "MSRValue": "0x1040", 2456 "SampleAfterValue": "100000", 2457 "UMask": "0x1" 2458 }, 2459 { 2460 "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", 2461 "EventCode": "0xB7", 2462 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", 2463 "MSRIndex": "0x1A6", 2464 "MSRValue": "0x840", 2465 "SampleAfterValue": "100000", 2466 "UMask": "0x1" 2467 }, 2468 { 2469 "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", 2470 "EventCode": "0xB7", 2471 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", 2472 "MSRIndex": "0x1A6", 2473 "MSRValue": "0x7F20", 2474 "SampleAfterValue": "100000", 2475 "UMask": "0x1" 2476 }, 2477 { 2478 "BriefDescription": "All offcore prefetch RFO requests", 2479 "EventCode": "0xB7", 2480 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", 2481 "MSRIndex": "0x1A6", 2482 "MSRValue": "0xFF20", 2483 "SampleAfterValue": "100000", 2484 "UMask": "0x1" 2485 }, 2486 { 2487 "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", 2488 "EventCode": "0xB7", 2489 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", 2490 "MSRIndex": "0x1A6", 2491 "MSRValue": "0x8020", 2492 "SampleAfterValue": "100000", 2493 "UMask": "0x1" 2494 }, 2495 { 2496 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", 2497 "EventCode": "0xB7", 2498 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", 2499 "MSRIndex": "0x1A6", 2500 "MSRValue": "0x120", 2501 "SampleAfterValue": "100000", 2502 "UMask": "0x1" 2503 }, 2504 { 2505 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", 2506 "EventCode": "0xB7", 2507 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", 2508 "MSRIndex": "0x1A6", 2509 "MSRValue": "0x220", 2510 "SampleAfterValue": "100000", 2511 "UMask": "0x1" 2512 }, 2513 { 2514 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", 2515 "EventCode": "0xB7", 2516 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", 2517 "MSRIndex": "0x1A6", 2518 "MSRValue": "0x420", 2519 "SampleAfterValue": "100000", 2520 "UMask": "0x1" 2521 }, 2522 { 2523 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", 2524 "EventCode": "0xB7", 2525 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", 2526 "MSRIndex": "0x1A6", 2527 "MSRValue": "0x720", 2528 "SampleAfterValue": "100000", 2529 "UMask": "0x1" 2530 }, 2531 { 2532 "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", 2533 "EventCode": "0xB7", 2534 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", 2535 "MSRIndex": "0x1A6", 2536 "MSRValue": "0x4720", 2537 "SampleAfterValue": "100000", 2538 "UMask": "0x1" 2539 }, 2540 { 2541 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", 2542 "EventCode": "0xB7", 2543 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", 2544 "MSRIndex": "0x1A6", 2545 "MSRValue": "0x1820", 2546 "SampleAfterValue": "100000", 2547 "UMask": "0x1" 2548 }, 2549 { 2550 "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", 2551 "EventCode": "0xB7", 2552 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", 2553 "MSRIndex": "0x1A6", 2554 "MSRValue": "0x3820", 2555 "SampleAfterValue": "100000", 2556 "UMask": "0x1" 2557 }, 2558 { 2559 "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", 2560 "EventCode": "0xB7", 2561 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", 2562 "MSRIndex": "0x1A6", 2563 "MSRValue": "0x1020", 2564 "SampleAfterValue": "100000", 2565 "UMask": "0x1" 2566 }, 2567 { 2568 "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", 2569 "EventCode": "0xB7", 2570 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", 2571 "MSRIndex": "0x1A6", 2572 "MSRValue": "0x820", 2573 "SampleAfterValue": "100000", 2574 "UMask": "0x1" 2575 }, 2576 { 2577 "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", 2578 "EventCode": "0xB7", 2579 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", 2580 "MSRIndex": "0x1A6", 2581 "MSRValue": "0x7F70", 2582 "SampleAfterValue": "100000", 2583 "UMask": "0x1" 2584 }, 2585 { 2586 "BriefDescription": "All offcore prefetch requests", 2587 "EventCode": "0xB7", 2588 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", 2589 "MSRIndex": "0x1A6", 2590 "MSRValue": "0xFF70", 2591 "SampleAfterValue": "100000", 2592 "UMask": "0x1" 2593 }, 2594 { 2595 "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", 2596 "EventCode": "0xB7", 2597 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", 2598 "MSRIndex": "0x1A6", 2599 "MSRValue": "0x8070", 2600 "SampleAfterValue": "100000", 2601 "UMask": "0x1" 2602 }, 2603 { 2604 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", 2605 "EventCode": "0xB7", 2606 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", 2607 "MSRIndex": "0x1A6", 2608 "MSRValue": "0x170", 2609 "SampleAfterValue": "100000", 2610 "UMask": "0x1" 2611 }, 2612 { 2613 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", 2614 "EventCode": "0xB7", 2615 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", 2616 "MSRIndex": "0x1A6", 2617 "MSRValue": "0x270", 2618 "SampleAfterValue": "100000", 2619 "UMask": "0x1" 2620 }, 2621 { 2622 "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", 2623 "EventCode": "0xB7", 2624 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", 2625 "MSRIndex": "0x1A6", 2626 "MSRValue": "0x470", 2627 "SampleAfterValue": "100000", 2628 "UMask": "0x1" 2629 }, 2630 { 2631 "BriefDescription": "Offcore prefetch requests satisfied by the LLC", 2632 "EventCode": "0xB7", 2633 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", 2634 "MSRIndex": "0x1A6", 2635 "MSRValue": "0x770", 2636 "SampleAfterValue": "100000", 2637 "UMask": "0x1" 2638 }, 2639 { 2640 "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", 2641 "EventCode": "0xB7", 2642 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", 2643 "MSRIndex": "0x1A6", 2644 "MSRValue": "0x4770", 2645 "SampleAfterValue": "100000", 2646 "UMask": "0x1" 2647 }, 2648 { 2649 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", 2650 "EventCode": "0xB7", 2651 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", 2652 "MSRIndex": "0x1A6", 2653 "MSRValue": "0x1870", 2654 "SampleAfterValue": "100000", 2655 "UMask": "0x1" 2656 }, 2657 { 2658 "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", 2659 "EventCode": "0xB7", 2660 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", 2661 "MSRIndex": "0x1A6", 2662 "MSRValue": "0x3870", 2663 "SampleAfterValue": "100000", 2664 "UMask": "0x1" 2665 }, 2666 { 2667 "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", 2668 "EventCode": "0xB7", 2669 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", 2670 "MSRIndex": "0x1A6", 2671 "MSRValue": "0x1070", 2672 "SampleAfterValue": "100000", 2673 "UMask": "0x1" 2674 }, 2675 { 2676 "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", 2677 "EventCode": "0xB7", 2678 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", 2679 "MSRIndex": "0x1A6", 2680 "MSRValue": "0x870", 2681 "SampleAfterValue": "100000", 2682 "UMask": "0x1" 2683 }, 2684 { 2685 "BriefDescription": "Super Queue lock splits across a cache line", 2686 "EventCode": "0xF4", 2687 "EventName": "SQ_MISC.SPLIT_LOCK", 2688 "SampleAfterValue": "2000000", 2689 "UMask": "0x10" 2690 }, 2691 { 2692 "BriefDescription": "Loads delayed with at-Retirement block code", 2693 "EventCode": "0x6", 2694 "EventName": "STORE_BLOCKS.AT_RET", 2695 "SampleAfterValue": "200000", 2696 "UMask": "0x4" 2697 }, 2698 { 2699 "BriefDescription": "Cacheable loads delayed with L1D block code", 2700 "EventCode": "0x6", 2701 "EventName": "STORE_BLOCKS.L1D_BLOCK", 2702 "SampleAfterValue": "200000", 2703 "UMask": "0x8" 2704 } 2705] 2706