1[ 2 { 3 "BriefDescription": "This event counts the cycles the floating point divider is busy.", 4 "CounterMask": "1", 5 "EventCode": "0xb0", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x1", 9 "Unit": "cpu_core" 10 }, 11 { 12 "BriefDescription": "Counts all microcode FP assists.", 13 "EventCode": "0xc1", 14 "EventName": "ASSISTS.FP", 15 "PublicDescription": "Counts all microcode Floating Point assists.", 16 "SampleAfterValue": "100003", 17 "UMask": "0x2", 18 "Unit": "cpu_core" 19 }, 20 { 21 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 22 "EventCode": "0xc1", 23 "EventName": "ASSISTS.SSE_AVX_MIX", 24 "SampleAfterValue": "1000003", 25 "UMask": "0x10", 26 "Unit": "cpu_core" 27 }, 28 { 29 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 30 "EventCode": "0xb3", 31 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 32 "SampleAfterValue": "2000003", 33 "UMask": "0x1", 34 "Unit": "cpu_core" 35 }, 36 { 37 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 38 "EventCode": "0xb3", 39 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x2", 42 "Unit": "cpu_core" 43 }, 44 { 45 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 46 "EventCode": "0xc7", 47 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 48 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 49 "SampleAfterValue": "100003", 50 "UMask": "0x4", 51 "Unit": "cpu_core" 52 }, 53 { 54 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 55 "EventCode": "0xc7", 56 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 57 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 58 "SampleAfterValue": "100003", 59 "UMask": "0x8", 60 "Unit": "cpu_core" 61 }, 62 { 63 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 64 "EventCode": "0xc7", 65 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 66 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 67 "SampleAfterValue": "100003", 68 "UMask": "0x10", 69 "Unit": "cpu_core" 70 }, 71 { 72 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 73 "EventCode": "0xc7", 74 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 75 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 76 "SampleAfterValue": "100003", 77 "UMask": "0x20", 78 "Unit": "cpu_core" 79 }, 80 { 81 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 82 "EventCode": "0xc7", 83 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 84 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 85 "SampleAfterValue": "100003", 86 "UMask": "0x18", 87 "Unit": "cpu_core" 88 }, 89 { 90 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 91 "EventCode": "0xc7", 92 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 93 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 94 "SampleAfterValue": "1000003", 95 "UMask": "0x3", 96 "Unit": "cpu_core" 97 }, 98 { 99 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 100 "EventCode": "0xc7", 101 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 102 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 103 "SampleAfterValue": "100003", 104 "UMask": "0x1", 105 "Unit": "cpu_core" 106 }, 107 { 108 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 109 "EventCode": "0xc7", 110 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 111 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 112 "SampleAfterValue": "100003", 113 "UMask": "0x2", 114 "Unit": "cpu_core" 115 }, 116 { 117 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 118 "EventCode": "0xc7", 119 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 120 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 121 "SampleAfterValue": "1000003", 122 "UMask": "0xfc", 123 "Unit": "cpu_core" 124 }, 125 { 126 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 127 "EventCode": "0xc3", 128 "EventName": "MACHINE_CLEARS.FP_ASSIST", 129 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 130 "SampleAfterValue": "20003", 131 "UMask": "0x4", 132 "Unit": "cpu_atom" 133 }, 134 { 135 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 136 "EventCode": "0xc2", 137 "EventName": "UOPS_RETIRED.FPDIV", 138 "PEBS": "1", 139 "SampleAfterValue": "2000003", 140 "UMask": "0x8", 141 "Unit": "cpu_atom" 142 } 143] 144