1[ 2 { 3 "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", 4 "CounterMask": "1", 5 "EventCode": "0xcd", 6 "EventName": "ARITH.FPDIV_ACTIVE", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x2", 9 "Unit": "cpu_atom" 10 }, 11 { 12 "BriefDescription": "This event counts the cycles the floating point divider is busy.", 13 "CounterMask": "1", 14 "EventCode": "0xb0", 15 "EventName": "ARITH.FPDIV_ACTIVE", 16 "SampleAfterValue": "1000003", 17 "UMask": "0x1", 18 "Unit": "cpu_core" 19 }, 20 { 21 "BriefDescription": "Counts all microcode FP assists.", 22 "EventCode": "0xc1", 23 "EventName": "ASSISTS.FP", 24 "PublicDescription": "Counts all microcode Floating Point assists.", 25 "SampleAfterValue": "100003", 26 "UMask": "0x2", 27 "Unit": "cpu_core" 28 }, 29 { 30 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 31 "EventCode": "0xc1", 32 "EventName": "ASSISTS.SSE_AVX_MIX", 33 "SampleAfterValue": "1000003", 34 "UMask": "0x10", 35 "Unit": "cpu_core" 36 }, 37 { 38 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", 39 "EventCode": "0xb3", 40 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 41 "SampleAfterValue": "2000003", 42 "UMask": "0x1", 43 "Unit": "cpu_core" 44 }, 45 { 46 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", 47 "EventCode": "0xb3", 48 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 49 "SampleAfterValue": "2000003", 50 "UMask": "0x2", 51 "Unit": "cpu_core" 52 }, 53 { 54 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", 55 "EventCode": "0xb3", 56 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 57 "SampleAfterValue": "2000003", 58 "UMask": "0x4", 59 "Unit": "cpu_core" 60 }, 61 { 62 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", 63 "EventCode": "0xb3", 64 "EventName": "FP_ARITH_DISPATCHED.V0", 65 "SampleAfterValue": "2000003", 66 "UMask": "0x1", 67 "Unit": "cpu_core" 68 }, 69 { 70 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", 71 "EventCode": "0xb3", 72 "EventName": "FP_ARITH_DISPATCHED.V1", 73 "SampleAfterValue": "2000003", 74 "UMask": "0x2", 75 "Unit": "cpu_core" 76 }, 77 { 78 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", 79 "EventCode": "0xb3", 80 "EventName": "FP_ARITH_DISPATCHED.V2", 81 "SampleAfterValue": "2000003", 82 "UMask": "0x4", 83 "Unit": "cpu_core" 84 }, 85 { 86 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 87 "EventCode": "0xc7", 88 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 89 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 90 "SampleAfterValue": "100003", 91 "UMask": "0x4", 92 "Unit": "cpu_core" 93 }, 94 { 95 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 96 "EventCode": "0xc7", 97 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 98 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 99 "SampleAfterValue": "100003", 100 "UMask": "0x8", 101 "Unit": "cpu_core" 102 }, 103 { 104 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 105 "EventCode": "0xc7", 106 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 107 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 108 "SampleAfterValue": "100003", 109 "UMask": "0x10", 110 "Unit": "cpu_core" 111 }, 112 { 113 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 114 "EventCode": "0xc7", 115 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 116 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 117 "SampleAfterValue": "100003", 118 "UMask": "0x20", 119 "Unit": "cpu_core" 120 }, 121 { 122 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 123 "EventCode": "0xc7", 124 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 125 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 126 "SampleAfterValue": "100003", 127 "UMask": "0x18", 128 "Unit": "cpu_core" 129 }, 130 { 131 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 132 "EventCode": "0xc7", 133 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 134 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 135 "SampleAfterValue": "1000003", 136 "UMask": "0x3", 137 "Unit": "cpu_core" 138 }, 139 { 140 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 141 "EventCode": "0xc7", 142 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 143 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 144 "SampleAfterValue": "100003", 145 "UMask": "0x1", 146 "Unit": "cpu_core" 147 }, 148 { 149 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 150 "EventCode": "0xc7", 151 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 152 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 153 "SampleAfterValue": "100003", 154 "UMask": "0x2", 155 "Unit": "cpu_core" 156 }, 157 { 158 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 159 "EventCode": "0xc7", 160 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 161 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 162 "SampleAfterValue": "1000003", 163 "UMask": "0xfc", 164 "Unit": "cpu_core" 165 }, 166 { 167 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", 168 "EventCode": "0xc8", 169 "EventName": "FP_FLOPS_RETIRED.ALL", 170 "PEBS": "1", 171 "SampleAfterValue": "1000003", 172 "UMask": "0x3", 173 "Unit": "cpu_atom" 174 }, 175 { 176 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]", 177 "Deprecated": "1", 178 "EventCode": "0xc8", 179 "EventName": "FP_FLOPS_RETIRED.DP", 180 "PEBS": "1", 181 "SampleAfterValue": "1000003", 182 "UMask": "0x1", 183 "Unit": "cpu_atom" 184 }, 185 { 186 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]", 187 "EventCode": "0xc8", 188 "EventName": "FP_FLOPS_RETIRED.FP32", 189 "PEBS": "1", 190 "SampleAfterValue": "1000003", 191 "UMask": "0x2", 192 "Unit": "cpu_atom" 193 }, 194 { 195 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]", 196 "EventCode": "0xc8", 197 "EventName": "FP_FLOPS_RETIRED.FP64", 198 "PEBS": "1", 199 "SampleAfterValue": "1000003", 200 "UMask": "0x1", 201 "Unit": "cpu_atom" 202 }, 203 { 204 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]", 205 "Deprecated": "1", 206 "EventCode": "0xc8", 207 "EventName": "FP_FLOPS_RETIRED.SP", 208 "PEBS": "1", 209 "SampleAfterValue": "1000003", 210 "UMask": "0x2", 211 "Unit": "cpu_atom" 212 }, 213 { 214 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 215 "EventCode": "0xc3", 216 "EventName": "MACHINE_CLEARS.FP_ASSIST", 217 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 218 "SampleAfterValue": "20003", 219 "UMask": "0x4", 220 "Unit": "cpu_atom" 221 }, 222 { 223 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 224 "EventCode": "0xc2", 225 "EventName": "UOPS_RETIRED.FPDIV", 226 "PEBS": "1", 227 "SampleAfterValue": "2000003", 228 "UMask": "0x8", 229 "Unit": "cpu_atom" 230 } 231] 232