1[ 2 { 3 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", 4 "Data_LA": "1", 5 "EventCode": "0xcd", 6 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", 7 "MSRIndex": "0x3F6", 8 "MSRValue": "0x400", 9 "PEBS": "2", 10 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", 11 "SampleAfterValue": "53", 12 "UMask": "0x1", 13 "Unit": "cpu_core" 14 }, 15 { 16 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 17 "Data_LA": "1", 18 "EventCode": "0xcd", 19 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 20 "MSRIndex": "0x3F6", 21 "MSRValue": "0x80", 22 "PEBS": "2", 23 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 24 "SampleAfterValue": "1009", 25 "UMask": "0x1", 26 "Unit": "cpu_core" 27 }, 28 { 29 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 30 "Data_LA": "1", 31 "EventCode": "0xcd", 32 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 33 "MSRIndex": "0x3F6", 34 "MSRValue": "0x10", 35 "PEBS": "2", 36 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 37 "SampleAfterValue": "20011", 38 "UMask": "0x1", 39 "Unit": "cpu_core" 40 }, 41 { 42 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", 43 "Data_LA": "1", 44 "EventCode": "0xcd", 45 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", 46 "MSRIndex": "0x3F6", 47 "MSRValue": "0x800", 48 "PEBS": "2", 49 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", 50 "SampleAfterValue": "23", 51 "UMask": "0x1", 52 "Unit": "cpu_core" 53 }, 54 { 55 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 56 "Data_LA": "1", 57 "EventCode": "0xcd", 58 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 59 "MSRIndex": "0x3F6", 60 "MSRValue": "0x100", 61 "PEBS": "2", 62 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 63 "SampleAfterValue": "503", 64 "UMask": "0x1", 65 "Unit": "cpu_core" 66 }, 67 { 68 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 69 "Data_LA": "1", 70 "EventCode": "0xcd", 71 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 72 "MSRIndex": "0x3F6", 73 "MSRValue": "0x20", 74 "PEBS": "2", 75 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 76 "SampleAfterValue": "100007", 77 "UMask": "0x1", 78 "Unit": "cpu_core" 79 }, 80 { 81 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 82 "Data_LA": "1", 83 "EventCode": "0xcd", 84 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 85 "MSRIndex": "0x3F6", 86 "MSRValue": "0x4", 87 "PEBS": "2", 88 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 89 "SampleAfterValue": "100003", 90 "UMask": "0x1", 91 "Unit": "cpu_core" 92 }, 93 { 94 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 95 "Data_LA": "1", 96 "EventCode": "0xcd", 97 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 98 "MSRIndex": "0x3F6", 99 "MSRValue": "0x200", 100 "PEBS": "2", 101 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 102 "SampleAfterValue": "101", 103 "UMask": "0x1", 104 "Unit": "cpu_core" 105 }, 106 { 107 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 108 "Data_LA": "1", 109 "EventCode": "0xcd", 110 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 111 "MSRIndex": "0x3F6", 112 "MSRValue": "0x40", 113 "PEBS": "2", 114 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 115 "SampleAfterValue": "2003", 116 "UMask": "0x1", 117 "Unit": "cpu_core" 118 }, 119 { 120 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 121 "Data_LA": "1", 122 "EventCode": "0xcd", 123 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 124 "MSRIndex": "0x3F6", 125 "MSRValue": "0x8", 126 "PEBS": "2", 127 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 128 "SampleAfterValue": "50021", 129 "UMask": "0x1", 130 "Unit": "cpu_core" 131 }, 132 { 133 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", 134 "Data_LA": "1", 135 "EventCode": "0xcd", 136 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", 137 "PEBS": "2", 138 "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", 139 "SampleAfterValue": "1000003", 140 "UMask": "0x2", 141 "Unit": "cpu_core" 142 }, 143 { 144 "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.", 145 "EventCode": "0xB7", 146 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 147 "MSRIndex": "0x1a6,0x1a7", 148 "MSRValue": "0x3FBFC00001", 149 "SampleAfterValue": "100003", 150 "UMask": "0x1", 151 "Unit": "cpu_atom" 152 }, 153 { 154 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 155 "EventCode": "0x2A,0x2B", 156 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 157 "MSRIndex": "0x1a6,0x1a7", 158 "MSRValue": "0x3FBFC00001", 159 "SampleAfterValue": "100003", 160 "UMask": "0x1", 161 "Unit": "cpu_core" 162 }, 163 { 164 "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.", 165 "EventCode": "0xB7", 166 "EventName": "OCR.DEMAND_RFO.L3_MISS", 167 "MSRIndex": "0x1a6,0x1a7", 168 "MSRValue": "0x3FBFC00002", 169 "SampleAfterValue": "100003", 170 "UMask": "0x1", 171 "Unit": "cpu_atom" 172 }, 173 { 174 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 175 "EventCode": "0x2A,0x2B", 176 "EventName": "OCR.DEMAND_RFO.L3_MISS", 177 "MSRIndex": "0x1a6,0x1a7", 178 "MSRValue": "0x3FBFC00002", 179 "SampleAfterValue": "100003", 180 "UMask": "0x1", 181 "Unit": "cpu_core" 182 } 183] 184