1[ 2 { 3 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", 4 "Counter": "0,1,2,3,4,5,6,7,8,9", 5 "Data_LA": "1", 6 "EventCode": "0xcd", 7 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", 8 "MSRIndex": "0x3F6", 9 "MSRValue": "0x400", 10 "PEBS": "2", 11 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", 12 "SampleAfterValue": "53", 13 "UMask": "0x1", 14 "Unit": "cpu_core" 15 }, 16 { 17 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 18 "Counter": "0,1,2,3,4,5,6,7,8,9", 19 "Data_LA": "1", 20 "EventCode": "0xcd", 21 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 22 "MSRIndex": "0x3F6", 23 "MSRValue": "0x80", 24 "PEBS": "2", 25 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 26 "SampleAfterValue": "1009", 27 "UMask": "0x1", 28 "Unit": "cpu_core" 29 }, 30 { 31 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 32 "Counter": "0,1,2,3,4,5,6,7,8,9", 33 "Data_LA": "1", 34 "EventCode": "0xcd", 35 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 36 "MSRIndex": "0x3F6", 37 "MSRValue": "0x10", 38 "PEBS": "2", 39 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 40 "SampleAfterValue": "20011", 41 "UMask": "0x1", 42 "Unit": "cpu_core" 43 }, 44 { 45 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", 46 "Counter": "0,1,2,3,4,5,6,7,8,9", 47 "Data_LA": "1", 48 "EventCode": "0xcd", 49 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", 50 "MSRIndex": "0x3F6", 51 "MSRValue": "0x800", 52 "PEBS": "2", 53 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", 54 "SampleAfterValue": "23", 55 "UMask": "0x1", 56 "Unit": "cpu_core" 57 }, 58 { 59 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 60 "Counter": "0,1,2,3,4,5,6,7,8,9", 61 "Data_LA": "1", 62 "EventCode": "0xcd", 63 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 64 "MSRIndex": "0x3F6", 65 "MSRValue": "0x100", 66 "PEBS": "2", 67 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 68 "SampleAfterValue": "503", 69 "UMask": "0x1", 70 "Unit": "cpu_core" 71 }, 72 { 73 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 74 "Counter": "0,1,2,3,4,5,6,7,8,9", 75 "Data_LA": "1", 76 "EventCode": "0xcd", 77 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 78 "MSRIndex": "0x3F6", 79 "MSRValue": "0x20", 80 "PEBS": "2", 81 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 82 "SampleAfterValue": "100007", 83 "UMask": "0x1", 84 "Unit": "cpu_core" 85 }, 86 { 87 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 88 "Counter": "0,1,2,3,4,5,6,7,8,9", 89 "Data_LA": "1", 90 "EventCode": "0xcd", 91 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 92 "MSRIndex": "0x3F6", 93 "MSRValue": "0x4", 94 "PEBS": "2", 95 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 96 "SampleAfterValue": "100003", 97 "UMask": "0x1", 98 "Unit": "cpu_core" 99 }, 100 { 101 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 102 "Counter": "0,1,2,3,4,5,6,7,8,9", 103 "Data_LA": "1", 104 "EventCode": "0xcd", 105 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 106 "MSRIndex": "0x3F6", 107 "MSRValue": "0x200", 108 "PEBS": "2", 109 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 110 "SampleAfterValue": "101", 111 "UMask": "0x1", 112 "Unit": "cpu_core" 113 }, 114 { 115 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 116 "Counter": "0,1,2,3,4,5,6,7,8,9", 117 "Data_LA": "1", 118 "EventCode": "0xcd", 119 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 120 "MSRIndex": "0x3F6", 121 "MSRValue": "0x40", 122 "PEBS": "2", 123 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 124 "SampleAfterValue": "2003", 125 "UMask": "0x1", 126 "Unit": "cpu_core" 127 }, 128 { 129 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 130 "Counter": "0,1,2,3,4,5,6,7,8,9", 131 "Data_LA": "1", 132 "EventCode": "0xcd", 133 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 134 "MSRIndex": "0x3F6", 135 "MSRValue": "0x8", 136 "PEBS": "2", 137 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 138 "SampleAfterValue": "50021", 139 "UMask": "0x1", 140 "Unit": "cpu_core" 141 }, 142 { 143 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", 144 "Counter": "0,1", 145 "Data_LA": "1", 146 "EventCode": "0xcd", 147 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", 148 "PEBS": "2", 149 "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", 150 "SampleAfterValue": "1000003", 151 "UMask": "0x2", 152 "Unit": "cpu_core" 153 }, 154 { 155 "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.", 156 "Counter": "0,1,2,3,4,5,6,7", 157 "EventCode": "0xB7", 158 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 159 "MSRIndex": "0x1a6,0x1a7", 160 "MSRValue": "0x3FBFC00001", 161 "SampleAfterValue": "100003", 162 "UMask": "0x1", 163 "Unit": "cpu_atom" 164 }, 165 { 166 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 167 "Counter": "0,1,2,3", 168 "EventCode": "0x2A,0x2B", 169 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 170 "MSRIndex": "0x1a6,0x1a7", 171 "MSRValue": "0xFE7F8000001", 172 "SampleAfterValue": "100003", 173 "UMask": "0x1", 174 "Unit": "cpu_core" 175 }, 176 { 177 "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.", 178 "Counter": "0,1,2,3,4,5,6,7", 179 "EventCode": "0xB7", 180 "EventName": "OCR.DEMAND_RFO.L3_MISS", 181 "MSRIndex": "0x1a6,0x1a7", 182 "MSRValue": "0x3FBFC00002", 183 "SampleAfterValue": "100003", 184 "UMask": "0x1", 185 "Unit": "cpu_atom" 186 }, 187 { 188 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 189 "Counter": "0,1,2,3", 190 "EventCode": "0x2A,0x2B", 191 "EventName": "OCR.DEMAND_RFO.L3_MISS", 192 "MSRIndex": "0x1a6,0x1a7", 193 "MSRValue": "0xFE7F8000002", 194 "SampleAfterValue": "100003", 195 "UMask": "0x1", 196 "Unit": "cpu_core" 197 } 198] 199