1[ 2 { 3 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", 4 "Counter": "0,1,2,3,4,5,6,7", 5 "EventCode": "0x80", 6 "EventName": "ICACHE.ACCESSES", 7 "SampleAfterValue": "200003", 8 "UMask": "0x3", 9 "Unit": "cpu_atom" 10 }, 11 { 12 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", 13 "Counter": "0,1,2,3,4,5,6,7", 14 "EventCode": "0x80", 15 "EventName": "ICACHE.MISSES", 16 "SampleAfterValue": "200003", 17 "UMask": "0x2", 18 "Unit": "cpu_atom" 19 }, 20 { 21 "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", 22 "Counter": "0,1,2,3,4,5,6,7,8,9", 23 "EventCode": "0x9c", 24 "EventName": "IDQ_BUBBLES.CORE", 25 "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 26 "SampleAfterValue": "1000003", 27 "UMask": "0x1", 28 "Unit": "cpu_core" 29 } 30] 31