1[ 2 { 3 "BriefDescription": "Counts the number of branch instructions retired", 4 "EventCode": "0xC4", 5 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 6 "PEBS": "1", 7 "SampleAfterValue": "200003" 8 }, 9 { 10 "BriefDescription": "Counts the number of near CALL branch instructions retired.", 11 "EventCode": "0xC4", 12 "EventName": "BR_INST_RETIRED.CALL", 13 "PEBS": "1", 14 "SampleAfterValue": "200003", 15 "UMask": "0xf9" 16 }, 17 { 18 "BriefDescription": "Counts the number of far branch instructions retired.", 19 "EventCode": "0xC4", 20 "EventName": "BR_INST_RETIRED.FAR_BRANCH", 21 "PEBS": "1", 22 "SampleAfterValue": "200003", 23 "UMask": "0xbf" 24 }, 25 { 26 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", 27 "EventCode": "0xC4", 28 "EventName": "BR_INST_RETIRED.IND_CALL", 29 "PEBS": "1", 30 "SampleAfterValue": "200003", 31 "UMask": "0xfb" 32 }, 33 { 34 "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.", 35 "EventCode": "0xC4", 36 "EventName": "BR_INST_RETIRED.JCC", 37 "PEBS": "1", 38 "SampleAfterValue": "200003", 39 "UMask": "0x7e" 40 }, 41 { 42 "BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.", 43 "EventCode": "0xC4", 44 "EventName": "BR_INST_RETIRED.NON_RETURN_IND", 45 "PEBS": "1", 46 "SampleAfterValue": "200003", 47 "UMask": "0xeb" 48 }, 49 { 50 "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", 51 "EventCode": "0xC4", 52 "EventName": "BR_INST_RETIRED.REL_CALL", 53 "PEBS": "1", 54 "SampleAfterValue": "200003", 55 "UMask": "0xfd" 56 }, 57 { 58 "BriefDescription": "Counts the number of near RET branch instructions retired.", 59 "EventCode": "0xC4", 60 "EventName": "BR_INST_RETIRED.RETURN", 61 "PEBS": "1", 62 "SampleAfterValue": "200003", 63 "UMask": "0xf7" 64 }, 65 { 66 "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.", 67 "EventCode": "0xC4", 68 "EventName": "BR_INST_RETIRED.TAKEN_JCC", 69 "PEBS": "1", 70 "SampleAfterValue": "200003", 71 "UMask": "0xfe" 72 }, 73 { 74 "BriefDescription": "Counts the number of mispredicted branch instructions retired", 75 "EventCode": "0xC5", 76 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 77 "PEBS": "1", 78 "SampleAfterValue": "200003" 79 }, 80 { 81 "BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.", 82 "EventCode": "0xC5", 83 "EventName": "BR_MISP_RETIRED.CALL", 84 "PEBS": "1", 85 "SampleAfterValue": "200003", 86 "UMask": "0xf9" 87 }, 88 { 89 "BriefDescription": "Counts the number of mispredicted far branch instructions retired.", 90 "EventCode": "0xC5", 91 "EventName": "BR_MISP_RETIRED.FAR_BRANCH", 92 "PEBS": "1", 93 "SampleAfterValue": "200003", 94 "UMask": "0xbf" 95 }, 96 { 97 "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", 98 "EventCode": "0xC5", 99 "EventName": "BR_MISP_RETIRED.IND_CALL", 100 "PEBS": "1", 101 "SampleAfterValue": "200003", 102 "UMask": "0xfb" 103 }, 104 { 105 "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.", 106 "EventCode": "0xC5", 107 "EventName": "BR_MISP_RETIRED.JCC", 108 "PEBS": "1", 109 "SampleAfterValue": "200003", 110 "UMask": "0x7e" 111 }, 112 { 113 "BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.", 114 "EventCode": "0xC5", 115 "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", 116 "PEBS": "1", 117 "SampleAfterValue": "200003", 118 "UMask": "0xeb" 119 }, 120 { 121 "BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.", 122 "EventCode": "0xC5", 123 "EventName": "BR_MISP_RETIRED.REL_CALL", 124 "PEBS": "1", 125 "SampleAfterValue": "200003", 126 "UMask": "0xfd" 127 }, 128 { 129 "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", 130 "EventCode": "0xC5", 131 "EventName": "BR_MISP_RETIRED.RETURN", 132 "PEBS": "1", 133 "SampleAfterValue": "200003", 134 "UMask": "0xf7" 135 }, 136 { 137 "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.", 138 "EventCode": "0xC5", 139 "EventName": "BR_MISP_RETIRED.TAKEN_JCC", 140 "PEBS": "1", 141 "SampleAfterValue": "200003", 142 "UMask": "0xfe" 143 }, 144 { 145 "BriefDescription": "Counts the number of unhalted reference clock cycles", 146 "EventCode": "0x3C", 147 "EventName": "CPU_CLK_UNHALTED.REF", 148 "SampleAfterValue": "2000003", 149 "UMask": "0x1" 150 }, 151 { 152 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 153 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 154 "SampleAfterValue": "2000003", 155 "UMask": "0x3" 156 }, 157 { 158 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 159 "EventName": "CPU_CLK_UNHALTED.THREAD", 160 "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter", 161 "SampleAfterValue": "2000003", 162 "UMask": "0x2" 163 }, 164 { 165 "BriefDescription": "Counts the number of unhalted core clock cycles", 166 "EventCode": "0x3C", 167 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 168 "SampleAfterValue": "2000003" 169 }, 170 { 171 "BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.", 172 "EventCode": "0xCD", 173 "EventName": "CYCLES_DIV_BUSY.ALL", 174 "PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.", 175 "SampleAfterValue": "2000003", 176 "UMask": "0x1" 177 }, 178 { 179 "BriefDescription": "Fixed Counter: Counts the number of instructions retired", 180 "EventName": "INST_RETIRED.ANY", 181 "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.", 182 "SampleAfterValue": "2000003", 183 "UMask": "0x1" 184 }, 185 { 186 "BriefDescription": "Counts the total number of instructions retired", 187 "EventCode": "0xC0", 188 "EventName": "INST_RETIRED.ANY_P", 189 "SampleAfterValue": "2000003" 190 }, 191 { 192 "BriefDescription": "Counts all nukes", 193 "EventCode": "0xC3", 194 "EventName": "MACHINE_CLEARS.ALL", 195 "SampleAfterValue": "200003", 196 "UMask": "0x8" 197 }, 198 { 199 "BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page", 200 "EventCode": "0xC3", 201 "EventName": "MACHINE_CLEARS.SMC", 202 "SampleAfterValue": "200003", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason.", 207 "EventCode": "0xCA", 208 "EventName": "NO_ALLOC_CYCLES.ALL", 209 "SampleAfterValue": "200003", 210 "UMask": "0x7f" 211 }, 212 { 213 "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", 214 "EventCode": "0xCA", 215 "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", 216 "PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", 217 "SampleAfterValue": "200003", 218 "UMask": "0x4" 219 }, 220 { 221 "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.", 222 "EventCode": "0xCA", 223 "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", 224 "PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.", 225 "SampleAfterValue": "200003", 226 "UMask": "0x90" 227 }, 228 { 229 "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.", 230 "EventCode": "0xCA", 231 "EventName": "NO_ALLOC_CYCLES.RAT_STALL", 232 "SampleAfterValue": "200003", 233 "UMask": "0x20" 234 }, 235 { 236 "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full", 237 "EventCode": "0xCA", 238 "EventName": "NO_ALLOC_CYCLES.ROB_FULL", 239 "SampleAfterValue": "200003", 240 "UMask": "0x1" 241 }, 242 { 243 "BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason.", 244 "EventCode": "0x03", 245 "EventName": "RECYCLEQ.ANY_LD", 246 "SampleAfterValue": "200003", 247 "UMask": "0x40" 248 }, 249 { 250 "BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason.", 251 "EventCode": "0x03", 252 "EventName": "RECYCLEQ.ANY_ST", 253 "SampleAfterValue": "200003", 254 "UMask": "0x80" 255 }, 256 { 257 "BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready", 258 "EventCode": "0x03", 259 "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", 260 "SampleAfterValue": "200003", 261 "UMask": "0x2" 262 }, 263 { 264 "BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store", 265 "Data_LA": "1", 266 "EventCode": "0x03", 267 "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", 268 "PEBS": "1", 269 "SampleAfterValue": "200003", 270 "UMask": "0x1" 271 }, 272 { 273 "BriefDescription": "Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once.", 274 "Data_LA": "1", 275 "EventCode": "0x03", 276 "EventName": "RECYCLEQ.LD_SPLITS", 277 "PEBS": "1", 278 "SampleAfterValue": "200003", 279 "UMask": "0x8" 280 }, 281 { 282 "BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores", 283 "EventCode": "0x03", 284 "EventName": "RECYCLEQ.LOCK", 285 "SampleAfterValue": "200003", 286 "UMask": "0x10" 287 }, 288 { 289 "BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full", 290 "EventCode": "0x03", 291 "EventName": "RECYCLEQ.STA_FULL", 292 "SampleAfterValue": "200003", 293 "UMask": "0x20" 294 }, 295 { 296 "BriefDescription": "Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.", 297 "EventCode": "0x03", 298 "EventName": "RECYCLEQ.ST_SPLITS", 299 "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.", 300 "SampleAfterValue": "200003", 301 "UMask": "0x4" 302 }, 303 { 304 "BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.", 305 "EventCode": "0xCB", 306 "EventName": "RS_FULL_STALL.ALL", 307 "SampleAfterValue": "200003", 308 "UMask": "0x1f" 309 }, 310 { 311 "BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.", 312 "EventCode": "0xCB", 313 "EventName": "RS_FULL_STALL.MEC", 314 "SampleAfterValue": "200003", 315 "UMask": "0x1" 316 }, 317 { 318 "BriefDescription": "Counts the number of micro-ops retired", 319 "EventCode": "0xC2", 320 "EventName": "UOPS_RETIRED.ALL", 321 "PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.", 322 "SampleAfterValue": "2000003", 323 "UMask": "0x10" 324 }, 325 { 326 "BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).", 327 "EventCode": "0xC2", 328 "EventName": "UOPS_RETIRED.MS", 329 "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", 330 "SampleAfterValue": "2000003", 331 "UMask": "0x1" 332 } 333] 334