1[ 2 { 3 "BriefDescription": "Counts the number of floating operations retired that required microcode assists", 4 "Counter": "0,1", 5 "EventCode": "0xC3", 6 "EventName": "MACHINE_CLEARS.FP_ASSIST", 7 "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.", 8 "SampleAfterValue": "200003", 9 "UMask": "0x4" 10 }, 11 { 12 "BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", 13 "Counter": "0,1", 14 "EventCode": "0xC2", 15 "EventName": "UOPS_RETIRED.PACKED_SIMD", 16 "PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.", 17 "SampleAfterValue": "200003", 18 "UMask": "0x40" 19 }, 20 { 21 "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.", 22 "Counter": "0,1", 23 "EventCode": "0xC2", 24 "EventName": "UOPS_RETIRED.SCALAR_SIMD", 25 "PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.", 26 "SampleAfterValue": "200003", 27 "UMask": "0x20" 28 } 29] 30