1[ 2 { 3 "BriefDescription": "Counts the number of floating operations retired that required microcode assists", 4 "EventCode": "0xC3", 5 "EventName": "MACHINE_CLEARS.FP_ASSIST", 6 "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.", 7 "SampleAfterValue": "200003", 8 "UMask": "0x4" 9 }, 10 { 11 "BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", 12 "EventCode": "0xC2", 13 "EventName": "UOPS_RETIRED.PACKED_SIMD", 14 "PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.", 15 "SampleAfterValue": "200003", 16 "UMask": "0x40" 17 }, 18 { 19 "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.", 20 "EventCode": "0xC2", 21 "EventName": "UOPS_RETIRED.SCALAR_SIMD", 22 "PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.", 23 "SampleAfterValue": "200003", 24 "UMask": "0x20" 25 } 26] 27