1[ 2 { 3 "PublicDescription": "Counts cycles the IDQ is empty.", 4 "EventCode": "0x79", 5 "Counter": "0,1,2,3", 6 "UMask": "0x2", 7 "EventName": "IDQ.EMPTY", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", 10 "CounterHTOff": "0,1,2,3" 11 }, 12 { 13 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", 14 "EventCode": "0x79", 15 "Counter": "0,1,2,3", 16 "UMask": "0x4", 17 "EventName": "IDQ.MITE_UOPS", 18 "SampleAfterValue": "2000003", 19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", 24 "EventCode": "0x79", 25 "Counter": "0,1,2,3", 26 "UMask": "0x8", 27 "EventName": "IDQ.DSB_UOPS", 28 "SampleAfterValue": "2000003", 29 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 }, 32 { 33 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", 34 "EventCode": "0x79", 35 "Counter": "0,1,2,3", 36 "UMask": "0x10", 37 "EventName": "IDQ.MS_DSB_UOPS", 38 "SampleAfterValue": "2000003", 39 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 40 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 }, 42 { 43 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", 44 "EventCode": "0x79", 45 "Counter": "0,1,2,3", 46 "UMask": "0x20", 47 "EventName": "IDQ.MS_MITE_UOPS", 48 "SampleAfterValue": "2000003", 49 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 50 "CounterHTOff": "0,1,2,3,4,5,6,7" 51 }, 52 { 53 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", 54 "EventCode": "0x79", 55 "Counter": "0,1,2,3", 56 "UMask": "0x30", 57 "EventName": "IDQ.MS_UOPS", 58 "SampleAfterValue": "2000003", 59 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 60 "CounterHTOff": "0,1,2,3,4,5,6,7" 61 }, 62 { 63 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 64 "EventCode": "0x79", 65 "Counter": "0,1,2,3", 66 "UMask": "0x30", 67 "EventName": "IDQ.MS_CYCLES", 68 "SampleAfterValue": "2000003", 69 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 70 "CounterMask": "1", 71 "CounterHTOff": "0,1,2,3,4,5,6,7" 72 }, 73 { 74 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", 75 "EventCode": "0x79", 76 "Counter": "0,1,2,3", 77 "UMask": "0x4", 78 "EventName": "IDQ.MITE_CYCLES", 79 "SampleAfterValue": "2000003", 80 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", 81 "CounterMask": "1", 82 "CounterHTOff": "0,1,2,3,4,5,6,7" 83 }, 84 { 85 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", 86 "EventCode": "0x79", 87 "Counter": "0,1,2,3", 88 "UMask": "0x8", 89 "EventName": "IDQ.DSB_CYCLES", 90 "SampleAfterValue": "2000003", 91 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", 92 "CounterMask": "1", 93 "CounterHTOff": "0,1,2,3,4,5,6,7" 94 }, 95 { 96 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", 97 "EventCode": "0x79", 98 "Counter": "0,1,2,3", 99 "UMask": "0x10", 100 "EventName": "IDQ.MS_DSB_CYCLES", 101 "SampleAfterValue": "2000003", 102 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", 103 "CounterMask": "1", 104 "CounterHTOff": "0,1,2,3,4,5,6,7" 105 }, 106 { 107 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", 108 "EventCode": "0x79", 109 "Counter": "0,1,2,3", 110 "UMask": "0x10", 111 "EdgeDetect": "1", 112 "EventName": "IDQ.MS_DSB_OCCUR", 113 "SampleAfterValue": "2000003", 114 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", 115 "CounterMask": "1", 116 "CounterHTOff": "0,1,2,3,4,5,6,7" 117 }, 118 { 119 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", 120 "EventCode": "0x79", 121 "Counter": "0,1,2,3", 122 "UMask": "0x18", 123 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 124 "SampleAfterValue": "2000003", 125 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 126 "CounterMask": "4", 127 "CounterHTOff": "0,1,2,3,4,5,6,7" 128 }, 129 { 130 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", 131 "EventCode": "0x79", 132 "Counter": "0,1,2,3", 133 "UMask": "0x18", 134 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 135 "SampleAfterValue": "2000003", 136 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 137 "CounterMask": "1", 138 "CounterHTOff": "0,1,2,3,4,5,6,7" 139 }, 140 { 141 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", 142 "EventCode": "0x79", 143 "Counter": "0,1,2,3", 144 "UMask": "0x24", 145 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", 146 "SampleAfterValue": "2000003", 147 "BriefDescription": "Cycles MITE is delivering 4 Uops", 148 "CounterMask": "4", 149 "CounterHTOff": "0,1,2,3,4,5,6,7" 150 }, 151 { 152 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", 153 "EventCode": "0x79", 154 "Counter": "0,1,2,3", 155 "UMask": "0x24", 156 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", 157 "SampleAfterValue": "2000003", 158 "BriefDescription": "Cycles MITE is delivering any Uop", 159 "CounterMask": "1", 160 "CounterHTOff": "0,1,2,3,4,5,6,7" 161 }, 162 { 163 "PublicDescription": "Number of uops delivered to IDQ from any path.", 164 "EventCode": "0x79", 165 "Counter": "0,1,2,3", 166 "UMask": "0x3c", 167 "EventName": "IDQ.MITE_ALL_UOPS", 168 "SampleAfterValue": "2000003", 169 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 170 "CounterHTOff": "0,1,2,3,4,5,6,7" 171 }, 172 { 173 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", 174 "EventCode": "0x80", 175 "Counter": "0,1,2,3", 176 "UMask": "0x1", 177 "EventName": "ICACHE.HIT", 178 "SampleAfterValue": "2000003", 179 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", 180 "CounterHTOff": "0,1,2,3,4,5,6,7" 181 }, 182 { 183 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", 184 "EventCode": "0x80", 185 "Counter": "0,1,2,3", 186 "UMask": "0x2", 187 "EventName": "ICACHE.MISSES", 188 "SampleAfterValue": "200003", 189 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", 190 "CounterHTOff": "0,1,2,3,4,5,6,7" 191 }, 192 { 193 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", 194 "EventCode": "0x80", 195 "Counter": "0,1,2,3", 196 "UMask": "0x4", 197 "EventName": "ICACHE.IFETCH_STALL", 198 "SampleAfterValue": "2000003", 199 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", 200 "CounterHTOff": "0,1,2,3,4,5,6,7" 201 }, 202 { 203 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", 204 "EventCode": "0x9C", 205 "Counter": "0,1,2,3", 206 "UMask": "0x1", 207 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 208 "SampleAfterValue": "2000003", 209 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ", 210 "CounterHTOff": "0,1,2,3" 211 }, 212 { 213 "EventCode": "0x9C", 214 "Counter": "0,1,2,3", 215 "UMask": "0x1", 216 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 217 "SampleAfterValue": "2000003", 218 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 219 "CounterMask": "4", 220 "CounterHTOff": "0,1,2,3" 221 }, 222 { 223 "EventCode": "0x9C", 224 "Counter": "0,1,2,3", 225 "UMask": "0x1", 226 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", 227 "SampleAfterValue": "2000003", 228 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", 229 "CounterMask": "3", 230 "CounterHTOff": "0,1,2,3" 231 }, 232 { 233 "EventCode": "0x9C", 234 "Counter": "0,1,2,3", 235 "UMask": "0x1", 236 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", 237 "SampleAfterValue": "2000003", 238 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", 239 "CounterMask": "2", 240 "CounterHTOff": "0,1,2,3" 241 }, 242 { 243 "EventCode": "0x9C", 244 "Counter": "0,1,2,3", 245 "UMask": "0x1", 246 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", 247 "SampleAfterValue": "2000003", 248 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", 249 "CounterMask": "1", 250 "CounterHTOff": "0,1,2,3" 251 }, 252 { 253 "EventCode": "0x9C", 254 "Invert": "1", 255 "Counter": "0,1,2,3", 256 "UMask": "0x1", 257 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 258 "SampleAfterValue": "2000003", 259 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", 260 "CounterMask": "1", 261 "CounterHTOff": "0,1,2,3" 262 }, 263 { 264 "PublicDescription": "Number of DSB to MITE switches.", 265 "EventCode": "0xAB", 266 "Counter": "0,1,2,3", 267 "UMask": "0x1", 268 "EventName": "DSB2MITE_SWITCHES.COUNT", 269 "SampleAfterValue": "2000003", 270 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 271 "CounterHTOff": "0,1,2,3,4,5,6,7" 272 }, 273 { 274 "PublicDescription": "Cycles DSB to MITE switches caused delay.", 275 "EventCode": "0xAB", 276 "Counter": "0,1,2,3", 277 "UMask": "0x2", 278 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 279 "SampleAfterValue": "2000003", 280 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", 281 "CounterHTOff": "0,1,2,3,4,5,6,7" 282 }, 283 { 284 "PublicDescription": "DSB Fill encountered > 3 DSB lines.", 285 "EventCode": "0xAC", 286 "Counter": "0,1,2,3", 287 "UMask": "0x8", 288 "EventName": "DSB_FILL.EXCEED_DSB_LINES", 289 "SampleAfterValue": "2000003", 290 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", 291 "CounterHTOff": "0,1,2,3,4,5,6,7" 292 }, 293 { 294 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 295 "EventCode": "0x79", 296 "Counter": "0,1,2,3", 297 "UMask": "0x30", 298 "EdgeDetect": "1", 299 "EventName": "IDQ.MS_SWITCHES", 300 "SampleAfterValue": "2000003", 301 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", 302 "CounterMask": "1", 303 "CounterHTOff": "0,1,2,3,4,5,6,7" 304 } 305]