1[ 2 { 3 "BriefDescription": "L1D data line replacements", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x51", 6 "EventName": "L1D.REPLACEMENT", 7 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x1" 10 }, 11 { 12 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability", 13 "Counter": "0,1,2,3", 14 "CounterMask": "1", 15 "EventCode": "0x48", 16 "EventName": "L1D_PEND_MISS.FB_FULL", 17 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", 18 "SampleAfterValue": "2000003", 19 "UMask": "0x2" 20 }, 21 { 22 "BriefDescription": "L1D miss outstanding duration in cycles", 23 "Counter": "2", 24 "EventCode": "0x48", 25 "EventName": "L1D_PEND_MISS.PENDING", 26 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x1" 29 }, 30 { 31 "BriefDescription": "Cycles with L1D load Misses outstanding.", 32 "Counter": "2", 33 "CounterMask": "1", 34 "EventCode": "0x48", 35 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x1" 38 }, 39 { 40 "AnyThread": "1", 41 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 42 "Counter": "2", 43 "CounterMask": "1", 44 "EventCode": "0x48", 45 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 46 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 47 "SampleAfterValue": "2000003", 48 "UMask": "0x1" 49 }, 50 { 51 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 52 "Counter": "0,1,2,3", 53 "EventCode": "0x28", 54 "EventName": "L2_L1D_WB_RQSTS.ALL", 55 "SampleAfterValue": "200003", 56 "UMask": "0xf" 57 }, 58 { 59 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x28", 62 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 63 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 64 "SampleAfterValue": "200003", 65 "UMask": "0x4" 66 }, 67 { 68 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 69 "Counter": "0,1,2,3", 70 "EventCode": "0x28", 71 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 72 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 73 "SampleAfterValue": "200003", 74 "UMask": "0x8" 75 }, 76 { 77 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", 78 "Counter": "0,1,2,3", 79 "EventCode": "0x28", 80 "EventName": "L2_L1D_WB_RQSTS.MISS", 81 "PublicDescription": "Not rejected writebacks that missed LLC.", 82 "SampleAfterValue": "200003", 83 "UMask": "0x1" 84 }, 85 { 86 "BriefDescription": "L2 cache lines filling L2", 87 "Counter": "0,1,2,3", 88 "EventCode": "0xF1", 89 "EventName": "L2_LINES_IN.ALL", 90 "PublicDescription": "L2 cache lines filling L2.", 91 "SampleAfterValue": "100003", 92 "UMask": "0x7" 93 }, 94 { 95 "BriefDescription": "L2 cache lines in E state filling L2", 96 "Counter": "0,1,2,3", 97 "EventCode": "0xF1", 98 "EventName": "L2_LINES_IN.E", 99 "PublicDescription": "L2 cache lines in E state filling L2.", 100 "SampleAfterValue": "100003", 101 "UMask": "0x4" 102 }, 103 { 104 "BriefDescription": "L2 cache lines in I state filling L2", 105 "Counter": "0,1,2,3", 106 "EventCode": "0xF1", 107 "EventName": "L2_LINES_IN.I", 108 "PublicDescription": "L2 cache lines in I state filling L2.", 109 "SampleAfterValue": "100003", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "L2 cache lines in S state filling L2", 114 "Counter": "0,1,2,3", 115 "EventCode": "0xF1", 116 "EventName": "L2_LINES_IN.S", 117 "PublicDescription": "L2 cache lines in S state filling L2.", 118 "SampleAfterValue": "100003", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "Clean L2 cache lines evicted by demand", 123 "Counter": "0,1,2,3", 124 "EventCode": "0xF2", 125 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 126 "PublicDescription": "Clean L2 cache lines evicted by demand.", 127 "SampleAfterValue": "100003", 128 "UMask": "0x1" 129 }, 130 { 131 "BriefDescription": "Dirty L2 cache lines evicted by demand", 132 "Counter": "0,1,2,3", 133 "EventCode": "0xF2", 134 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 135 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 136 "SampleAfterValue": "100003", 137 "UMask": "0x2" 138 }, 139 { 140 "BriefDescription": "Dirty L2 cache lines filling the L2", 141 "Counter": "0,1,2,3", 142 "EventCode": "0xF2", 143 "EventName": "L2_LINES_OUT.DIRTY_ALL", 144 "PublicDescription": "Dirty L2 cache lines filling the L2.", 145 "SampleAfterValue": "100003", 146 "UMask": "0xa" 147 }, 148 { 149 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", 150 "Counter": "0,1,2,3", 151 "EventCode": "0xF2", 152 "EventName": "L2_LINES_OUT.PF_CLEAN", 153 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", 154 "SampleAfterValue": "100003", 155 "UMask": "0x4" 156 }, 157 { 158 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", 159 "Counter": "0,1,2,3", 160 "EventCode": "0xF2", 161 "EventName": "L2_LINES_OUT.PF_DIRTY", 162 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", 163 "SampleAfterValue": "100003", 164 "UMask": "0x8" 165 }, 166 { 167 "BriefDescription": "L2 code requests", 168 "Counter": "0,1,2,3", 169 "EventCode": "0x24", 170 "EventName": "L2_RQSTS.ALL_CODE_RD", 171 "PublicDescription": "Counts all L2 code requests.", 172 "SampleAfterValue": "200003", 173 "UMask": "0x30" 174 }, 175 { 176 "BriefDescription": "Demand Data Read requests", 177 "Counter": "0,1,2,3", 178 "EventCode": "0x24", 179 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 180 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 181 "SampleAfterValue": "200003", 182 "UMask": "0x3" 183 }, 184 { 185 "BriefDescription": "Requests from L2 hardware prefetchers", 186 "Counter": "0,1,2,3", 187 "EventCode": "0x24", 188 "EventName": "L2_RQSTS.ALL_PF", 189 "PublicDescription": "Counts all L2 HW prefetcher requests.", 190 "SampleAfterValue": "200003", 191 "UMask": "0xc0" 192 }, 193 { 194 "BriefDescription": "RFO requests to L2 cache", 195 "Counter": "0,1,2,3", 196 "EventCode": "0x24", 197 "EventName": "L2_RQSTS.ALL_RFO", 198 "PublicDescription": "Counts all L2 store RFO requests.", 199 "SampleAfterValue": "200003", 200 "UMask": "0xc" 201 }, 202 { 203 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 204 "Counter": "0,1,2,3", 205 "EventCode": "0x24", 206 "EventName": "L2_RQSTS.CODE_RD_HIT", 207 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 208 "SampleAfterValue": "200003", 209 "UMask": "0x10" 210 }, 211 { 212 "BriefDescription": "L2 cache misses when fetching instructions", 213 "Counter": "0,1,2,3", 214 "EventCode": "0x24", 215 "EventName": "L2_RQSTS.CODE_RD_MISS", 216 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 217 "SampleAfterValue": "200003", 218 "UMask": "0x20" 219 }, 220 { 221 "BriefDescription": "Demand Data Read requests that hit L2 cache", 222 "Counter": "0,1,2,3", 223 "EventCode": "0x24", 224 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 225 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 226 "SampleAfterValue": "200003", 227 "UMask": "0x1" 228 }, 229 { 230 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 231 "Counter": "0,1,2,3", 232 "EventCode": "0x24", 233 "EventName": "L2_RQSTS.PF_HIT", 234 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 235 "SampleAfterValue": "200003", 236 "UMask": "0x40" 237 }, 238 { 239 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", 240 "Counter": "0,1,2,3", 241 "EventCode": "0x24", 242 "EventName": "L2_RQSTS.PF_MISS", 243 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 244 "SampleAfterValue": "200003", 245 "UMask": "0x80" 246 }, 247 { 248 "BriefDescription": "RFO requests that hit L2 cache", 249 "Counter": "0,1,2,3", 250 "EventCode": "0x24", 251 "EventName": "L2_RQSTS.RFO_HIT", 252 "PublicDescription": "RFO requests that hit L2 cache.", 253 "SampleAfterValue": "200003", 254 "UMask": "0x4" 255 }, 256 { 257 "BriefDescription": "RFO requests that miss L2 cache", 258 "Counter": "0,1,2,3", 259 "EventCode": "0x24", 260 "EventName": "L2_RQSTS.RFO_MISS", 261 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 262 "SampleAfterValue": "200003", 263 "UMask": "0x8" 264 }, 265 { 266 "BriefDescription": "RFOs that access cache lines in any state", 267 "Counter": "0,1,2,3", 268 "EventCode": "0x27", 269 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 270 "PublicDescription": "RFOs that access cache lines in any state.", 271 "SampleAfterValue": "200003", 272 "UMask": "0xf" 273 }, 274 { 275 "BriefDescription": "RFOs that hit cache lines in M state", 276 "Counter": "0,1,2,3", 277 "EventCode": "0x27", 278 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 279 "PublicDescription": "RFOs that hit cache lines in M state.", 280 "SampleAfterValue": "200003", 281 "UMask": "0x8" 282 }, 283 { 284 "BriefDescription": "RFOs that miss cache lines", 285 "Counter": "0,1,2,3", 286 "EventCode": "0x27", 287 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 288 "PublicDescription": "RFOs that miss cache lines.", 289 "SampleAfterValue": "200003", 290 "UMask": "0x1" 291 }, 292 { 293 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", 294 "Counter": "0,1,2,3", 295 "EventCode": "0xF0", 296 "EventName": "L2_TRANS.ALL_PF", 297 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", 298 "SampleAfterValue": "200003", 299 "UMask": "0x8" 300 }, 301 { 302 "BriefDescription": "Transactions accessing L2 pipe", 303 "Counter": "0,1,2,3", 304 "EventCode": "0xF0", 305 "EventName": "L2_TRANS.ALL_REQUESTS", 306 "PublicDescription": "Transactions accessing L2 pipe.", 307 "SampleAfterValue": "200003", 308 "UMask": "0x80" 309 }, 310 { 311 "BriefDescription": "L2 cache accesses when fetching instructions", 312 "Counter": "0,1,2,3", 313 "EventCode": "0xF0", 314 "EventName": "L2_TRANS.CODE_RD", 315 "PublicDescription": "L2 cache accesses when fetching instructions.", 316 "SampleAfterValue": "200003", 317 "UMask": "0x4" 318 }, 319 { 320 "BriefDescription": "Demand Data Read requests that access L2 cache", 321 "Counter": "0,1,2,3", 322 "EventCode": "0xF0", 323 "EventName": "L2_TRANS.DEMAND_DATA_RD", 324 "PublicDescription": "Demand Data Read requests that access L2 cache.", 325 "SampleAfterValue": "200003", 326 "UMask": "0x1" 327 }, 328 { 329 "BriefDescription": "L1D writebacks that access L2 cache", 330 "Counter": "0,1,2,3", 331 "EventCode": "0xF0", 332 "EventName": "L2_TRANS.L1D_WB", 333 "PublicDescription": "L1D writebacks that access L2 cache.", 334 "SampleAfterValue": "200003", 335 "UMask": "0x10" 336 }, 337 { 338 "BriefDescription": "L2 fill requests that access L2 cache", 339 "Counter": "0,1,2,3", 340 "EventCode": "0xF0", 341 "EventName": "L2_TRANS.L2_FILL", 342 "PublicDescription": "L2 fill requests that access L2 cache.", 343 "SampleAfterValue": "200003", 344 "UMask": "0x20" 345 }, 346 { 347 "BriefDescription": "L2 writebacks that access L2 cache", 348 "Counter": "0,1,2,3", 349 "EventCode": "0xF0", 350 "EventName": "L2_TRANS.L2_WB", 351 "PublicDescription": "L2 writebacks that access L2 cache.", 352 "SampleAfterValue": "200003", 353 "UMask": "0x40" 354 }, 355 { 356 "BriefDescription": "RFO requests that access L2 cache", 357 "Counter": "0,1,2,3", 358 "EventCode": "0xF0", 359 "EventName": "L2_TRANS.RFO", 360 "PublicDescription": "RFO requests that access L2 cache.", 361 "SampleAfterValue": "200003", 362 "UMask": "0x2" 363 }, 364 { 365 "BriefDescription": "Cycles when L1D is locked", 366 "Counter": "0,1,2,3", 367 "EventCode": "0x63", 368 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 369 "PublicDescription": "Cycles in which the L1D is locked.", 370 "SampleAfterValue": "2000003", 371 "UMask": "0x2" 372 }, 373 { 374 "BriefDescription": "Core-originated cacheable demand requests missed LLC", 375 "Counter": "0,1,2,3", 376 "EventCode": "0x2E", 377 "EventName": "LONGEST_LAT_CACHE.MISS", 378 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 379 "SampleAfterValue": "100003", 380 "UMask": "0x41" 381 }, 382 { 383 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", 384 "Counter": "0,1,2,3", 385 "EventCode": "0x2E", 386 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 387 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 388 "SampleAfterValue": "100003", 389 "UMask": "0x4f" 390 }, 391 { 392 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", 393 "Counter": "0,1,2,3", 394 "EventCode": "0xD2", 395 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 396 "PEBS": "1", 397 "SampleAfterValue": "20011", 398 "UMask": "0x2" 399 }, 400 { 401 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", 402 "Counter": "0,1,2,3", 403 "EventCode": "0xD2", 404 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 405 "PEBS": "1", 406 "SampleAfterValue": "20011", 407 "UMask": "0x4" 408 }, 409 { 410 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", 411 "Counter": "0,1,2,3", 412 "EventCode": "0xD2", 413 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 414 "PEBS": "1", 415 "SampleAfterValue": "20011", 416 "UMask": "0x1" 417 }, 418 { 419 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", 420 "Counter": "0,1,2,3", 421 "EventCode": "0xD2", 422 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 423 "PEBS": "1", 424 "SampleAfterValue": "100003", 425 "UMask": "0x8" 426 }, 427 { 428 "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", 429 "Counter": "0,1,2,3", 430 "EventCode": "0xD3", 431 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 432 "SampleAfterValue": "100007", 433 "UMask": "0x3" 434 }, 435 { 436 "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", 437 "Counter": "0,1,2,3", 438 "EventCode": "0xD3", 439 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", 440 "SampleAfterValue": "100007", 441 "UMask": "0xc" 442 }, 443 { 444 "BriefDescription": "Data forwarded from remote cache.", 445 "Counter": "0,1,2,3", 446 "EventCode": "0xD3", 447 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", 448 "SampleAfterValue": "100007", 449 "UMask": "0x20" 450 }, 451 { 452 "BriefDescription": "Remote cache HITM.", 453 "Counter": "0,1,2,3", 454 "EventCode": "0xD3", 455 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", 456 "SampleAfterValue": "100007", 457 "UMask": "0x10" 458 }, 459 { 460 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 461 "Counter": "0,1,2,3", 462 "EventCode": "0xD1", 463 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 464 "PEBS": "1", 465 "SampleAfterValue": "100003", 466 "UMask": "0x40" 467 }, 468 { 469 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 470 "Counter": "0,1,2,3", 471 "EventCode": "0xD1", 472 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 473 "PEBS": "1", 474 "SampleAfterValue": "2000003", 475 "UMask": "0x1" 476 }, 477 { 478 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", 479 "Counter": "0,1,2,3", 480 "EventCode": "0xD1", 481 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 482 "PEBS": "1", 483 "SampleAfterValue": "100003", 484 "UMask": "0x8" 485 }, 486 { 487 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 488 "Counter": "0,1,2,3", 489 "EventCode": "0xD1", 490 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 491 "PEBS": "1", 492 "SampleAfterValue": "100003", 493 "UMask": "0x2" 494 }, 495 { 496 "BriefDescription": "Retired load uops with L2 cache misses as data sources.", 497 "Counter": "0,1,2,3", 498 "EventCode": "0xD1", 499 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 500 "PEBS": "1", 501 "SampleAfterValue": "50021", 502 "UMask": "0x10" 503 }, 504 { 505 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", 506 "Counter": "0,1,2,3", 507 "EventCode": "0xD1", 508 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 509 "PEBS": "1", 510 "SampleAfterValue": "50021", 511 "UMask": "0x4" 512 }, 513 { 514 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 515 "Counter": "0,1,2,3", 516 "EventCode": "0xD1", 517 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 518 "PEBS": "1", 519 "SampleAfterValue": "100007", 520 "UMask": "0x20" 521 }, 522 { 523 "BriefDescription": "All retired load uops. (Precise Event)", 524 "Counter": "0,1,2,3", 525 "EventCode": "0xD0", 526 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 527 "PEBS": "1", 528 "SampleAfterValue": "2000003", 529 "UMask": "0x81" 530 }, 531 { 532 "BriefDescription": "All retired store uops. (Precise Event)", 533 "Counter": "0,1,2,3", 534 "EventCode": "0xD0", 535 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 536 "PEBS": "1", 537 "SampleAfterValue": "2000003", 538 "UMask": "0x82" 539 }, 540 { 541 "BriefDescription": "Retired load uops with locked access. (Precise Event)", 542 "Counter": "0,1,2,3", 543 "EventCode": "0xD0", 544 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 545 "PEBS": "1", 546 "SampleAfterValue": "100007", 547 "UMask": "0x21" 548 }, 549 { 550 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", 551 "Counter": "0,1,2,3", 552 "EventCode": "0xD0", 553 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 554 "PEBS": "1", 555 "SampleAfterValue": "100003", 556 "UMask": "0x41" 557 }, 558 { 559 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", 560 "Counter": "0,1,2,3", 561 "EventCode": "0xD0", 562 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 563 "PEBS": "1", 564 "SampleAfterValue": "100003", 565 "UMask": "0x42" 566 }, 567 { 568 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", 569 "Counter": "0,1,2,3", 570 "EventCode": "0xD0", 571 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 572 "PEBS": "1", 573 "SampleAfterValue": "100003", 574 "UMask": "0x11" 575 }, 576 { 577 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", 578 "Counter": "0,1,2,3", 579 "EventCode": "0xD0", 580 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 581 "PEBS": "1", 582 "SampleAfterValue": "100003", 583 "UMask": "0x12" 584 }, 585 { 586 "BriefDescription": "Demand and prefetch data reads", 587 "Counter": "0,1,2,3", 588 "EventCode": "0xB0", 589 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 590 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 591 "SampleAfterValue": "100003", 592 "UMask": "0x8" 593 }, 594 { 595 "BriefDescription": "Cacheable and noncacheable code read requests", 596 "Counter": "0,1,2,3", 597 "EventCode": "0xB0", 598 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 599 "PublicDescription": "Demand code read requests sent to uncore.", 600 "SampleAfterValue": "100003", 601 "UMask": "0x2" 602 }, 603 { 604 "BriefDescription": "Demand Data Read requests sent to uncore", 605 "Counter": "0,1,2,3", 606 "EventCode": "0xB0", 607 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 608 "PublicDescription": "Demand data read requests sent to uncore.", 609 "SampleAfterValue": "100003", 610 "UMask": "0x1" 611 }, 612 { 613 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 614 "Counter": "0,1,2,3", 615 "EventCode": "0xB0", 616 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 617 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 618 "SampleAfterValue": "100003", 619 "UMask": "0x4" 620 }, 621 { 622 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", 623 "Counter": "0,1,2,3", 624 "EventCode": "0xB2", 625 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 626 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", 627 "SampleAfterValue": "2000003", 628 "UMask": "0x1" 629 }, 630 { 631 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 632 "Counter": "0,1,2,3", 633 "EventCode": "0x60", 634 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 635 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 636 "SampleAfterValue": "2000003", 637 "UMask": "0x8" 638 }, 639 { 640 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 641 "Counter": "0,1,2,3", 642 "CounterMask": "1", 643 "EventCode": "0x60", 644 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 645 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 646 "SampleAfterValue": "2000003", 647 "UMask": "0x8" 648 }, 649 { 650 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 651 "Counter": "0,1,2,3", 652 "CounterMask": "1", 653 "EventCode": "0x60", 654 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 655 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 656 "SampleAfterValue": "2000003", 657 "UMask": "0x2" 658 }, 659 { 660 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 661 "Counter": "0,1,2,3", 662 "CounterMask": "1", 663 "EventCode": "0x60", 664 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 665 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 666 "SampleAfterValue": "2000003", 667 "UMask": "0x1" 668 }, 669 { 670 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 671 "Counter": "0,1,2,3", 672 "CounterMask": "1", 673 "EventCode": "0x60", 674 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 675 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 676 "SampleAfterValue": "2000003", 677 "UMask": "0x4" 678 }, 679 { 680 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 681 "Counter": "0,1,2,3", 682 "EventCode": "0x60", 683 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 684 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 685 "SampleAfterValue": "2000003", 686 "UMask": "0x2" 687 }, 688 { 689 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 690 "Counter": "0,1,2,3", 691 "EventCode": "0x60", 692 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 693 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 694 "SampleAfterValue": "2000003", 695 "UMask": "0x1" 696 }, 697 { 698 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", 699 "Counter": "0,1,2,3", 700 "CounterMask": "6", 701 "EventCode": "0x60", 702 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 703 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 704 "SampleAfterValue": "2000003", 705 "UMask": "0x1" 706 }, 707 { 708 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 709 "Counter": "0,1,2,3", 710 "EventCode": "0x60", 711 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 712 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 713 "SampleAfterValue": "2000003", 714 "UMask": "0x4" 715 }, 716 { 717 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 718 "Counter": "0,1,2,3", 719 "EventCode": "0xB7, 0xBB", 720 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 721 "MSRIndex": "0x1a6,0x1a7", 722 "MSRValue": "0x10003c0091", 723 "SampleAfterValue": "100003", 724 "UMask": "0x1" 725 }, 726 { 727 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 728 "Counter": "0,1,2,3", 729 "EventCode": "0xB7, 0xBB", 730 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 731 "MSRIndex": "0x1a6,0x1a7", 732 "MSRValue": "0x4003c0091", 733 "SampleAfterValue": "100003", 734 "UMask": "0x1" 735 }, 736 { 737 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 738 "Counter": "0,1,2,3", 739 "EventCode": "0xB7, 0xBB", 740 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 741 "MSRIndex": "0x1a6,0x1a7", 742 "MSRValue": "0x1003c0091", 743 "SampleAfterValue": "100003", 744 "UMask": "0x1" 745 }, 746 { 747 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 748 "Counter": "0,1,2,3", 749 "EventCode": "0xB7, 0xBB", 750 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", 751 "MSRIndex": "0x1a6,0x1a7", 752 "MSRValue": "0x2003c0091", 753 "SampleAfterValue": "100003", 754 "UMask": "0x1" 755 }, 756 { 757 "BriefDescription": "Counts all prefetch data reads that hit the LLC", 758 "Counter": "0,1,2,3", 759 "EventCode": "0xB7, 0xBB", 760 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", 761 "MSRIndex": "0x1a6,0x1a7", 762 "MSRValue": "0x3f803c0090", 763 "SampleAfterValue": "100003", 764 "UMask": "0x1" 765 }, 766 { 767 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 768 "Counter": "0,1,2,3", 769 "EventCode": "0xB7, 0xBB", 770 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 771 "MSRIndex": "0x1a6,0x1a7", 772 "MSRValue": "0x10003c0090", 773 "SampleAfterValue": "100003", 774 "UMask": "0x1" 775 }, 776 { 777 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 778 "Counter": "0,1,2,3", 779 "EventCode": "0xB7, 0xBB", 780 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 781 "MSRIndex": "0x1a6,0x1a7", 782 "MSRValue": "0x4003c0090", 783 "SampleAfterValue": "100003", 784 "UMask": "0x1" 785 }, 786 { 787 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 788 "Counter": "0,1,2,3", 789 "EventCode": "0xB7, 0xBB", 790 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 791 "MSRIndex": "0x1a6,0x1a7", 792 "MSRValue": "0x1003c0090", 793 "SampleAfterValue": "100003", 794 "UMask": "0x1" 795 }, 796 { 797 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", 798 "Counter": "0,1,2,3", 799 "EventCode": "0xB7, 0xBB", 800 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", 801 "MSRIndex": "0x1a6,0x1a7", 802 "MSRValue": "0x2003c0090", 803 "SampleAfterValue": "100003", 804 "UMask": "0x1" 805 }, 806 { 807 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", 808 "Counter": "0,1,2,3", 809 "EventCode": "0xB7, 0xBB", 810 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", 811 "MSRIndex": "0x1a6,0x1a7", 812 "MSRValue": "0x3f803c03f7", 813 "SampleAfterValue": "100003", 814 "UMask": "0x1" 815 }, 816 { 817 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 818 "Counter": "0,1,2,3", 819 "EventCode": "0xB7, 0xBB", 820 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", 821 "MSRIndex": "0x1a6,0x1a7", 822 "MSRValue": "0x10003c03f7", 823 "SampleAfterValue": "100003", 824 "UMask": "0x1" 825 }, 826 { 827 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 828 "Counter": "0,1,2,3", 829 "EventCode": "0xB7, 0xBB", 830 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 831 "MSRIndex": "0x1a6,0x1a7", 832 "MSRValue": "0x4003c03f7", 833 "SampleAfterValue": "100003", 834 "UMask": "0x1" 835 }, 836 { 837 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 838 "Counter": "0,1,2,3", 839 "EventCode": "0xB7, 0xBB", 840 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", 841 "MSRIndex": "0x1a6,0x1a7", 842 "MSRValue": "0x1003c03f7", 843 "SampleAfterValue": "100003", 844 "UMask": "0x1" 845 }, 846 { 847 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", 848 "Counter": "0,1,2,3", 849 "EventCode": "0xB7, 0xBB", 850 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", 851 "MSRIndex": "0x1a6,0x1a7", 852 "MSRValue": "0x2003c03f7", 853 "SampleAfterValue": "100003", 854 "UMask": "0x1" 855 }, 856 { 857 "BriefDescription": "Counts all writebacks from the core to the LLC", 858 "Counter": "0,1,2,3", 859 "EventCode": "0xB7, 0xBB", 860 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 861 "MSRIndex": "0x1a6,0x1a7", 862 "MSRValue": "0x10008", 863 "SampleAfterValue": "100003", 864 "UMask": "0x1" 865 }, 866 { 867 "BriefDescription": "Counts all demand code reads that hit in the LLC", 868 "Counter": "0,1,2,3", 869 "EventCode": "0xB7, 0xBB", 870 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 871 "MSRIndex": "0x1a6,0x1a7", 872 "MSRValue": "0x3f803c0004", 873 "SampleAfterValue": "100003", 874 "UMask": "0x1" 875 }, 876 { 877 "BriefDescription": "Counts all demand data reads that hit in the LLC", 878 "Counter": "0,1,2,3", 879 "EventCode": "0xB7, 0xBB", 880 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 881 "MSRIndex": "0x1a6,0x1a7", 882 "MSRValue": "0x3f803c0001", 883 "SampleAfterValue": "100003", 884 "UMask": "0x1" 885 }, 886 { 887 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 888 "Counter": "0,1,2,3", 889 "EventCode": "0xB7, 0xBB", 890 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 891 "MSRIndex": "0x1a6,0x1a7", 892 "MSRValue": "0x10003c0001", 893 "SampleAfterValue": "100003", 894 "UMask": "0x1" 895 }, 896 { 897 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 898 "Counter": "0,1,2,3", 899 "EventCode": "0xB7, 0xBB", 900 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 901 "MSRIndex": "0x1a6,0x1a7", 902 "MSRValue": "0x4003c0001", 903 "SampleAfterValue": "100003", 904 "UMask": "0x1" 905 }, 906 { 907 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 908 "Counter": "0,1,2,3", 909 "EventCode": "0xB7, 0xBB", 910 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 911 "MSRIndex": "0x1a6,0x1a7", 912 "MSRValue": "0x1003c0001", 913 "SampleAfterValue": "100003", 914 "UMask": "0x1" 915 }, 916 { 917 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", 918 "Counter": "0,1,2,3", 919 "EventCode": "0xB7, 0xBB", 920 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", 921 "MSRIndex": "0x1a6,0x1a7", 922 "MSRValue": "0x2003c0001", 923 "SampleAfterValue": "100003", 924 "UMask": "0x1" 925 }, 926 { 927 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 928 "Counter": "0,1,2,3", 929 "EventCode": "0xB7, 0xBB", 930 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 931 "MSRIndex": "0x1a6,0x1a7", 932 "MSRValue": "0x10003c0002", 933 "SampleAfterValue": "100003", 934 "UMask": "0x1" 935 }, 936 { 937 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", 938 "Counter": "0,1,2,3", 939 "EventCode": "0xB7, 0xBB", 940 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", 941 "MSRIndex": "0x1a6,0x1a7", 942 "MSRValue": "0x803c8000", 943 "SampleAfterValue": "100003", 944 "UMask": "0x1" 945 }, 946 { 947 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", 948 "Counter": "0,1,2,3", 949 "EventCode": "0xB7, 0xBB", 950 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", 951 "MSRIndex": "0x1a6,0x1a7", 952 "MSRValue": "0x23ffc08000", 953 "SampleAfterValue": "100003", 954 "UMask": "0x1" 955 }, 956 { 957 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", 958 "Counter": "0,1,2,3", 959 "EventCode": "0xB7, 0xBB", 960 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", 961 "MSRIndex": "0x1a6,0x1a7", 962 "MSRValue": "0x3f803c0040", 963 "SampleAfterValue": "100003", 964 "UMask": "0x1" 965 }, 966 { 967 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", 968 "Counter": "0,1,2,3", 969 "EventCode": "0xB7, 0xBB", 970 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", 971 "MSRIndex": "0x1a6,0x1a7", 972 "MSRValue": "0x3f803c0010", 973 "SampleAfterValue": "100003", 974 "UMask": "0x1" 975 }, 976 { 977 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 978 "Counter": "0,1,2,3", 979 "EventCode": "0xB7, 0xBB", 980 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 981 "MSRIndex": "0x1a6,0x1a7", 982 "MSRValue": "0x10003c0010", 983 "SampleAfterValue": "100003", 984 "UMask": "0x1" 985 }, 986 { 987 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 988 "Counter": "0,1,2,3", 989 "EventCode": "0xB7, 0xBB", 990 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 991 "MSRIndex": "0x1a6,0x1a7", 992 "MSRValue": "0x4003c0010", 993 "SampleAfterValue": "100003", 994 "UMask": "0x1" 995 }, 996 { 997 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 998 "Counter": "0,1,2,3", 999 "EventCode": "0xB7, 0xBB", 1000 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1001 "MSRIndex": "0x1a6,0x1a7", 1002 "MSRValue": "0x1003c0010", 1003 "SampleAfterValue": "100003", 1004 "UMask": "0x1" 1005 }, 1006 { 1007 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1008 "Counter": "0,1,2,3", 1009 "EventCode": "0xB7, 0xBB", 1010 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", 1011 "MSRIndex": "0x1a6,0x1a7", 1012 "MSRValue": "0x2003c0010", 1013 "SampleAfterValue": "100003", 1014 "UMask": "0x1" 1015 }, 1016 { 1017 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", 1018 "Counter": "0,1,2,3", 1019 "EventCode": "0xB7, 0xBB", 1020 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", 1021 "MSRIndex": "0x1a6,0x1a7", 1022 "MSRValue": "0x3f803c0200", 1023 "SampleAfterValue": "100003", 1024 "UMask": "0x1" 1025 }, 1026 { 1027 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", 1028 "Counter": "0,1,2,3", 1029 "EventCode": "0xB7, 0xBB", 1030 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", 1031 "MSRIndex": "0x1a6,0x1a7", 1032 "MSRValue": "0x3f803c0080", 1033 "SampleAfterValue": "100003", 1034 "UMask": "0x1" 1035 }, 1036 { 1037 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1038 "Counter": "0,1,2,3", 1039 "EventCode": "0xB7, 0xBB", 1040 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 1041 "MSRIndex": "0x1a6,0x1a7", 1042 "MSRValue": "0x10003c0080", 1043 "SampleAfterValue": "100003", 1044 "UMask": "0x1" 1045 }, 1046 { 1047 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1048 "Counter": "0,1,2,3", 1049 "EventCode": "0xB7, 0xBB", 1050 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 1051 "MSRIndex": "0x1a6,0x1a7", 1052 "MSRValue": "0x4003c0080", 1053 "SampleAfterValue": "100003", 1054 "UMask": "0x1" 1055 }, 1056 { 1057 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 1058 "Counter": "0,1,2,3", 1059 "EventCode": "0xB7, 0xBB", 1060 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 1061 "MSRIndex": "0x1a6,0x1a7", 1062 "MSRValue": "0x1003c0080", 1063 "SampleAfterValue": "100003", 1064 "UMask": "0x1" 1065 }, 1066 { 1067 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", 1068 "Counter": "0,1,2,3", 1069 "EventCode": "0xB7, 0xBB", 1070 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", 1071 "MSRIndex": "0x1a6,0x1a7", 1072 "MSRValue": "0x2003c0080", 1073 "SampleAfterValue": "100003", 1074 "UMask": "0x1" 1075 }, 1076 { 1077 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", 1078 "Counter": "0,1,2,3", 1079 "EventCode": "0xB7, 0xBB", 1080 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1081 "MSRIndex": "0x1a6,0x1a7", 1082 "MSRValue": "0x10400", 1083 "SampleAfterValue": "100003", 1084 "UMask": "0x1" 1085 }, 1086 { 1087 "BriefDescription": "Counts non-temporal stores", 1088 "Counter": "0,1,2,3", 1089 "EventCode": "0xB7, 0xBB", 1090 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1091 "MSRIndex": "0x1a6,0x1a7", 1092 "MSRValue": "0x10800", 1093 "SampleAfterValue": "100003", 1094 "UMask": "0x1" 1095 }, 1096 { 1097 "BriefDescription": "Split locks in SQ", 1098 "Counter": "0,1,2,3", 1099 "EventCode": "0xF4", 1100 "EventName": "SQ_MISC.SPLIT_LOCK", 1101 "SampleAfterValue": "100003", 1102 "UMask": "0x10" 1103 } 1104] 1105