1[ 2 { 3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 4 "EventCode": "0x5C", 5 "EventName": "CPL_CYCLES.RING0", 6 "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", 7 "SampleAfterValue": "2000003", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 12 "CounterMask": "1", 13 "EdgeDetect": "1", 14 "EventCode": "0x5C", 15 "EventName": "CPL_CYCLES.RING0_TRANS", 16 "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", 17 "SampleAfterValue": "100007", 18 "UMask": "0x1" 19 }, 20 { 21 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 22 "EventCode": "0x5C", 23 "EventName": "CPL_CYCLES.RING123", 24 "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", 25 "SampleAfterValue": "2000003", 26 "UMask": "0x2" 27 }, 28 { 29 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 30 "EventCode": "0x63", 31 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 32 "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", 33 "SampleAfterValue": "2000003", 34 "UMask": "0x1" 35 } 36] 37