xref: /linux/tools/perf/pmu-events/arch/x86/ivybridge/other.json (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
14b90798eSAndi Kleen[
24b90798eSAndi Kleen    {
34b90798eSAndi Kleen        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
4*238a2117SIan Rogers        "Counter": "0,1,2,3",
5e0f6eeefSIan Rogers        "EventCode": "0x5C",
6e0f6eeefSIan Rogers        "EventName": "CPL_CYCLES.RING0",
7e0f6eeefSIan Rogers        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
8e0f6eeefSIan Rogers        "SampleAfterValue": "2000003",
9e0f6eeefSIan Rogers        "UMask": "0x1"
104b90798eSAndi Kleen    },
114b90798eSAndi Kleen    {
124b90798eSAndi Kleen        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
13*238a2117SIan Rogers        "Counter": "0,1,2,3",
144b90798eSAndi Kleen        "CounterMask": "1",
15e0f6eeefSIan Rogers        "EdgeDetect": "1",
16c955cd2bSAndi Kleen        "EventCode": "0x5C",
17e0f6eeefSIan Rogers        "EventName": "CPL_CYCLES.RING0_TRANS",
18e0f6eeefSIan Rogers        "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
19e0f6eeefSIan Rogers        "SampleAfterValue": "100007",
20e0f6eeefSIan Rogers        "UMask": "0x1"
21c955cd2bSAndi Kleen    },
22c955cd2bSAndi Kleen    {
23e0f6eeefSIan Rogers        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
24*238a2117SIan Rogers        "Counter": "0,1,2,3",
25e0f6eeefSIan Rogers        "EventCode": "0x5C",
26e0f6eeefSIan Rogers        "EventName": "CPL_CYCLES.RING123",
27e0f6eeefSIan Rogers        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
284b90798eSAndi Kleen        "SampleAfterValue": "2000003",
29e0f6eeefSIan Rogers        "UMask": "0x2"
30e0f6eeefSIan Rogers    },
31e0f6eeefSIan Rogers    {
324b90798eSAndi Kleen        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
33*238a2117SIan Rogers        "Counter": "0,1,2,3",
34e0f6eeefSIan Rogers        "EventCode": "0x63",
35e0f6eeefSIan Rogers        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
36e0f6eeefSIan Rogers        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
37e0f6eeefSIan Rogers        "SampleAfterValue": "2000003",
38e0f6eeefSIan Rogers        "UMask": "0x1"
394b90798eSAndi Kleen    }
404b90798eSAndi Kleen]
41