1[ 2 { 3 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 4 "EventCode": "0xC3", 5 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 6 "SampleAfterValue": "100003", 7 "UMask": "0x2" 8 }, 9 { 10 "BriefDescription": "Loads with latency value being above 128", 11 "EventCode": "0xCD", 12 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 13 "MSRIndex": "0x3F6", 14 "MSRValue": "0x80", 15 "PEBS": "2", 16 "PublicDescription": "Loads with latency value being above 128.", 17 "SampleAfterValue": "1009", 18 "UMask": "0x1" 19 }, 20 { 21 "BriefDescription": "Loads with latency value being above 16", 22 "EventCode": "0xCD", 23 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 24 "MSRIndex": "0x3F6", 25 "MSRValue": "0x10", 26 "PEBS": "2", 27 "PublicDescription": "Loads with latency value being above 16.", 28 "SampleAfterValue": "20011", 29 "UMask": "0x1" 30 }, 31 { 32 "BriefDescription": "Loads with latency value being above 256", 33 "EventCode": "0xCD", 34 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 35 "MSRIndex": "0x3F6", 36 "MSRValue": "0x100", 37 "PEBS": "2", 38 "PublicDescription": "Loads with latency value being above 256.", 39 "SampleAfterValue": "503", 40 "UMask": "0x1" 41 }, 42 { 43 "BriefDescription": "Loads with latency value being above 32", 44 "EventCode": "0xCD", 45 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 46 "MSRIndex": "0x3F6", 47 "MSRValue": "0x20", 48 "PEBS": "2", 49 "PublicDescription": "Loads with latency value being above 32.", 50 "SampleAfterValue": "100007", 51 "UMask": "0x1" 52 }, 53 { 54 "BriefDescription": "Loads with latency value being above 4", 55 "EventCode": "0xCD", 56 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 57 "MSRIndex": "0x3F6", 58 "MSRValue": "0x4", 59 "PEBS": "2", 60 "PublicDescription": "Loads with latency value being above 4.", 61 "SampleAfterValue": "100003", 62 "UMask": "0x1" 63 }, 64 { 65 "BriefDescription": "Loads with latency value being above 512", 66 "EventCode": "0xCD", 67 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 68 "MSRIndex": "0x3F6", 69 "MSRValue": "0x200", 70 "PEBS": "2", 71 "PublicDescription": "Loads with latency value being above 512.", 72 "SampleAfterValue": "101", 73 "UMask": "0x1" 74 }, 75 { 76 "BriefDescription": "Loads with latency value being above 64", 77 "EventCode": "0xCD", 78 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 79 "MSRIndex": "0x3F6", 80 "MSRValue": "0x40", 81 "PEBS": "2", 82 "PublicDescription": "Loads with latency value being above 64.", 83 "SampleAfterValue": "2003", 84 "UMask": "0x1" 85 }, 86 { 87 "BriefDescription": "Loads with latency value being above 8", 88 "EventCode": "0xCD", 89 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 90 "MSRIndex": "0x3F6", 91 "MSRValue": "0x8", 92 "PEBS": "2", 93 "PublicDescription": "Loads with latency value being above 8.", 94 "SampleAfterValue": "50021", 95 "UMask": "0x1" 96 }, 97 { 98 "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", 99 "EventCode": "0xCD", 100 "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", 101 "PEBS": "2", 102 "SampleAfterValue": "2000003", 103 "UMask": "0x2" 104 }, 105 { 106 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 107 "EventCode": "0x05", 108 "EventName": "MISALIGN_MEM_REF.LOADS", 109 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 110 "SampleAfterValue": "2000003", 111 "UMask": "0x1" 112 }, 113 { 114 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 115 "EventCode": "0x05", 116 "EventName": "MISALIGN_MEM_REF.STORES", 117 "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", 118 "SampleAfterValue": "2000003", 119 "UMask": "0x2" 120 }, 121 { 122 "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", 123 "EventCode": "0xB7, 0xBB", 124 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", 125 "MSRIndex": "0x1a6,0x1a7", 126 "MSRValue": "0x300400244", 127 "SampleAfterValue": "100003", 128 "UMask": "0x1" 129 }, 130 { 131 "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", 132 "EventCode": "0xB7, 0xBB", 133 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", 134 "MSRIndex": "0x1a6,0x1a7", 135 "MSRValue": "0x300400091", 136 "SampleAfterValue": "100003", 137 "UMask": "0x1" 138 }, 139 { 140 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", 141 "EventCode": "0xB7, 0xBB", 142 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", 143 "MSRIndex": "0x1a6,0x1a7", 144 "MSRValue": "0x3004003f7", 145 "SampleAfterValue": "100003", 146 "UMask": "0x1" 147 }, 148 { 149 "BriefDescription": "Counts LLC replacements", 150 "EventCode": "0xB7, 0xBB", 151 "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", 152 "MSRIndex": "0x1a6,0x1a7", 153 "MSRValue": "0x6004001b3", 154 "SampleAfterValue": "100003", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", 159 "EventCode": "0xB7, 0xBB", 160 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", 161 "MSRIndex": "0x1a6,0x1a7", 162 "MSRValue": "0x300400004", 163 "SampleAfterValue": "100003", 164 "UMask": "0x1" 165 }, 166 { 167 "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", 168 "EventCode": "0xB7, 0xBB", 169 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", 170 "MSRIndex": "0x1a6,0x1a7", 171 "MSRValue": "0x300400001", 172 "SampleAfterValue": "100003", 173 "UMask": "0x1" 174 }, 175 { 176 "BriefDescription": "Number of any page walk that had a miss in LLC.", 177 "EventCode": "0xBE", 178 "EventName": "PAGE_WALKS.LLC_MISS", 179 "SampleAfterValue": "100003", 180 "UMask": "0x1" 181 } 182] 183