1[ 2 { 3 "PublicDescription": "Demand Data Read requests that hit L2 cache.", 4 "EventCode": "0x24", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 8 "SampleAfterValue": "200003", 9 "BriefDescription": "Demand Data Read requests that hit L2 cache", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 14 "EventCode": "0x24", 15 "Counter": "0,1,2,3", 16 "UMask": "0x3", 17 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 18 "SampleAfterValue": "200003", 19 "BriefDescription": "Demand Data Read requests", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "RFO requests that hit L2 cache.", 24 "EventCode": "0x24", 25 "Counter": "0,1,2,3", 26 "UMask": "0x4", 27 "EventName": "L2_RQSTS.RFO_HIT", 28 "SampleAfterValue": "200003", 29 "BriefDescription": "RFO requests that hit L2 cache", 30 "CounterHTOff": "0,1,2,3,4,5,6,7" 31 }, 32 { 33 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 34 "EventCode": "0x24", 35 "Counter": "0,1,2,3", 36 "UMask": "0x8", 37 "EventName": "L2_RQSTS.RFO_MISS", 38 "SampleAfterValue": "200003", 39 "BriefDescription": "RFO requests that miss L2 cache", 40 "CounterHTOff": "0,1,2,3,4,5,6,7" 41 }, 42 { 43 "PublicDescription": "Counts all L2 store RFO requests.", 44 "EventCode": "0x24", 45 "Counter": "0,1,2,3", 46 "UMask": "0xc", 47 "EventName": "L2_RQSTS.ALL_RFO", 48 "SampleAfterValue": "200003", 49 "BriefDescription": "RFO requests to L2 cache", 50 "CounterHTOff": "0,1,2,3,4,5,6,7" 51 }, 52 { 53 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 54 "EventCode": "0x24", 55 "Counter": "0,1,2,3", 56 "UMask": "0x10", 57 "EventName": "L2_RQSTS.CODE_RD_HIT", 58 "SampleAfterValue": "200003", 59 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 60 "CounterHTOff": "0,1,2,3,4,5,6,7" 61 }, 62 { 63 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 64 "EventCode": "0x24", 65 "Counter": "0,1,2,3", 66 "UMask": "0x20", 67 "EventName": "L2_RQSTS.CODE_RD_MISS", 68 "SampleAfterValue": "200003", 69 "BriefDescription": "L2 cache misses when fetching instructions", 70 "CounterHTOff": "0,1,2,3,4,5,6,7" 71 }, 72 { 73 "PublicDescription": "Counts all L2 code requests.", 74 "EventCode": "0x24", 75 "Counter": "0,1,2,3", 76 "UMask": "0x30", 77 "EventName": "L2_RQSTS.ALL_CODE_RD", 78 "SampleAfterValue": "200003", 79 "BriefDescription": "L2 code requests", 80 "CounterHTOff": "0,1,2,3,4,5,6,7" 81 }, 82 { 83 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 84 "EventCode": "0x24", 85 "Counter": "0,1,2,3", 86 "UMask": "0x40", 87 "EventName": "L2_RQSTS.PF_HIT", 88 "SampleAfterValue": "200003", 89 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", 90 "CounterHTOff": "0,1,2,3,4,5,6,7" 91 }, 92 { 93 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 94 "EventCode": "0x24", 95 "Counter": "0,1,2,3", 96 "UMask": "0x80", 97 "EventName": "L2_RQSTS.PF_MISS", 98 "SampleAfterValue": "200003", 99 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", 100 "CounterHTOff": "0,1,2,3,4,5,6,7" 101 }, 102 { 103 "PublicDescription": "Counts all L2 HW prefetcher requests.", 104 "EventCode": "0x24", 105 "Counter": "0,1,2,3", 106 "UMask": "0xc0", 107 "EventName": "L2_RQSTS.ALL_PF", 108 "SampleAfterValue": "200003", 109 "BriefDescription": "Requests from L2 hardware prefetchers", 110 "CounterHTOff": "0,1,2,3,4,5,6,7" 111 }, 112 { 113 "PublicDescription": "RFOs that miss cache lines.", 114 "EventCode": "0x27", 115 "Counter": "0,1,2,3", 116 "UMask": "0x1", 117 "EventName": "L2_STORE_LOCK_RQSTS.MISS", 118 "SampleAfterValue": "200003", 119 "BriefDescription": "RFOs that miss cache lines", 120 "CounterHTOff": "0,1,2,3,4,5,6,7" 121 }, 122 { 123 "PublicDescription": "RFOs that hit cache lines in M state.", 124 "EventCode": "0x27", 125 "Counter": "0,1,2,3", 126 "UMask": "0x8", 127 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", 128 "SampleAfterValue": "200003", 129 "BriefDescription": "RFOs that hit cache lines in M state", 130 "CounterHTOff": "0,1,2,3,4,5,6,7" 131 }, 132 { 133 "PublicDescription": "RFOs that access cache lines in any state.", 134 "EventCode": "0x27", 135 "Counter": "0,1,2,3", 136 "UMask": "0xf", 137 "EventName": "L2_STORE_LOCK_RQSTS.ALL", 138 "SampleAfterValue": "200003", 139 "BriefDescription": "RFOs that access cache lines in any state", 140 "CounterHTOff": "0,1,2,3,4,5,6,7" 141 }, 142 { 143 "PublicDescription": "Not rejected writebacks that missed LLC.", 144 "EventCode": "0x28", 145 "Counter": "0,1,2,3", 146 "UMask": "0x1", 147 "EventName": "L2_L1D_WB_RQSTS.MISS", 148 "SampleAfterValue": "200003", 149 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", 150 "CounterHTOff": "0,1,2,3,4,5,6,7" 151 }, 152 { 153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", 154 "EventCode": "0x28", 155 "Counter": "0,1,2,3", 156 "UMask": "0x4", 157 "EventName": "L2_L1D_WB_RQSTS.HIT_E", 158 "SampleAfterValue": "200003", 159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", 160 "CounterHTOff": "0,1,2,3,4,5,6,7" 161 }, 162 { 163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", 164 "EventCode": "0x28", 165 "Counter": "0,1,2,3", 166 "UMask": "0x8", 167 "EventName": "L2_L1D_WB_RQSTS.HIT_M", 168 "SampleAfterValue": "200003", 169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", 170 "CounterHTOff": "0,1,2,3,4,5,6,7" 171 }, 172 { 173 "EventCode": "0x28", 174 "Counter": "0,1,2,3", 175 "UMask": "0xf", 176 "EventName": "L2_L1D_WB_RQSTS.ALL", 177 "SampleAfterValue": "200003", 178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", 179 "CounterHTOff": "0,1,2,3,4,5,6,7" 180 }, 181 { 182 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 183 "EventCode": "0x2E", 184 "Counter": "0,1,2,3", 185 "UMask": "0x41", 186 "EventName": "LONGEST_LAT_CACHE.MISS", 187 "SampleAfterValue": "100003", 188 "BriefDescription": "Core-originated cacheable demand requests missed LLC", 189 "CounterHTOff": "0,1,2,3,4,5,6,7" 190 }, 191 { 192 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 193 "EventCode": "0x2E", 194 "Counter": "0,1,2,3", 195 "UMask": "0x4f", 196 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 197 "SampleAfterValue": "100003", 198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", 199 "CounterHTOff": "0,1,2,3,4,5,6,7" 200 }, 201 { 202 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 203 "EventCode": "0x48", 204 "Counter": "2", 205 "UMask": "0x1", 206 "EventName": "L1D_PEND_MISS.PENDING", 207 "SampleAfterValue": "2000003", 208 "BriefDescription": "L1D miss oustandings duration in cycles", 209 "CounterHTOff": "2" 210 }, 211 { 212 "EventCode": "0x48", 213 "Counter": "2", 214 "UMask": "0x1", 215 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 216 "SampleAfterValue": "2000003", 217 "BriefDescription": "Cycles with L1D load Misses outstanding.", 218 "CounterMask": "1", 219 "CounterHTOff": "2" 220 }, 221 { 222 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 223 "EventCode": "0x48", 224 "Counter": "2", 225 "UMask": "0x1", 226 "AnyThread": "1", 227 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 228 "SampleAfterValue": "2000003", 229 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", 230 "CounterMask": "1", 231 "CounterHTOff": "2" 232 }, 233 { 234 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 235 "EventCode": "0x48", 236 "Counter": "0,1,2,3", 237 "UMask": "0x2", 238 "EventName": "L1D_PEND_MISS.FB_FULL", 239 "SampleAfterValue": "2000003", 240 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", 241 "CounterMask": "1", 242 "CounterHTOff": "0,1,2,3,4,5,6,7" 243 }, 244 { 245 "PublicDescription": "Counts the number of lines brought into the L1 data cache.", 246 "EventCode": "0x51", 247 "Counter": "0,1,2,3", 248 "UMask": "0x1", 249 "EventName": "L1D.REPLACEMENT", 250 "SampleAfterValue": "2000003", 251 "BriefDescription": "L1D data line replacements", 252 "CounterHTOff": "0,1,2,3,4,5,6,7" 253 }, 254 { 255 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 256 "EventCode": "0x60", 257 "Counter": "0,1,2,3", 258 "UMask": "0x1", 259 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 260 "SampleAfterValue": "2000003", 261 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 262 "CounterHTOff": "0,1,2,3,4,5,6,7" 263 }, 264 { 265 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 266 "EventCode": "0x60", 267 "Counter": "0,1,2,3", 268 "UMask": "0x1", 269 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 270 "SampleAfterValue": "2000003", 271 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", 272 "CounterMask": "1", 273 "CounterHTOff": "0,1,2,3,4,5,6,7" 274 }, 275 { 276 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 277 "EventCode": "0x60", 278 "Counter": "0,1,2,3", 279 "UMask": "0x1", 280 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 281 "SampleAfterValue": "2000003", 282 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", 283 "CounterMask": "6", 284 "CounterHTOff": "0,1,2,3,4,5,6,7" 285 }, 286 { 287 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 288 "EventCode": "0x60", 289 "Counter": "0,1,2,3", 290 "UMask": "0x2", 291 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 292 "SampleAfterValue": "2000003", 293 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 294 "CounterHTOff": "0,1,2,3,4,5,6,7" 295 }, 296 { 297 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 298 "EventCode": "0x60", 299 "Counter": "0,1,2,3", 300 "UMask": "0x2", 301 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", 302 "SampleAfterValue": "2000003", 303 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 304 "CounterMask": "1", 305 "CounterHTOff": "0,1,2,3,4,5,6,7" 306 }, 307 { 308 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 309 "EventCode": "0x60", 310 "Counter": "0,1,2,3", 311 "UMask": "0x4", 312 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 313 "SampleAfterValue": "2000003", 314 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 315 "CounterHTOff": "0,1,2,3,4,5,6,7" 316 }, 317 { 318 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 319 "EventCode": "0x60", 320 "Counter": "0,1,2,3", 321 "UMask": "0x4", 322 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 323 "SampleAfterValue": "2000003", 324 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 325 "CounterMask": "1", 326 "CounterHTOff": "0,1,2,3,4,5,6,7" 327 }, 328 { 329 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 330 "EventCode": "0x60", 331 "Counter": "0,1,2,3", 332 "UMask": "0x8", 333 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 334 "SampleAfterValue": "2000003", 335 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 336 "CounterHTOff": "0,1,2,3,4,5,6,7" 337 }, 338 { 339 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 340 "EventCode": "0x60", 341 "Counter": "0,1,2,3", 342 "UMask": "0x8", 343 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 344 "SampleAfterValue": "2000003", 345 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", 346 "CounterMask": "1", 347 "CounterHTOff": "0,1,2,3,4,5,6,7" 348 }, 349 { 350 "PublicDescription": "Cycles in which the L1D is locked.", 351 "EventCode": "0x63", 352 "Counter": "0,1,2,3", 353 "UMask": "0x2", 354 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 355 "SampleAfterValue": "2000003", 356 "BriefDescription": "Cycles when L1D is locked", 357 "CounterHTOff": "0,1,2,3,4,5,6,7" 358 }, 359 { 360 "PublicDescription": "Demand data read requests sent to uncore.", 361 "EventCode": "0xB0", 362 "Counter": "0,1,2,3", 363 "UMask": "0x1", 364 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 365 "SampleAfterValue": "100003", 366 "BriefDescription": "Demand Data Read requests sent to uncore", 367 "CounterHTOff": "0,1,2,3,4,5,6,7" 368 }, 369 { 370 "PublicDescription": "Demand code read requests sent to uncore.", 371 "EventCode": "0xB0", 372 "Counter": "0,1,2,3", 373 "UMask": "0x2", 374 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 375 "SampleAfterValue": "100003", 376 "BriefDescription": "Cacheable and noncachaeble code read requests", 377 "CounterHTOff": "0,1,2,3,4,5,6,7" 378 }, 379 { 380 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 381 "EventCode": "0xB0", 382 "Counter": "0,1,2,3", 383 "UMask": "0x4", 384 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 385 "SampleAfterValue": "100003", 386 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 387 "CounterHTOff": "0,1,2,3,4,5,6,7" 388 }, 389 { 390 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 391 "EventCode": "0xB0", 392 "Counter": "0,1,2,3", 393 "UMask": "0x8", 394 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 395 "SampleAfterValue": "100003", 396 "BriefDescription": "Demand and prefetch data reads", 397 "CounterHTOff": "0,1,2,3,4,5,6,7" 398 }, 399 { 400 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", 401 "EventCode": "0xB2", 402 "Counter": "0,1,2,3", 403 "UMask": "0x1", 404 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 405 "SampleAfterValue": "2000003", 406 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", 407 "CounterHTOff": "0,1,2,3,4,5,6,7" 408 }, 409 { 410 "PEBS": "1", 411 "EventCode": "0xD0", 412 "Counter": "0,1,2,3", 413 "UMask": "0x11", 414 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 415 "SampleAfterValue": "100003", 416 "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", 417 "CounterHTOff": "0,1,2,3" 418 }, 419 { 420 "PEBS": "1", 421 "EventCode": "0xD0", 422 "Counter": "0,1,2,3", 423 "UMask": "0x12", 424 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 425 "SampleAfterValue": "100003", 426 "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", 427 "CounterHTOff": "0,1,2,3" 428 }, 429 { 430 "PEBS": "1", 431 "EventCode": "0xD0", 432 "Counter": "0,1,2,3", 433 "UMask": "0x21", 434 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 435 "SampleAfterValue": "100007", 436 "BriefDescription": "Retired load uops with locked access. (Precise Event)", 437 "CounterHTOff": "0,1,2,3" 438 }, 439 { 440 "PEBS": "1", 441 "EventCode": "0xD0", 442 "Counter": "0,1,2,3", 443 "UMask": "0x41", 444 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 445 "SampleAfterValue": "100003", 446 "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", 447 "CounterHTOff": "0,1,2,3" 448 }, 449 { 450 "PEBS": "1", 451 "EventCode": "0xD0", 452 "Counter": "0,1,2,3", 453 "UMask": "0x42", 454 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 455 "SampleAfterValue": "100003", 456 "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", 457 "CounterHTOff": "0,1,2,3" 458 }, 459 { 460 "PEBS": "1", 461 "EventCode": "0xD0", 462 "Counter": "0,1,2,3", 463 "UMask": "0x81", 464 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 465 "SampleAfterValue": "2000003", 466 "BriefDescription": "All retired load uops. (Precise Event)", 467 "CounterHTOff": "0,1,2,3" 468 }, 469 { 470 "PEBS": "1", 471 "EventCode": "0xD0", 472 "Counter": "0,1,2,3", 473 "UMask": "0x82", 474 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 475 "SampleAfterValue": "2000003", 476 "BriefDescription": "All retired store uops. (Precise Event)", 477 "CounterHTOff": "0,1,2,3" 478 }, 479 { 480 "PEBS": "1", 481 "EventCode": "0xD1", 482 "Counter": "0,1,2,3", 483 "UMask": "0x1", 484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 485 "SampleAfterValue": "2000003", 486 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 487 "CounterHTOff": "0,1,2,3" 488 }, 489 { 490 "PEBS": "1", 491 "EventCode": "0xD1", 492 "Counter": "0,1,2,3", 493 "UMask": "0x2", 494 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 495 "SampleAfterValue": "100003", 496 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 497 "CounterHTOff": "0,1,2,3" 498 }, 499 { 500 "PEBS": "1", 501 "EventCode": "0xD1", 502 "Counter": "0,1,2,3", 503 "UMask": "0x4", 504 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", 505 "SampleAfterValue": "50021", 506 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", 507 "CounterHTOff": "0,1,2,3" 508 }, 509 { 510 "PEBS": "1", 511 "EventCode": "0xD1", 512 "Counter": "0,1,2,3", 513 "UMask": "0x8", 514 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 515 "SampleAfterValue": "100003", 516 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", 517 "CounterHTOff": "0,1,2,3" 518 }, 519 { 520 "PEBS": "1", 521 "EventCode": "0xD1", 522 "Counter": "0,1,2,3", 523 "UMask": "0x10", 524 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 525 "SampleAfterValue": "50021", 526 "BriefDescription": "Retired load uops with L2 cache misses as data sources.", 527 "CounterHTOff": "0,1,2,3" 528 }, 529 { 530 "PEBS": "1", 531 "EventCode": "0xD1", 532 "Counter": "0,1,2,3", 533 "UMask": "0x20", 534 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", 535 "SampleAfterValue": "100007", 536 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 537 "CounterHTOff": "0,1,2,3" 538 }, 539 { 540 "PEBS": "1", 541 "EventCode": "0xD1", 542 "Counter": "0,1,2,3", 543 "UMask": "0x40", 544 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 545 "SampleAfterValue": "100003", 546 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 547 "CounterHTOff": "0,1,2,3" 548 }, 549 { 550 "PEBS": "1", 551 "EventCode": "0xD2", 552 "Counter": "0,1,2,3", 553 "UMask": "0x1", 554 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", 555 "SampleAfterValue": "20011", 556 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", 557 "CounterHTOff": "0,1,2,3" 558 }, 559 { 560 "PEBS": "1", 561 "EventCode": "0xD2", 562 "Counter": "0,1,2,3", 563 "UMask": "0x2", 564 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", 565 "SampleAfterValue": "20011", 566 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", 567 "CounterHTOff": "0,1,2,3" 568 }, 569 { 570 "PEBS": "1", 571 "EventCode": "0xD2", 572 "Counter": "0,1,2,3", 573 "UMask": "0x4", 574 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", 575 "SampleAfterValue": "20011", 576 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", 577 "CounterHTOff": "0,1,2,3" 578 }, 579 { 580 "PEBS": "1", 581 "EventCode": "0xD2", 582 "Counter": "0,1,2,3", 583 "UMask": "0x8", 584 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", 585 "SampleAfterValue": "100003", 586 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", 587 "CounterHTOff": "0,1,2,3" 588 }, 589 { 590 "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", 591 "EventCode": "0xD3", 592 "Counter": "0,1,2,3", 593 "UMask": "0x1", 594 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", 595 "SampleAfterValue": "100007", 596 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", 597 "CounterHTOff": "0,1,2,3" 598 }, 599 { 600 "PublicDescription": "Demand Data Read requests that access L2 cache.", 601 "EventCode": "0xF0", 602 "Counter": "0,1,2,3", 603 "UMask": "0x1", 604 "EventName": "L2_TRANS.DEMAND_DATA_RD", 605 "SampleAfterValue": "200003", 606 "BriefDescription": "Demand Data Read requests that access L2 cache", 607 "CounterHTOff": "0,1,2,3,4,5,6,7" 608 }, 609 { 610 "PublicDescription": "RFO requests that access L2 cache.", 611 "EventCode": "0xF0", 612 "Counter": "0,1,2,3", 613 "UMask": "0x2", 614 "EventName": "L2_TRANS.RFO", 615 "SampleAfterValue": "200003", 616 "BriefDescription": "RFO requests that access L2 cache", 617 "CounterHTOff": "0,1,2,3,4,5,6,7" 618 }, 619 { 620 "PublicDescription": "L2 cache accesses when fetching instructions.", 621 "EventCode": "0xF0", 622 "Counter": "0,1,2,3", 623 "UMask": "0x4", 624 "EventName": "L2_TRANS.CODE_RD", 625 "SampleAfterValue": "200003", 626 "BriefDescription": "L2 cache accesses when fetching instructions", 627 "CounterHTOff": "0,1,2,3,4,5,6,7" 628 }, 629 { 630 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", 631 "EventCode": "0xF0", 632 "Counter": "0,1,2,3", 633 "UMask": "0x8", 634 "EventName": "L2_TRANS.ALL_PF", 635 "SampleAfterValue": "200003", 636 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", 637 "CounterHTOff": "0,1,2,3,4,5,6,7" 638 }, 639 { 640 "PublicDescription": "L1D writebacks that access L2 cache.", 641 "EventCode": "0xF0", 642 "Counter": "0,1,2,3", 643 "UMask": "0x10", 644 "EventName": "L2_TRANS.L1D_WB", 645 "SampleAfterValue": "200003", 646 "BriefDescription": "L1D writebacks that access L2 cache", 647 "CounterHTOff": "0,1,2,3,4,5,6,7" 648 }, 649 { 650 "PublicDescription": "L2 fill requests that access L2 cache.", 651 "EventCode": "0xF0", 652 "Counter": "0,1,2,3", 653 "UMask": "0x20", 654 "EventName": "L2_TRANS.L2_FILL", 655 "SampleAfterValue": "200003", 656 "BriefDescription": "L2 fill requests that access L2 cache", 657 "CounterHTOff": "0,1,2,3,4,5,6,7" 658 }, 659 { 660 "PublicDescription": "L2 writebacks that access L2 cache.", 661 "EventCode": "0xF0", 662 "Counter": "0,1,2,3", 663 "UMask": "0x40", 664 "EventName": "L2_TRANS.L2_WB", 665 "SampleAfterValue": "200003", 666 "BriefDescription": "L2 writebacks that access L2 cache", 667 "CounterHTOff": "0,1,2,3,4,5,6,7" 668 }, 669 { 670 "PublicDescription": "Transactions accessing L2 pipe.", 671 "EventCode": "0xF0", 672 "Counter": "0,1,2,3", 673 "UMask": "0x80", 674 "EventName": "L2_TRANS.ALL_REQUESTS", 675 "SampleAfterValue": "200003", 676 "BriefDescription": "Transactions accessing L2 pipe", 677 "CounterHTOff": "0,1,2,3,4,5,6,7" 678 }, 679 { 680 "PublicDescription": "L2 cache lines in I state filling L2.", 681 "EventCode": "0xF1", 682 "Counter": "0,1,2,3", 683 "UMask": "0x1", 684 "EventName": "L2_LINES_IN.I", 685 "SampleAfterValue": "100003", 686 "BriefDescription": "L2 cache lines in I state filling L2", 687 "CounterHTOff": "0,1,2,3,4,5,6,7" 688 }, 689 { 690 "PublicDescription": "L2 cache lines in S state filling L2.", 691 "EventCode": "0xF1", 692 "Counter": "0,1,2,3", 693 "UMask": "0x2", 694 "EventName": "L2_LINES_IN.S", 695 "SampleAfterValue": "100003", 696 "BriefDescription": "L2 cache lines in S state filling L2", 697 "CounterHTOff": "0,1,2,3,4,5,6,7" 698 }, 699 { 700 "PublicDescription": "L2 cache lines in E state filling L2.", 701 "EventCode": "0xF1", 702 "Counter": "0,1,2,3", 703 "UMask": "0x4", 704 "EventName": "L2_LINES_IN.E", 705 "SampleAfterValue": "100003", 706 "BriefDescription": "L2 cache lines in E state filling L2", 707 "CounterHTOff": "0,1,2,3,4,5,6,7" 708 }, 709 { 710 "PublicDescription": "L2 cache lines filling L2.", 711 "EventCode": "0xF1", 712 "Counter": "0,1,2,3", 713 "UMask": "0x7", 714 "EventName": "L2_LINES_IN.ALL", 715 "SampleAfterValue": "100003", 716 "BriefDescription": "L2 cache lines filling L2", 717 "CounterHTOff": "0,1,2,3,4,5,6,7" 718 }, 719 { 720 "PublicDescription": "Clean L2 cache lines evicted by demand.", 721 "EventCode": "0xF2", 722 "Counter": "0,1,2,3", 723 "UMask": "0x1", 724 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 725 "SampleAfterValue": "100003", 726 "BriefDescription": "Clean L2 cache lines evicted by demand", 727 "CounterHTOff": "0,1,2,3,4,5,6,7" 728 }, 729 { 730 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 731 "EventCode": "0xF2", 732 "Counter": "0,1,2,3", 733 "UMask": "0x2", 734 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 735 "SampleAfterValue": "100003", 736 "BriefDescription": "Dirty L2 cache lines evicted by demand", 737 "CounterHTOff": "0,1,2,3,4,5,6,7" 738 }, 739 { 740 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", 741 "EventCode": "0xF2", 742 "Counter": "0,1,2,3", 743 "UMask": "0x4", 744 "EventName": "L2_LINES_OUT.PF_CLEAN", 745 "SampleAfterValue": "100003", 746 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", 747 "CounterHTOff": "0,1,2,3,4,5,6,7" 748 }, 749 { 750 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", 751 "EventCode": "0xF2", 752 "Counter": "0,1,2,3", 753 "UMask": "0x8", 754 "EventName": "L2_LINES_OUT.PF_DIRTY", 755 "SampleAfterValue": "100003", 756 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", 757 "CounterHTOff": "0,1,2,3,4,5,6,7" 758 }, 759 { 760 "PublicDescription": "Dirty L2 cache lines filling the L2.", 761 "EventCode": "0xF2", 762 "Counter": "0,1,2,3", 763 "UMask": "0xa", 764 "EventName": "L2_LINES_OUT.DIRTY_ALL", 765 "SampleAfterValue": "100003", 766 "BriefDescription": "Dirty L2 cache lines filling the L2", 767 "CounterHTOff": "0,1,2,3,4,5,6,7" 768 }, 769 { 770 "EventCode": "0xF4", 771 "Counter": "0,1,2,3", 772 "UMask": "0x10", 773 "EventName": "SQ_MISC.SPLIT_LOCK", 774 "SampleAfterValue": "100003", 775 "BriefDescription": "Split locks in SQ", 776 "CounterHTOff": "0,1,2,3,4,5,6,7" 777 }, 778 { 779 "EventCode": "0xB7, 0xBB", 780 "MSRValue": "0x3f803c0244", 781 "Counter": "0,1,2,3", 782 "UMask": "0x1", 783 "Offcore": "1", 784 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", 785 "MSRIndex": "0x1a6,0x1a7", 786 "SampleAfterValue": "100003", 787 "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", 788 "CounterHTOff": "0,1,2,3" 789 }, 790 { 791 "EventCode": "0xB7, 0xBB", 792 "MSRValue": "0x1003c0244", 793 "Counter": "0,1,2,3", 794 "UMask": "0x1", 795 "Offcore": "1", 796 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 797 "MSRIndex": "0x1a6,0x1a7", 798 "SampleAfterValue": "100003", 799 "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 800 "CounterHTOff": "0,1,2,3" 801 }, 802 { 803 "EventCode": "0xB7, 0xBB", 804 "MSRValue": "0x3f803c0091", 805 "Counter": "0,1,2,3", 806 "UMask": "0x1", 807 "Offcore": "1", 808 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", 809 "MSRIndex": "0x1a6,0x1a7", 810 "SampleAfterValue": "100003", 811 "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", 812 "CounterHTOff": "0,1,2,3" 813 }, 814 { 815 "EventCode": "0xB7, 0xBB", 816 "MSRValue": "0x4003c0091", 817 "Counter": "0,1,2,3", 818 "UMask": "0x1", 819 "Offcore": "1", 820 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 821 "MSRIndex": "0x1a6,0x1a7", 822 "SampleAfterValue": "100003", 823 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 824 "CounterHTOff": "0,1,2,3" 825 }, 826 { 827 "EventCode": "0xB7, 0xBB", 828 "MSRValue": "0x10003c0091", 829 "Counter": "0,1,2,3", 830 "UMask": "0x1", 831 "Offcore": "1", 832 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 833 "MSRIndex": "0x1a6,0x1a7", 834 "SampleAfterValue": "100003", 835 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 836 "CounterHTOff": "0,1,2,3" 837 }, 838 { 839 "EventCode": "0xB7, 0xBB", 840 "MSRValue": "0x1003c0091", 841 "Counter": "0,1,2,3", 842 "UMask": "0x1", 843 "Offcore": "1", 844 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 845 "MSRIndex": "0x1a6,0x1a7", 846 "SampleAfterValue": "100003", 847 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 848 "CounterHTOff": "0,1,2,3" 849 }, 850 { 851 "EventCode": "0xB7, 0xBB", 852 "MSRValue": "0x3f803c0122", 853 "Counter": "0,1,2,3", 854 "UMask": "0x1", 855 "Offcore": "1", 856 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", 857 "MSRIndex": "0x1a6,0x1a7", 858 "SampleAfterValue": "100003", 859 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", 860 "CounterHTOff": "0,1,2,3" 861 }, 862 { 863 "EventCode": "0xB7, 0xBB", 864 "MSRValue": "0x1003c0122", 865 "Counter": "0,1,2,3", 866 "UMask": "0x1", 867 "Offcore": "1", 868 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", 869 "MSRIndex": "0x1a6,0x1a7", 870 "SampleAfterValue": "100003", 871 "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 872 "CounterHTOff": "0,1,2,3" 873 }, 874 { 875 "EventCode": "0xB7, 0xBB", 876 "MSRValue": "0x10008", 877 "Counter": "0,1,2,3", 878 "UMask": "0x1", 879 "Offcore": "1", 880 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", 881 "MSRIndex": "0x1a6,0x1a7", 882 "SampleAfterValue": "100003", 883 "BriefDescription": "Counts all writebacks from the core to the LLC", 884 "CounterHTOff": "0,1,2,3" 885 }, 886 { 887 "EventCode": "0xB7, 0xBB", 888 "MSRValue": "0x3f803c0004", 889 "Counter": "0,1,2,3", 890 "UMask": "0x1", 891 "Offcore": "1", 892 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", 893 "MSRIndex": "0x1a6,0x1a7", 894 "SampleAfterValue": "100003", 895 "BriefDescription": "Counts all demand code reads that hit in the LLC", 896 "CounterHTOff": "0,1,2,3" 897 }, 898 { 899 "EventCode": "0xB7, 0xBB", 900 "MSRValue": "0x1003c0004", 901 "Counter": "0,1,2,3", 902 "UMask": "0x1", 903 "Offcore": "1", 904 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", 905 "MSRIndex": "0x1a6,0x1a7", 906 "SampleAfterValue": "100003", 907 "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 908 "CounterHTOff": "0,1,2,3" 909 }, 910 { 911 "EventCode": "0xB7, 0xBB", 912 "MSRValue": "0x3f803c0001", 913 "Counter": "0,1,2,3", 914 "UMask": "0x1", 915 "Offcore": "1", 916 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", 917 "MSRIndex": "0x1a6,0x1a7", 918 "SampleAfterValue": "100003", 919 "BriefDescription": "Counts all demand data reads that hit in the LLC", 920 "CounterHTOff": "0,1,2,3" 921 }, 922 { 923 "EventCode": "0xB7, 0xBB", 924 "MSRValue": "0x4003c0001", 925 "Counter": "0,1,2,3", 926 "UMask": "0x1", 927 "Offcore": "1", 928 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", 929 "MSRIndex": "0x1a6,0x1a7", 930 "SampleAfterValue": "100003", 931 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 932 "CounterHTOff": "0,1,2,3" 933 }, 934 { 935 "EventCode": "0xB7, 0xBB", 936 "MSRValue": "0x10003c0001", 937 "Counter": "0,1,2,3", 938 "UMask": "0x1", 939 "Offcore": "1", 940 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", 941 "MSRIndex": "0x1a6,0x1a7", 942 "SampleAfterValue": "100003", 943 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 944 "CounterHTOff": "0,1,2,3" 945 }, 946 { 947 "EventCode": "0xB7, 0xBB", 948 "MSRValue": "0x1003c0001", 949 "Counter": "0,1,2,3", 950 "UMask": "0x1", 951 "Offcore": "1", 952 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", 953 "MSRIndex": "0x1a6,0x1a7", 954 "SampleAfterValue": "100003", 955 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 956 "CounterHTOff": "0,1,2,3" 957 }, 958 { 959 "EventCode": "0xB7, 0xBB", 960 "MSRValue": "0x3f803c0002", 961 "Counter": "0,1,2,3", 962 "UMask": "0x1", 963 "Offcore": "1", 964 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", 965 "MSRIndex": "0x1a6,0x1a7", 966 "SampleAfterValue": "100003", 967 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", 968 "CounterHTOff": "0,1,2,3" 969 }, 970 { 971 "EventCode": "0xB7, 0xBB", 972 "MSRValue": "0x10003c0002", 973 "Counter": "0,1,2,3", 974 "UMask": "0x1", 975 "Offcore": "1", 976 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", 977 "MSRIndex": "0x1a6,0x1a7", 978 "SampleAfterValue": "100003", 979 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 980 "CounterHTOff": "0,1,2,3" 981 }, 982 { 983 "EventCode": "0xB7, 0xBB", 984 "MSRValue": "0x1003c0002", 985 "Counter": "0,1,2,3", 986 "UMask": "0x1", 987 "Offcore": "1", 988 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", 989 "MSRIndex": "0x1a6,0x1a7", 990 "SampleAfterValue": "100003", 991 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", 992 "CounterHTOff": "0,1,2,3" 993 }, 994 { 995 "EventCode": "0xB7, 0xBB", 996 "MSRValue": "0x18000", 997 "Counter": "0,1,2,3", 998 "UMask": "0x1", 999 "Offcore": "1", 1000 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", 1001 "MSRIndex": "0x1a6,0x1a7", 1002 "SampleAfterValue": "100003", 1003 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", 1004 "CounterHTOff": "0,1,2,3" 1005 }, 1006 { 1007 "EventCode": "0xB7, 0xBB", 1008 "MSRValue": "0x10400", 1009 "Counter": "0,1,2,3", 1010 "UMask": "0x1", 1011 "Offcore": "1", 1012 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", 1013 "MSRIndex": "0x1a6,0x1a7", 1014 "SampleAfterValue": "100003", 1015 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", 1016 "CounterHTOff": "0,1,2,3" 1017 }, 1018 { 1019 "EventCode": "0xB7, 0xBB", 1020 "MSRValue": "0x10800", 1021 "Counter": "0,1,2,3", 1022 "UMask": "0x1", 1023 "Offcore": "1", 1024 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", 1025 "MSRIndex": "0x1a6,0x1a7", 1026 "SampleAfterValue": "100003", 1027 "BriefDescription": "Counts non-temporal stores", 1028 "CounterHTOff": "0,1,2,3" 1029 }, 1030 { 1031 "EventCode": "0xB7, 0xBB", 1032 "MSRValue": "0x00010001", 1033 "Counter": "0,1,2,3", 1034 "UMask": "0x1", 1035 "Offcore": "1", 1036 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", 1037 "MSRIndex": "0x1a6,0x1a7", 1038 "SampleAfterValue": "100003", 1039 "BriefDescription": "Counts all demand data reads", 1040 "CounterHTOff": "0,1,2,3" 1041 }, 1042 { 1043 "EventCode": "0xB7, 0xBB", 1044 "MSRValue": "0x00010002", 1045 "Counter": "0,1,2,3", 1046 "UMask": "0x1", 1047 "Offcore": "1", 1048 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", 1049 "MSRIndex": "0x1a6,0x1a7", 1050 "SampleAfterValue": "100003", 1051 "BriefDescription": "Counts all demand rfo's", 1052 "CounterHTOff": "0,1,2,3" 1053 }, 1054 { 1055 "EventCode": "0xB7, 0xBB", 1056 "MSRValue": "0x00010004", 1057 "Counter": "0,1,2,3", 1058 "UMask": "0x1", 1059 "Offcore": "1", 1060 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", 1061 "MSRIndex": "0x1a6,0x1a7", 1062 "SampleAfterValue": "100003", 1063 "BriefDescription": "Counts all demand code reads", 1064 "CounterHTOff": "0,1,2,3" 1065 }, 1066 { 1067 "EventCode": "0xB7, 0xBB", 1068 "MSRValue": "0x000105B3", 1069 "Counter": "0,1,2,3", 1070 "UMask": "0x1", 1071 "Offcore": "1", 1072 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", 1073 "MSRIndex": "0x1a6,0x1a7", 1074 "SampleAfterValue": "100003", 1075 "BriefDescription": "Counts all demand & prefetch data reads", 1076 "CounterHTOff": "0,1,2,3" 1077 }, 1078 { 1079 "EventCode": "0xB7, 0xBB", 1080 "MSRValue": "0x00010122", 1081 "Counter": "0,1,2,3", 1082 "UMask": "0x1", 1083 "Offcore": "1", 1084 "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", 1085 "MSRIndex": "0x1a6,0x1a7", 1086 "SampleAfterValue": "100003", 1087 "BriefDescription": "Counts all demand & prefetch prefetch RFOs", 1088 "CounterHTOff": "0,1,2,3" 1089 }, 1090 { 1091 "EventCode": "0xB7, 0xBB", 1092 "MSRValue": "0x000107F7", 1093 "Counter": "0,1,2,3", 1094 "UMask": "0x1", 1095 "Offcore": "1", 1096 "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", 1097 "MSRIndex": "0x1a6,0x1a7", 1098 "SampleAfterValue": "100003", 1099 "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", 1100 "CounterHTOff": "0,1,2,3" 1101 } 1102]