1[ 2 { 3 "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 4 "CollectPEBSRecord": "2", 5 "Counter": "0,1,2,3,4,5,6,7", 6 "EventCode": "0xc1", 7 "EventName": "ASSISTS.ANY", 8 "PEBScounters": "0,1,2,3,4,5,6,7", 9 "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", 10 "SampleAfterValue": "100003", 11 "Speculative": "1", 12 "UMask": "0x7" 13 }, 14 { 15 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 16 "CollectPEBSRecord": "2", 17 "Counter": "0,1,2,3", 18 "EventCode": "0x28", 19 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 20 "PEBScounters": "0,1,2,3", 21 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 22 "SampleAfterValue": "200003", 23 "Speculative": "1", 24 "UMask": "0x7" 25 }, 26 { 27 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 28 "CollectPEBSRecord": "2", 29 "Counter": "0,1,2,3", 30 "EventCode": "0x28", 31 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 32 "PEBScounters": "0,1,2,3", 33 "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 34 "SampleAfterValue": "200003", 35 "Speculative": "1", 36 "UMask": "0x18" 37 }, 38 { 39 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 40 "CollectPEBSRecord": "2", 41 "Counter": "0,1,2,3", 42 "EventCode": "0x28", 43 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 44 "PEBScounters": "0,1,2,3", 45 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 46 "SampleAfterValue": "200003", 47 "Speculative": "1", 48 "UMask": "0x20" 49 }, 50 { 51 "BriefDescription": "Hit snoop reply with data, line invalidated.", 52 "CollectPEBSRecord": "2", 53 "Counter": "0,1,2,3", 54 "EventCode": "0xef", 55 "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE", 56 "PEBScounters": "0,1,2,3", 57 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.", 58 "SampleAfterValue": "1000003", 59 "Speculative": "1", 60 "UMask": "0x20" 61 }, 62 { 63 "BriefDescription": "HitM snoop reply with data, line invalidated.", 64 "CollectPEBSRecord": "2", 65 "Counter": "0,1,2,3", 66 "EventCode": "0xef", 67 "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M", 68 "PEBScounters": "0,1,2,3", 69 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.", 70 "SampleAfterValue": "1000003", 71 "Speculative": "1", 72 "UMask": "0x10" 73 }, 74 { 75 "BriefDescription": "Hit snoop reply without sending the data, line invalidated.", 76 "CollectPEBSRecord": "2", 77 "Counter": "0,1,2,3", 78 "EventCode": "0xef", 79 "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE", 80 "PEBScounters": "0,1,2,3", 81 "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.", 82 "SampleAfterValue": "1000003", 83 "Speculative": "1", 84 "UMask": "0x2" 85 }, 86 { 87 "BriefDescription": "Line not found snoop reply", 88 "CollectPEBSRecord": "2", 89 "Counter": "0,1,2,3", 90 "EventCode": "0xef", 91 "EventName": "CORE_SNOOP_RESPONSE.MISS", 92 "PEBScounters": "0,1,2,3", 93 "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.", 94 "SampleAfterValue": "1000003", 95 "Speculative": "1", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Hit snoop reply with data, line kept in Shared state.", 100 "CollectPEBSRecord": "2", 101 "Counter": "0,1,2,3", 102 "EventCode": "0xef", 103 "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE", 104 "PEBScounters": "0,1,2,3", 105 "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.", 106 "SampleAfterValue": "1000003", 107 "Speculative": "1", 108 "UMask": "0x40" 109 }, 110 { 111 "BriefDescription": "HitM snoop reply with data, line kept in Shared state", 112 "CollectPEBSRecord": "2", 113 "Counter": "0,1,2,3", 114 "EventCode": "0xef", 115 "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M", 116 "PEBScounters": "0,1,2,3", 117 "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.", 118 "SampleAfterValue": "1000003", 119 "Speculative": "1", 120 "UMask": "0x8" 121 }, 122 { 123 "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.", 124 "CollectPEBSRecord": "2", 125 "Counter": "0,1,2,3", 126 "EventCode": "0xef", 127 "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE", 128 "PEBScounters": "0,1,2,3", 129 "PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.", 130 "SampleAfterValue": "1000003", 131 "Speculative": "1", 132 "UMask": "0x4" 133 }, 134 { 135 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 136 "Counter": "0,1,2,3", 137 "EventCode": "0xB7, 0xBB", 138 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 139 "MSRIndex": "0x1a6,0x1a7", 140 "MSRValue": "0x10004", 141 "Offcore": "1", 142 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 143 "SampleAfterValue": "100003", 144 "UMask": "0x1" 145 }, 146 { 147 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 148 "Counter": "0,1,2,3", 149 "EventCode": "0xB7, 0xBB", 150 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 151 "MSRIndex": "0x1a6,0x1a7", 152 "MSRValue": "0x73C000004", 153 "Offcore": "1", 154 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 155 "SampleAfterValue": "100003", 156 "UMask": "0x1" 157 }, 158 { 159 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 160 "Counter": "0,1,2,3", 161 "EventCode": "0xB7, 0xBB", 162 "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 163 "MSRIndex": "0x1a6,0x1a7", 164 "MSRValue": "0x104000004", 165 "Offcore": "1", 166 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 167 "SampleAfterValue": "100003", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 172 "Counter": "0,1,2,3", 173 "EventCode": "0xB7, 0xBB", 174 "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", 175 "MSRIndex": "0x1a6,0x1a7", 176 "MSRValue": "0x708000004", 177 "Offcore": "1", 178 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 179 "SampleAfterValue": "100003", 180 "UMask": "0x1" 181 }, 182 { 183 "BriefDescription": "Counts demand data reads that have any type of response.", 184 "Counter": "0,1,2,3", 185 "EventCode": "0xB7, 0xBB", 186 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 187 "MSRIndex": "0x1a6,0x1a7", 188 "MSRValue": "0x10001", 189 "Offcore": "1", 190 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 191 "SampleAfterValue": "100003", 192 "UMask": "0x1" 193 }, 194 { 195 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 196 "Counter": "0,1,2,3", 197 "EventCode": "0xB7, 0xBB", 198 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 199 "MSRIndex": "0x1a6,0x1a7", 200 "MSRValue": "0x73C000001", 201 "Offcore": "1", 202 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 203 "SampleAfterValue": "100003", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 208 "Counter": "0,1,2,3", 209 "EventCode": "0xB7, 0xBB", 210 "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 211 "MSRIndex": "0x1a6,0x1a7", 212 "MSRValue": "0x104000001", 213 "Offcore": "1", 214 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 215 "SampleAfterValue": "100003", 216 "UMask": "0x1" 217 }, 218 { 219 "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", 220 "Counter": "0,1,2,3", 221 "EventCode": "0xB7, 0xBB", 222 "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", 223 "MSRIndex": "0x1a6,0x1a7", 224 "MSRValue": "0x100400001", 225 "Offcore": "1", 226 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 227 "SampleAfterValue": "100003", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Counts demand data reads that were supplied by PMM.", 232 "Counter": "0,1,2,3", 233 "EventCode": "0xB7, 0xBB", 234 "EventName": "OCR.DEMAND_DATA_RD.PMM", 235 "MSRIndex": "0x1a6,0x1a7", 236 "MSRValue": "0x703C00001", 237 "Offcore": "1", 238 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 239 "SampleAfterValue": "100003", 240 "UMask": "0x1" 241 }, 242 { 243 "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", 244 "Counter": "0,1,2,3", 245 "EventCode": "0xB7, 0xBB", 246 "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", 247 "MSRIndex": "0x1a6,0x1a7", 248 "MSRValue": "0x730000001", 249 "Offcore": "1", 250 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", 256 "Counter": "0,1,2,3", 257 "EventCode": "0xB7, 0xBB", 258 "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", 259 "MSRIndex": "0x1a6,0x1a7", 260 "MSRValue": "0x703000001", 261 "Offcore": "1", 262 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 263 "SampleAfterValue": "100003", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 268 "Counter": "0,1,2,3", 269 "EventCode": "0xB7, 0xBB", 270 "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x708000001", 273 "Offcore": "1", 274 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 275 "SampleAfterValue": "100003", 276 "UMask": "0x1" 277 }, 278 { 279 "BriefDescription": "Counts demand data reads that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 280 "Counter": "0,1,2,3", 281 "EventCode": "0xB7, 0xBB", 282 "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", 283 "MSRIndex": "0x1a6,0x1a7", 284 "MSRValue": "0x700800001", 285 "Offcore": "1", 286 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 287 "SampleAfterValue": "100003", 288 "UMask": "0x1" 289 }, 290 { 291 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 292 "Counter": "0,1,2,3", 293 "EventCode": "0xB7, 0xBB", 294 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 295 "MSRIndex": "0x1a6,0x1a7", 296 "MSRValue": "0x3F3FFC0002", 297 "Offcore": "1", 298 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 299 "SampleAfterValue": "100003", 300 "UMask": "0x1" 301 }, 302 { 303 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 304 "Counter": "0,1,2,3", 305 "EventCode": "0xB7, 0xBB", 306 "EventName": "OCR.DEMAND_RFO.DRAM", 307 "MSRIndex": "0x1a6,0x1a7", 308 "MSRValue": "0x73C000002", 309 "Offcore": "1", 310 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 311 "SampleAfterValue": "100003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 316 "Counter": "0,1,2,3", 317 "EventCode": "0xB7, 0xBB", 318 "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 319 "MSRIndex": "0x1a6,0x1a7", 320 "MSRValue": "0x104000002", 321 "Offcore": "1", 322 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 323 "SampleAfterValue": "100003", 324 "UMask": "0x1" 325 }, 326 { 327 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", 328 "Counter": "0,1,2,3", 329 "EventCode": "0xB7, 0xBB", 330 "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", 331 "MSRIndex": "0x1a6,0x1a7", 332 "MSRValue": "0x100400002", 333 "Offcore": "1", 334 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 335 "SampleAfterValue": "100003", 336 "UMask": "0x1" 337 }, 338 { 339 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.", 340 "Counter": "0,1,2,3", 341 "EventCode": "0xB7, 0xBB", 342 "EventName": "OCR.DEMAND_RFO.PMM", 343 "MSRIndex": "0x1a6,0x1a7", 344 "MSRValue": "0x703C00002", 345 "Offcore": "1", 346 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 347 "SampleAfterValue": "100003", 348 "UMask": "0x1" 349 }, 350 { 351 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.", 352 "Counter": "0,1,2,3", 353 "EventCode": "0xB7, 0xBB", 354 "EventName": "OCR.DEMAND_RFO.REMOTE_PMM", 355 "MSRIndex": "0x1a6,0x1a7", 356 "MSRValue": "0x703000002", 357 "Offcore": "1", 358 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 359 "SampleAfterValue": "100003", 360 "UMask": "0x1" 361 }, 362 { 363 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 364 "Counter": "0,1,2,3", 365 "EventCode": "0xB7, 0xBB", 366 "EventName": "OCR.DEMAND_RFO.SNC_DRAM", 367 "MSRIndex": "0x1a6,0x1a7", 368 "MSRValue": "0x708000002", 369 "Offcore": "1", 370 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 371 "SampleAfterValue": "100003", 372 "UMask": "0x1" 373 }, 374 { 375 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 376 "Counter": "0,1,2,3", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OCR.DEMAND_RFO.SNC_PMM", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0x700800002", 381 "Offcore": "1", 382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 383 "SampleAfterValue": "100003", 384 "UMask": "0x1" 385 }, 386 { 387 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.", 388 "Counter": "0,1,2,3", 389 "EventCode": "0xB7, 0xBB", 390 "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 391 "MSRIndex": "0x1a6,0x1a7", 392 "MSRValue": "0x73C000400", 393 "Offcore": "1", 394 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 395 "SampleAfterValue": "100003", 396 "UMask": "0x1" 397 }, 398 { 399 "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 400 "Counter": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x104000400", 405 "Offcore": "1", 406 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 407 "SampleAfterValue": "100003", 408 "UMask": "0x1" 409 }, 410 { 411 "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.", 412 "Counter": "0,1,2,3", 413 "EventCode": "0xB7, 0xBB", 414 "EventName": "OCR.HWPF_L3.ANY_RESPONSE", 415 "MSRIndex": "0x1a6,0x1a7", 416 "MSRValue": "0x12380", 417 "Offcore": "1", 418 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 419 "SampleAfterValue": "100003", 420 "UMask": "0x1" 421 }, 422 { 423 "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", 424 "Counter": "0,1,2,3", 425 "EventCode": "0xB7, 0xBB", 426 "EventName": "OCR.HWPF_L3.REMOTE", 427 "MSRIndex": "0x1a6,0x1a7", 428 "MSRValue": "0x90002380", 429 "Offcore": "1", 430 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 431 "SampleAfterValue": "100003", 432 "UMask": "0x1" 433 }, 434 { 435 "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", 436 "Counter": "0,1,2,3", 437 "EventCode": "0xB7, 0xBB", 438 "EventName": "OCR.ITOM.REMOTE", 439 "MSRIndex": "0x1a6,0x1a7", 440 "MSRValue": "0x90000002", 441 "Offcore": "1", 442 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 443 "SampleAfterValue": "100003", 444 "UMask": "0x1" 445 }, 446 { 447 "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 448 "Counter": "0,1,2,3", 449 "EventCode": "0xB7, 0xBB", 450 "EventName": "OCR.OTHER.ANY_RESPONSE", 451 "MSRIndex": "0x1a6,0x1a7", 452 "MSRValue": "0x18000", 453 "Offcore": "1", 454 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 455 "SampleAfterValue": "100003", 456 "UMask": "0x1" 457 }, 458 { 459 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", 460 "Counter": "0,1,2,3", 461 "EventCode": "0xB7, 0xBB", 462 "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", 463 "MSRIndex": "0x1a6,0x1a7", 464 "MSRValue": "0x3F3FFC0477", 465 "Offcore": "1", 466 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 467 "SampleAfterValue": "100003", 468 "UMask": "0x1" 469 }, 470 { 471 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", 472 "Counter": "0,1,2,3", 473 "EventCode": "0xB7, 0xBB", 474 "EventName": "OCR.READS_TO_CORE.DRAM", 475 "MSRIndex": "0x1a6,0x1a7", 476 "MSRValue": "0x73C000477", 477 "Offcore": "1", 478 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 479 "SampleAfterValue": "100003", 480 "UMask": "0x1" 481 }, 482 { 483 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 484 "Counter": "0,1,2,3", 485 "EventCode": "0xB7, 0xBB", 486 "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", 487 "MSRIndex": "0x1a6,0x1a7", 488 "MSRValue": "0x104000477", 489 "Offcore": "1", 490 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 491 "SampleAfterValue": "100003", 492 "UMask": "0x1" 493 }, 494 { 495 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", 496 "Counter": "0,1,2,3", 497 "EventCode": "0xB7, 0xBB", 498 "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", 499 "MSRIndex": "0x1a6,0x1a7", 500 "MSRValue": "0x100400477", 501 "Offcore": "1", 502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 503 "SampleAfterValue": "100003", 504 "UMask": "0x1" 505 }, 506 { 507 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", 508 "Counter": "0,1,2,3", 509 "EventCode": "0xB7, 0xBB", 510 "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", 511 "MSRIndex": "0x1a6,0x1a7", 512 "MSRValue": "0x70C000477", 513 "Offcore": "1", 514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 515 "SampleAfterValue": "100003", 516 "UMask": "0x1" 517 }, 518 { 519 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", 520 "Counter": "0,1,2,3", 521 "EventCode": "0xB7, 0xBB", 522 "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", 523 "MSRIndex": "0x1a6,0x1a7", 524 "MSRValue": "0x700C00477", 525 "Offcore": "1", 526 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 527 "SampleAfterValue": "100003", 528 "UMask": "0x1" 529 }, 530 { 531 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", 532 "Counter": "0,1,2,3", 533 "EventCode": "0xB7, 0xBB", 534 "EventName": "OCR.READS_TO_CORE.REMOTE", 535 "MSRIndex": "0x1a6,0x1a7", 536 "MSRValue": "0x3F33000477", 537 "Offcore": "1", 538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 539 "SampleAfterValue": "100003", 540 "UMask": "0x1" 541 }, 542 { 543 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", 544 "Counter": "0,1,2,3", 545 "EventCode": "0xB7, 0xBB", 546 "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", 547 "MSRIndex": "0x1a6,0x1a7", 548 "MSRValue": "0x730000477", 549 "Offcore": "1", 550 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 551 "SampleAfterValue": "100003", 552 "UMask": "0x1" 553 }, 554 { 555 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", 556 "Counter": "0,1,2,3", 557 "EventCode": "0xB7, 0xBB", 558 "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", 559 "MSRIndex": "0x1a6,0x1a7", 560 "MSRValue": "0x703000477", 561 "Offcore": "1", 562 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 563 "SampleAfterValue": "100003", 564 "UMask": "0x1" 565 }, 566 { 567 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 568 "Counter": "0,1,2,3", 569 "EventCode": "0xB7, 0xBB", 570 "EventName": "OCR.READS_TO_CORE.SNC_DRAM", 571 "MSRIndex": "0x1a6,0x1a7", 572 "MSRValue": "0x708000477", 573 "Offcore": "1", 574 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 575 "SampleAfterValue": "100003", 576 "UMask": "0x1" 577 }, 578 { 579 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", 580 "Counter": "0,1,2,3", 581 "EventCode": "0xB7, 0xBB", 582 "EventName": "OCR.READS_TO_CORE.SNC_PMM", 583 "MSRIndex": "0x1a6,0x1a7", 584 "MSRValue": "0x700800477", 585 "Offcore": "1", 586 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 587 "SampleAfterValue": "100003", 588 "UMask": "0x1" 589 }, 590 { 591 "BriefDescription": "Counts streaming stores that have any type of response.", 592 "Counter": "0,1,2,3", 593 "EventCode": "0xB7, 0xBB", 594 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 595 "MSRIndex": "0x1a6,0x1a7", 596 "MSRValue": "0x10800", 597 "Offcore": "1", 598 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 599 "SampleAfterValue": "100003", 600 "UMask": "0x1" 601 } 602]