1[ 2 { 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4 "EventCode": "0x08", 5 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 6 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 7 "SampleAfterValue": "100003", 8 "UMask": "0x1" 9 }, 10 { 11 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 12 "EventCode": "0x08", 13 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 14 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 15 "SampleAfterValue": "100003", 16 "UMask": "0x80" 17 }, 18 { 19 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 20 "EventCode": "0x08", 21 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 22 "PublicDescription": "Number of cache load STLB hits. No page walk.", 23 "SampleAfterValue": "2000003", 24 "UMask": "0x60" 25 }, 26 { 27 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 28 "EventCode": "0x08", 29 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 30 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 31 "SampleAfterValue": "2000003", 32 "UMask": "0x40" 33 }, 34 { 35 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 36 "EventCode": "0x08", 37 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 38 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 39 "SampleAfterValue": "2000003", 40 "UMask": "0x20" 41 }, 42 { 43 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 44 "EventCode": "0x08", 45 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 46 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 47 "SampleAfterValue": "100003", 48 "UMask": "0xe" 49 }, 50 { 51 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 52 "EventCode": "0x08", 53 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 54 "SampleAfterValue": "2000003", 55 "UMask": "0x8" 56 }, 57 { 58 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 59 "EventCode": "0x08", 60 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 61 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 62 "SampleAfterValue": "2000003", 63 "UMask": "0x4" 64 }, 65 { 66 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 67 "EventCode": "0x08", 68 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 69 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 70 "SampleAfterValue": "2000003", 71 "UMask": "0x2" 72 }, 73 { 74 "BriefDescription": "Cycles when PMH is busy with page walks", 75 "EventCode": "0x08", 76 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 77 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 78 "SampleAfterValue": "2000003", 79 "UMask": "0x10" 80 }, 81 { 82 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 83 "EventCode": "0x49", 84 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 85 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 86 "SampleAfterValue": "100003", 87 "UMask": "0x1" 88 }, 89 { 90 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 91 "EventCode": "0x49", 92 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 93 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 94 "SampleAfterValue": "100003", 95 "UMask": "0x80" 96 }, 97 { 98 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 99 "EventCode": "0x49", 100 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 101 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 102 "SampleAfterValue": "100003", 103 "UMask": "0x60" 104 }, 105 { 106 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 107 "EventCode": "0x49", 108 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 109 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 110 "SampleAfterValue": "100003", 111 "UMask": "0x40" 112 }, 113 { 114 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 115 "EventCode": "0x49", 116 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 117 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 118 "SampleAfterValue": "100003", 119 "UMask": "0x20" 120 }, 121 { 122 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 123 "EventCode": "0x49", 124 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 125 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 126 "SampleAfterValue": "100003", 127 "UMask": "0xe" 128 }, 129 { 130 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 131 "EventCode": "0x49", 132 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 133 "SampleAfterValue": "100003", 134 "UMask": "0x8" 135 }, 136 { 137 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 138 "EventCode": "0x49", 139 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 140 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 141 "SampleAfterValue": "100003", 142 "UMask": "0x4" 143 }, 144 { 145 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 146 "EventCode": "0x49", 147 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 148 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 149 "SampleAfterValue": "100003", 150 "UMask": "0x2" 151 }, 152 { 153 "BriefDescription": "Cycles when PMH is busy with page walks", 154 "EventCode": "0x49", 155 "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 156 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 157 "SampleAfterValue": "100003", 158 "UMask": "0x10" 159 }, 160 { 161 "BriefDescription": "Cycle count for an Extended Page table walk.", 162 "EventCode": "0x4f", 163 "EventName": "EPT.WALK_CYCLES", 164 "SampleAfterValue": "2000003", 165 "UMask": "0x10" 166 }, 167 { 168 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 169 "EventCode": "0xae", 170 "EventName": "ITLB.ITLB_FLUSH", 171 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 172 "SampleAfterValue": "100003", 173 "UMask": "0x1" 174 }, 175 { 176 "BriefDescription": "Misses at all ITLB levels that cause page walks", 177 "EventCode": "0x85", 178 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 179 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 180 "SampleAfterValue": "100003", 181 "UMask": "0x1" 182 }, 183 { 184 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 185 "EventCode": "0x85", 186 "EventName": "ITLB_MISSES.STLB_HIT", 187 "PublicDescription": "ITLB misses that hit STLB. No page walk.", 188 "SampleAfterValue": "100003", 189 "UMask": "0x60" 190 }, 191 { 192 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 193 "EventCode": "0x85", 194 "EventName": "ITLB_MISSES.STLB_HIT_2M", 195 "PublicDescription": "ITLB misses that hit STLB (2M).", 196 "SampleAfterValue": "100003", 197 "UMask": "0x40" 198 }, 199 { 200 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 201 "EventCode": "0x85", 202 "EventName": "ITLB_MISSES.STLB_HIT_4K", 203 "PublicDescription": "ITLB misses that hit STLB (4K).", 204 "SampleAfterValue": "100003", 205 "UMask": "0x20" 206 }, 207 { 208 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 209 "EventCode": "0x85", 210 "EventName": "ITLB_MISSES.WALK_COMPLETED", 211 "PublicDescription": "Completed page walks in ITLB of any page size.", 212 "SampleAfterValue": "100003", 213 "UMask": "0xe" 214 }, 215 { 216 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 217 "EventCode": "0x85", 218 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 219 "SampleAfterValue": "100003", 220 "UMask": "0x8" 221 }, 222 { 223 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 224 "EventCode": "0x85", 225 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 226 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 227 "SampleAfterValue": "100003", 228 "UMask": "0x4" 229 }, 230 { 231 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 232 "EventCode": "0x85", 233 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 234 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 235 "SampleAfterValue": "100003", 236 "UMask": "0x2" 237 }, 238 { 239 "BriefDescription": "Cycles when PMH is busy with page walks", 240 "EventCode": "0x85", 241 "EventName": "ITLB_MISSES.WALK_DURATION", 242 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 243 "SampleAfterValue": "100003", 244 "UMask": "0x10" 245 }, 246 { 247 "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 248 "EventCode": "0xBC", 249 "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 250 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 251 "SampleAfterValue": "2000003", 252 "UMask": "0x11" 253 }, 254 { 255 "BriefDescription": "Number of DTLB page walker hits in the L2", 256 "EventCode": "0xBC", 257 "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 258 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 259 "SampleAfterValue": "2000003", 260 "UMask": "0x12" 261 }, 262 { 263 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 264 "Errata": "HSD25", 265 "EventCode": "0xBC", 266 "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 267 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 268 "SampleAfterValue": "2000003", 269 "UMask": "0x14" 270 }, 271 { 272 "BriefDescription": "Number of DTLB page walker hits in Memory", 273 "Errata": "HSD25", 274 "EventCode": "0xBC", 275 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 276 "PublicDescription": "Number of DTLB page walker loads from memory.", 277 "SampleAfterValue": "2000003", 278 "UMask": "0x18" 279 }, 280 { 281 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 282 "EventCode": "0xBC", 283 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 284 "SampleAfterValue": "2000003", 285 "UMask": "0x41" 286 }, 287 { 288 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 289 "EventCode": "0xBC", 290 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 291 "SampleAfterValue": "2000003", 292 "UMask": "0x42" 293 }, 294 { 295 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 296 "EventCode": "0xBC", 297 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 298 "SampleAfterValue": "2000003", 299 "UMask": "0x44" 300 }, 301 { 302 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 303 "EventCode": "0xBC", 304 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 305 "SampleAfterValue": "2000003", 306 "UMask": "0x48" 307 }, 308 { 309 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 310 "EventCode": "0xBC", 311 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 312 "SampleAfterValue": "2000003", 313 "UMask": "0x81" 314 }, 315 { 316 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 317 "EventCode": "0xBC", 318 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 319 "SampleAfterValue": "2000003", 320 "UMask": "0x82" 321 }, 322 { 323 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 324 "EventCode": "0xBC", 325 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 326 "SampleAfterValue": "2000003", 327 "UMask": "0x84" 328 }, 329 { 330 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 331 "EventCode": "0xBC", 332 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 333 "SampleAfterValue": "2000003", 334 "UMask": "0x88" 335 }, 336 { 337 "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 338 "EventCode": "0xBC", 339 "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 340 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 341 "SampleAfterValue": "2000003", 342 "UMask": "0x21" 343 }, 344 { 345 "BriefDescription": "Number of ITLB page walker hits in the L2", 346 "EventCode": "0xBC", 347 "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 348 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 349 "SampleAfterValue": "2000003", 350 "UMask": "0x22" 351 }, 352 { 353 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 354 "Errata": "HSD25", 355 "EventCode": "0xBC", 356 "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 357 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 358 "SampleAfterValue": "2000003", 359 "UMask": "0x24" 360 }, 361 { 362 "BriefDescription": "Number of ITLB page walker hits in Memory", 363 "Errata": "HSD25", 364 "EventCode": "0xBC", 365 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 366 "PublicDescription": "Number of ITLB page walker loads from memory.", 367 "SampleAfterValue": "2000003", 368 "UMask": "0x28" 369 }, 370 { 371 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 372 "EventCode": "0xBD", 373 "EventName": "TLB_FLUSH.DTLB_THREAD", 374 "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 375 "SampleAfterValue": "100003", 376 "UMask": "0x1" 377 }, 378 { 379 "BriefDescription": "STLB flush attempts", 380 "EventCode": "0xBD", 381 "EventName": "TLB_FLUSH.STLB_ANY", 382 "PublicDescription": "Count number of STLB flush attempts.", 383 "SampleAfterValue": "100003", 384 "UMask": "0x20" 385 } 386] 387