1[ 2 { 3 "BriefDescription": "Load misses in all DTLB levels that cause page walks", 4 "Counter": "0,1,2,3", 5 "EventCode": "0x08", 6 "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 7 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", 8 "SampleAfterValue": "100003", 9 "UMask": "0x1" 10 }, 11 { 12 "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", 13 "Counter": "0,1,2,3", 14 "EventCode": "0x08", 15 "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", 16 "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", 17 "SampleAfterValue": "100003", 18 "UMask": "0x80" 19 }, 20 { 21 "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", 22 "Counter": "0,1,2,3", 23 "EventCode": "0x08", 24 "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 25 "PublicDescription": "Number of cache load STLB hits. No page walk.", 26 "SampleAfterValue": "2000003", 27 "UMask": "0x60" 28 }, 29 { 30 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", 31 "Counter": "0,1,2,3", 32 "EventCode": "0x08", 33 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", 34 "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 35 "SampleAfterValue": "2000003", 36 "UMask": "0x40" 37 }, 38 { 39 "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", 40 "Counter": "0,1,2,3", 41 "EventCode": "0x08", 42 "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", 43 "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 44 "SampleAfterValue": "2000003", 45 "UMask": "0x20" 46 }, 47 { 48 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", 49 "Counter": "0,1,2,3", 50 "EventCode": "0x08", 51 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 52 "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", 53 "SampleAfterValue": "100003", 54 "UMask": "0xe" 55 }, 56 { 57 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", 58 "Counter": "0,1,2,3", 59 "EventCode": "0x08", 60 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 61 "SampleAfterValue": "2000003", 62 "UMask": "0x8" 63 }, 64 { 65 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", 66 "Counter": "0,1,2,3", 67 "EventCode": "0x08", 68 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 69 "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", 70 "SampleAfterValue": "2000003", 71 "UMask": "0x4" 72 }, 73 { 74 "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", 75 "Counter": "0,1,2,3", 76 "EventCode": "0x08", 77 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 78 "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", 79 "SampleAfterValue": "2000003", 80 "UMask": "0x2" 81 }, 82 { 83 "BriefDescription": "Cycles when PMH is busy with page walks", 84 "Counter": "0,1,2,3", 85 "EventCode": "0x08", 86 "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", 87 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", 88 "SampleAfterValue": "2000003", 89 "UMask": "0x10" 90 }, 91 { 92 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 93 "Counter": "0,1,2,3", 94 "EventCode": "0x49", 95 "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 96 "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", 97 "SampleAfterValue": "100003", 98 "UMask": "0x1" 99 }, 100 { 101 "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", 102 "Counter": "0,1,2,3", 103 "EventCode": "0x49", 104 "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", 105 "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", 106 "SampleAfterValue": "100003", 107 "UMask": "0x80" 108 }, 109 { 110 "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", 111 "Counter": "0,1,2,3", 112 "EventCode": "0x49", 113 "EventName": "DTLB_STORE_MISSES.STLB_HIT", 114 "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", 115 "SampleAfterValue": "100003", 116 "UMask": "0x60" 117 }, 118 { 119 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", 120 "Counter": "0,1,2,3", 121 "EventCode": "0x49", 122 "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", 123 "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", 124 "SampleAfterValue": "100003", 125 "UMask": "0x40" 126 }, 127 { 128 "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", 129 "Counter": "0,1,2,3", 130 "EventCode": "0x49", 131 "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", 132 "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", 133 "SampleAfterValue": "100003", 134 "UMask": "0x20" 135 }, 136 { 137 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", 138 "Counter": "0,1,2,3", 139 "EventCode": "0x49", 140 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 141 "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", 142 "SampleAfterValue": "100003", 143 "UMask": "0xe" 144 }, 145 { 146 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", 147 "Counter": "0,1,2,3", 148 "EventCode": "0x49", 149 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 150 "SampleAfterValue": "100003", 151 "UMask": "0x8" 152 }, 153 { 154 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", 155 "Counter": "0,1,2,3", 156 "EventCode": "0x49", 157 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 158 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", 159 "SampleAfterValue": "100003", 160 "UMask": "0x4" 161 }, 162 { 163 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", 164 "Counter": "0,1,2,3", 165 "EventCode": "0x49", 166 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 167 "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", 168 "SampleAfterValue": "100003", 169 "UMask": "0x2" 170 }, 171 { 172 "BriefDescription": "Cycles when PMH is busy with page walks", 173 "Counter": "0,1,2,3", 174 "EventCode": "0x49", 175 "EventName": "DTLB_STORE_MISSES.WALK_DURATION", 176 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", 177 "SampleAfterValue": "100003", 178 "UMask": "0x10" 179 }, 180 { 181 "BriefDescription": "Cycle count for an Extended Page table walk.", 182 "Counter": "0,1,2,3", 183 "EventCode": "0x4f", 184 "EventName": "EPT.WALK_CYCLES", 185 "SampleAfterValue": "2000003", 186 "UMask": "0x10" 187 }, 188 { 189 "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", 190 "Counter": "0,1,2,3", 191 "EventCode": "0xae", 192 "EventName": "ITLB.ITLB_FLUSH", 193 "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", 194 "SampleAfterValue": "100003", 195 "UMask": "0x1" 196 }, 197 { 198 "BriefDescription": "Misses at all ITLB levels that cause page walks", 199 "Counter": "0,1,2,3", 200 "EventCode": "0x85", 201 "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", 202 "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", 203 "SampleAfterValue": "100003", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", 208 "Counter": "0,1,2,3", 209 "EventCode": "0x85", 210 "EventName": "ITLB_MISSES.STLB_HIT", 211 "PublicDescription": "ITLB misses that hit STLB. No page walk.", 212 "SampleAfterValue": "100003", 213 "UMask": "0x60" 214 }, 215 { 216 "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", 217 "Counter": "0,1,2,3", 218 "EventCode": "0x85", 219 "EventName": "ITLB_MISSES.STLB_HIT_2M", 220 "PublicDescription": "ITLB misses that hit STLB (2M).", 221 "SampleAfterValue": "100003", 222 "UMask": "0x40" 223 }, 224 { 225 "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", 226 "Counter": "0,1,2,3", 227 "EventCode": "0x85", 228 "EventName": "ITLB_MISSES.STLB_HIT_4K", 229 "PublicDescription": "ITLB misses that hit STLB (4K).", 230 "SampleAfterValue": "100003", 231 "UMask": "0x20" 232 }, 233 { 234 "BriefDescription": "Misses in all ITLB levels that cause completed page walks", 235 "Counter": "0,1,2,3", 236 "EventCode": "0x85", 237 "EventName": "ITLB_MISSES.WALK_COMPLETED", 238 "PublicDescription": "Completed page walks in ITLB of any page size.", 239 "SampleAfterValue": "100003", 240 "UMask": "0xe" 241 }, 242 { 243 "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", 244 "Counter": "0,1,2,3", 245 "EventCode": "0x85", 246 "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", 247 "SampleAfterValue": "100003", 248 "UMask": "0x8" 249 }, 250 { 251 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 252 "Counter": "0,1,2,3", 253 "EventCode": "0x85", 254 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 255 "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", 256 "SampleAfterValue": "100003", 257 "UMask": "0x4" 258 }, 259 { 260 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 261 "Counter": "0,1,2,3", 262 "EventCode": "0x85", 263 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 264 "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", 265 "SampleAfterValue": "100003", 266 "UMask": "0x2" 267 }, 268 { 269 "BriefDescription": "Cycles when PMH is busy with page walks", 270 "Counter": "0,1,2,3", 271 "EventCode": "0x85", 272 "EventName": "ITLB_MISSES.WALK_DURATION", 273 "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", 274 "SampleAfterValue": "100003", 275 "UMask": "0x10" 276 }, 277 { 278 "BriefDescription": "Number of DTLB page walker hits in the L1+FB", 279 "Counter": "0,1,2,3", 280 "EventCode": "0xBC", 281 "EventName": "PAGE_WALKER_LOADS.DTLB_L1", 282 "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", 283 "SampleAfterValue": "2000003", 284 "UMask": "0x11" 285 }, 286 { 287 "BriefDescription": "Number of DTLB page walker hits in the L2", 288 "Counter": "0,1,2,3", 289 "EventCode": "0xBC", 290 "EventName": "PAGE_WALKER_LOADS.DTLB_L2", 291 "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", 292 "SampleAfterValue": "2000003", 293 "UMask": "0x12" 294 }, 295 { 296 "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", 297 "Counter": "0,1,2,3", 298 "Errata": "HSD25", 299 "EventCode": "0xBC", 300 "EventName": "PAGE_WALKER_LOADS.DTLB_L3", 301 "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", 302 "SampleAfterValue": "2000003", 303 "UMask": "0x14" 304 }, 305 { 306 "BriefDescription": "Number of DTLB page walker hits in Memory", 307 "Counter": "0,1,2,3", 308 "Errata": "HSD25", 309 "EventCode": "0xBC", 310 "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", 311 "PublicDescription": "Number of DTLB page walker loads from memory.", 312 "SampleAfterValue": "2000003", 313 "UMask": "0x18" 314 }, 315 { 316 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", 317 "Counter": "0,1,2,3", 318 "EventCode": "0xBC", 319 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", 320 "SampleAfterValue": "2000003", 321 "UMask": "0x41" 322 }, 323 { 324 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", 325 "Counter": "0,1,2,3", 326 "EventCode": "0xBC", 327 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", 328 "SampleAfterValue": "2000003", 329 "UMask": "0x42" 330 }, 331 { 332 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", 333 "Counter": "0,1,2,3", 334 "EventCode": "0xBC", 335 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", 336 "SampleAfterValue": "2000003", 337 "UMask": "0x44" 338 }, 339 { 340 "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", 341 "Counter": "0,1,2,3", 342 "EventCode": "0xBC", 343 "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", 344 "SampleAfterValue": "2000003", 345 "UMask": "0x48" 346 }, 347 { 348 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", 349 "Counter": "0,1,2,3", 350 "EventCode": "0xBC", 351 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", 352 "SampleAfterValue": "2000003", 353 "UMask": "0x81" 354 }, 355 { 356 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 357 "Counter": "0,1,2,3", 358 "EventCode": "0xBC", 359 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", 360 "SampleAfterValue": "2000003", 361 "UMask": "0x82" 362 }, 363 { 364 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", 365 "Counter": "0,1,2,3", 366 "EventCode": "0xBC", 367 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", 368 "SampleAfterValue": "2000003", 369 "UMask": "0x84" 370 }, 371 { 372 "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", 373 "Counter": "0,1,2,3", 374 "EventCode": "0xBC", 375 "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", 376 "SampleAfterValue": "2000003", 377 "UMask": "0x88" 378 }, 379 { 380 "BriefDescription": "Number of ITLB page walker hits in the L1+FB", 381 "Counter": "0,1,2,3", 382 "EventCode": "0xBC", 383 "EventName": "PAGE_WALKER_LOADS.ITLB_L1", 384 "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", 385 "SampleAfterValue": "2000003", 386 "UMask": "0x21" 387 }, 388 { 389 "BriefDescription": "Number of ITLB page walker hits in the L2", 390 "Counter": "0,1,2,3", 391 "EventCode": "0xBC", 392 "EventName": "PAGE_WALKER_LOADS.ITLB_L2", 393 "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", 394 "SampleAfterValue": "2000003", 395 "UMask": "0x22" 396 }, 397 { 398 "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", 399 "Counter": "0,1,2,3", 400 "Errata": "HSD25", 401 "EventCode": "0xBC", 402 "EventName": "PAGE_WALKER_LOADS.ITLB_L3", 403 "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", 404 "SampleAfterValue": "2000003", 405 "UMask": "0x24" 406 }, 407 { 408 "BriefDescription": "Number of ITLB page walker hits in Memory", 409 "Counter": "0,1,2,3", 410 "Errata": "HSD25", 411 "EventCode": "0xBC", 412 "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", 413 "PublicDescription": "Number of ITLB page walker loads from memory.", 414 "SampleAfterValue": "2000003", 415 "UMask": "0x28" 416 }, 417 { 418 "BriefDescription": "DTLB flush attempts of the thread-specific entries", 419 "Counter": "0,1,2,3", 420 "EventCode": "0xBD", 421 "EventName": "TLB_FLUSH.DTLB_THREAD", 422 "PublicDescription": "DTLB flush attempts of the thread-specific entries.", 423 "SampleAfterValue": "100003", 424 "UMask": "0x1" 425 }, 426 { 427 "BriefDescription": "STLB flush attempts", 428 "Counter": "0,1,2,3", 429 "EventCode": "0xBD", 430 "EventName": "TLB_FLUSH.STLB_ANY", 431 "PublicDescription": "Count number of STLB flush attempts.", 432 "SampleAfterValue": "100003", 433 "UMask": "0x20" 434 } 435] 436