1[ 2 { 3 "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", 4 "EventCode": "0x05", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "MISALIGN_MEM_REF.LOADS", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", 14 "EventCode": "0x05", 15 "Counter": "0,1,2,3", 16 "UMask": "0x2", 17 "EventName": "MISALIGN_MEM_REF.STORES", 18 "SampleAfterValue": "2000003", 19 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "EventCode": "0x54", 24 "Counter": "0,1,2,3", 25 "UMask": "0x1", 26 "EventName": "TX_MEM.ABORT_CONFLICT", 27 "SampleAfterValue": "2000003", 28 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", 29 "CounterHTOff": "0,1,2,3,4,5,6,7" 30 }, 31 { 32 "EventCode": "0x54", 33 "Counter": "0,1,2,3", 34 "UMask": "0x2", 35 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 36 "SampleAfterValue": "2000003", 37 "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", 38 "CounterHTOff": "0,1,2,3,4,5,6,7" 39 }, 40 { 41 "EventCode": "0x54", 42 "Counter": "0,1,2,3", 43 "UMask": "0x4", 44 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 45 "SampleAfterValue": "2000003", 46 "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", 47 "CounterHTOff": "0,1,2,3,4,5,6,7" 48 }, 49 { 50 "EventCode": "0x54", 51 "Counter": "0,1,2,3", 52 "UMask": "0x8", 53 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 54 "SampleAfterValue": "2000003", 55 "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 56 "CounterHTOff": "0,1,2,3,4,5,6,7" 57 }, 58 { 59 "EventCode": "0x54", 60 "Counter": "0,1,2,3", 61 "UMask": "0x10", 62 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 63 "SampleAfterValue": "2000003", 64 "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", 65 "CounterHTOff": "0,1,2,3,4,5,6,7" 66 }, 67 { 68 "EventCode": "0x54", 69 "Counter": "0,1,2,3", 70 "UMask": "0x20", 71 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 72 "SampleAfterValue": "2000003", 73 "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 74 "CounterHTOff": "0,1,2,3,4,5,6,7" 75 }, 76 { 77 "EventCode": "0x54", 78 "Counter": "0,1,2,3", 79 "UMask": "0x40", 80 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 81 "SampleAfterValue": "2000003", 82 "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 83 "CounterHTOff": "0,1,2,3,4,5,6,7" 84 }, 85 { 86 "EventCode": "0x5d", 87 "Counter": "0,1,2,3", 88 "UMask": "0x1", 89 "EventName": "TX_EXEC.MISC1", 90 "SampleAfterValue": "2000003", 91 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 92 "CounterHTOff": "0,1,2,3,4,5,6,7" 93 }, 94 { 95 "EventCode": "0x5d", 96 "Counter": "0,1,2,3", 97 "UMask": "0x2", 98 "EventName": "TX_EXEC.MISC2", 99 "SampleAfterValue": "2000003", 100 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", 101 "CounterHTOff": "0,1,2,3,4,5,6,7" 102 }, 103 { 104 "EventCode": "0x5d", 105 "Counter": "0,1,2,3", 106 "UMask": "0x4", 107 "EventName": "TX_EXEC.MISC3", 108 "SampleAfterValue": "2000003", 109 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", 110 "CounterHTOff": "0,1,2,3,4,5,6,7" 111 }, 112 { 113 "EventCode": "0x5d", 114 "Counter": "0,1,2,3", 115 "UMask": "0x8", 116 "EventName": "TX_EXEC.MISC4", 117 "SampleAfterValue": "2000003", 118 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 119 "CounterHTOff": "0,1,2,3,4,5,6,7" 120 }, 121 { 122 "EventCode": "0x5d", 123 "Counter": "0,1,2,3", 124 "UMask": "0x10", 125 "EventName": "TX_EXEC.MISC5", 126 "SampleAfterValue": "2000003", 127 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 128 "CounterHTOff": "0,1,2,3,4,5,6,7" 129 }, 130 { 131 "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", 132 "EventCode": "0xC3", 133 "Counter": "0,1,2,3", 134 "UMask": "0x2", 135 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 136 "SampleAfterValue": "100003", 137 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 138 "CounterHTOff": "0,1,2,3,4,5,6,7" 139 }, 140 { 141 "EventCode": "0xC8", 142 "Counter": "0,1,2,3", 143 "UMask": "0x1", 144 "EventName": "HLE_RETIRED.START", 145 "SampleAfterValue": "2000003", 146 "BriefDescription": "Number of times an HLE execution started.", 147 "CounterHTOff": "0,1,2,3,4,5,6,7" 148 }, 149 { 150 "EventCode": "0xc8", 151 "Counter": "0,1,2,3", 152 "UMask": "0x2", 153 "EventName": "HLE_RETIRED.COMMIT", 154 "SampleAfterValue": "2000003", 155 "BriefDescription": "Number of times an HLE execution successfully committed.", 156 "CounterHTOff": "0,1,2,3,4,5,6,7" 157 }, 158 { 159 "PEBS": "1", 160 "EventCode": "0xc8", 161 "Counter": "0,1,2,3", 162 "UMask": "0x4", 163 "EventName": "HLE_RETIRED.ABORTED", 164 "SampleAfterValue": "2000003", 165 "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 166 "CounterHTOff": "0,1,2,3,4,5,6,7" 167 }, 168 { 169 "EventCode": "0xc8", 170 "Counter": "0,1,2,3", 171 "UMask": "0x8", 172 "EventName": "HLE_RETIRED.ABORTED_MISC1", 173 "SampleAfterValue": "2000003", 174 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 175 "CounterHTOff": "0,1,2,3,4,5,6,7" 176 }, 177 { 178 "EventCode": "0xc8", 179 "Counter": "0,1,2,3", 180 "UMask": "0x10", 181 "EventName": "HLE_RETIRED.ABORTED_MISC2", 182 "SampleAfterValue": "2000003", 183 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", 184 "CounterHTOff": "0,1,2,3,4,5,6,7" 185 }, 186 { 187 "EventCode": "0xc8", 188 "Counter": "0,1,2,3", 189 "UMask": "0x20", 190 "EventName": "HLE_RETIRED.ABORTED_MISC3", 191 "SampleAfterValue": "2000003", 192 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", 193 "CounterHTOff": "0,1,2,3,4,5,6,7" 194 }, 195 { 196 "EventCode": "0xc8", 197 "Counter": "0,1,2,3", 198 "UMask": "0x40", 199 "Errata": "HSD65", 200 "EventName": "HLE_RETIRED.ABORTED_MISC4", 201 "SampleAfterValue": "2000003", 202 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", 203 "CounterHTOff": "0,1,2,3,4,5,6,7" 204 }, 205 { 206 "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", 207 "EventCode": "0xc8", 208 "Counter": "0,1,2,3", 209 "UMask": "0x80", 210 "EventName": "HLE_RETIRED.ABORTED_MISC5", 211 "SampleAfterValue": "2000003", 212 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 213 "CounterHTOff": "0,1,2,3,4,5,6,7" 214 }, 215 { 216 "EventCode": "0xC9", 217 "Counter": "0,1,2,3", 218 "UMask": "0x1", 219 "EventName": "RTM_RETIRED.START", 220 "SampleAfterValue": "2000003", 221 "BriefDescription": "Number of times an RTM execution started.", 222 "CounterHTOff": "0,1,2,3" 223 }, 224 { 225 "EventCode": "0xc9", 226 "Counter": "0,1,2,3", 227 "UMask": "0x2", 228 "EventName": "RTM_RETIRED.COMMIT", 229 "SampleAfterValue": "2000003", 230 "BriefDescription": "Number of times an RTM execution successfully committed.", 231 "CounterHTOff": "0,1,2,3" 232 }, 233 { 234 "PEBS": "1", 235 "EventCode": "0xc9", 236 "Counter": "0,1,2,3", 237 "UMask": "0x4", 238 "EventName": "RTM_RETIRED.ABORTED", 239 "SampleAfterValue": "2000003", 240 "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", 241 "CounterHTOff": "0,1,2,3" 242 }, 243 { 244 "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 245 "EventCode": "0xc9", 246 "Counter": "0,1,2,3", 247 "UMask": "0x8", 248 "EventName": "RTM_RETIRED.ABORTED_MISC1", 249 "SampleAfterValue": "2000003", 250 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 251 "CounterHTOff": "0,1,2,3" 252 }, 253 { 254 "EventCode": "0xc9", 255 "Counter": "0,1,2,3", 256 "UMask": "0x10", 257 "EventName": "RTM_RETIRED.ABORTED_MISC2", 258 "SampleAfterValue": "2000003", 259 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 260 "CounterHTOff": "0,1,2,3" 261 }, 262 { 263 "EventCode": "0xc9", 264 "Counter": "0,1,2,3", 265 "UMask": "0x20", 266 "EventName": "RTM_RETIRED.ABORTED_MISC3", 267 "SampleAfterValue": "2000003", 268 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", 269 "CounterHTOff": "0,1,2,3" 270 }, 271 { 272 "EventCode": "0xc9", 273 "Counter": "0,1,2,3", 274 "UMask": "0x40", 275 "Errata": "HSD65", 276 "EventName": "RTM_RETIRED.ABORTED_MISC4", 277 "SampleAfterValue": "2000003", 278 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", 279 "CounterHTOff": "0,1,2,3" 280 }, 281 { 282 "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 283 "EventCode": "0xc9", 284 "Counter": "0,1,2,3", 285 "UMask": "0x80", 286 "EventName": "RTM_RETIRED.ABORTED_MISC5", 287 "SampleAfterValue": "2000003", 288 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 289 "CounterHTOff": "0,1,2,3" 290 }, 291 { 292 "PEBS": "2", 293 "EventCode": "0xCD", 294 "MSRValue": "0x4", 295 "Counter": "3", 296 "UMask": "0x1", 297 "Errata": "HSD76, HSD25, HSM26", 298 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 299 "MSRIndex": "0x3F6", 300 "SampleAfterValue": "100003", 301 "BriefDescription": "Loads with latency value being above 4.", 302 "TakenAlone": "1", 303 "CounterHTOff": "3" 304 }, 305 { 306 "PEBS": "2", 307 "EventCode": "0xCD", 308 "MSRValue": "0x8", 309 "Counter": "3", 310 "UMask": "0x1", 311 "Errata": "HSD76, HSD25, HSM26", 312 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 313 "MSRIndex": "0x3F6", 314 "SampleAfterValue": "50021", 315 "BriefDescription": "Loads with latency value being above 8.", 316 "TakenAlone": "1", 317 "CounterHTOff": "3" 318 }, 319 { 320 "PEBS": "2", 321 "EventCode": "0xCD", 322 "MSRValue": "0x10", 323 "Counter": "3", 324 "UMask": "0x1", 325 "Errata": "HSD76, HSD25, HSM26", 326 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 327 "MSRIndex": "0x3F6", 328 "SampleAfterValue": "20011", 329 "BriefDescription": "Loads with latency value being above 16.", 330 "TakenAlone": "1", 331 "CounterHTOff": "3" 332 }, 333 { 334 "PEBS": "2", 335 "EventCode": "0xCD", 336 "MSRValue": "0x20", 337 "Counter": "3", 338 "UMask": "0x1", 339 "Errata": "HSD76, HSD25, HSM26", 340 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 341 "MSRIndex": "0x3F6", 342 "SampleAfterValue": "100003", 343 "BriefDescription": "Loads with latency value being above 32.", 344 "TakenAlone": "1", 345 "CounterHTOff": "3" 346 }, 347 { 348 "PEBS": "2", 349 "EventCode": "0xCD", 350 "MSRValue": "0x40", 351 "Counter": "3", 352 "UMask": "0x1", 353 "Errata": "HSD76, HSD25, HSM26", 354 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 355 "MSRIndex": "0x3F6", 356 "SampleAfterValue": "2003", 357 "BriefDescription": "Loads with latency value being above 64.", 358 "TakenAlone": "1", 359 "CounterHTOff": "3" 360 }, 361 { 362 "PEBS": "2", 363 "EventCode": "0xCD", 364 "MSRValue": "0x80", 365 "Counter": "3", 366 "UMask": "0x1", 367 "Errata": "HSD76, HSD25, HSM26", 368 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 369 "MSRIndex": "0x3F6", 370 "SampleAfterValue": "1009", 371 "BriefDescription": "Loads with latency value being above 128.", 372 "TakenAlone": "1", 373 "CounterHTOff": "3" 374 }, 375 { 376 "PEBS": "2", 377 "EventCode": "0xCD", 378 "MSRValue": "0x100", 379 "Counter": "3", 380 "UMask": "0x1", 381 "Errata": "HSD76, HSD25, HSM26", 382 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 383 "MSRIndex": "0x3F6", 384 "SampleAfterValue": "503", 385 "BriefDescription": "Loads with latency value being above 256.", 386 "TakenAlone": "1", 387 "CounterHTOff": "3" 388 }, 389 { 390 "PEBS": "2", 391 "EventCode": "0xCD", 392 "MSRValue": "0x200", 393 "Counter": "3", 394 "UMask": "0x1", 395 "Errata": "HSD76, HSD25, HSM26", 396 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 397 "MSRIndex": "0x3F6", 398 "SampleAfterValue": "101", 399 "BriefDescription": "Loads with latency value being above 512.", 400 "TakenAlone": "1", 401 "CounterHTOff": "3" 402 }, 403 { 404 "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 405 "EventCode": "0xB7, 0xBB", 406 "MSRValue": "0x3fffc08fff", 407 "Counter": "0,1,2,3", 408 "UMask": "0x1", 409 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", 410 "MSRIndex": "0x1a6,0x1a7", 411 "SampleAfterValue": "100003", 412 "BriefDescription": "Counts all requests that miss in the L3", 413 "Offcore": "1", 414 "CounterHTOff": "0,1,2,3" 415 }, 416 { 417 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 418 "EventCode": "0xB7, 0xBB", 419 "MSRValue": "0x01004007f7", 420 "Counter": "0,1,2,3", 421 "UMask": "0x1", 422 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", 423 "MSRIndex": "0x1a6,0x1a7", 424 "SampleAfterValue": "100003", 425 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram", 426 "Offcore": "1", 427 "CounterHTOff": "0,1,2,3" 428 }, 429 { 430 "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 431 "EventCode": "0xB7, 0xBB", 432 "MSRValue": "0x3fffc007f7", 433 "Counter": "0,1,2,3", 434 "UMask": "0x1", 435 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", 436 "MSRIndex": "0x1a6,0x1a7", 437 "SampleAfterValue": "100003", 438 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3", 439 "Offcore": "1", 440 "CounterHTOff": "0,1,2,3" 441 }, 442 { 443 "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 444 "EventCode": "0xB7, 0xBB", 445 "MSRValue": "0x0100400244", 446 "Counter": "0,1,2,3", 447 "UMask": "0x1", 448 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", 449 "MSRIndex": "0x1a6,0x1a7", 450 "SampleAfterValue": "100003", 451 "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram", 452 "Offcore": "1", 453 "CounterHTOff": "0,1,2,3" 454 }, 455 { 456 "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 457 "EventCode": "0xB7, 0xBB", 458 "MSRValue": "0x3fffc00244", 459 "Counter": "0,1,2,3", 460 "UMask": "0x1", 461 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", 462 "MSRIndex": "0x1a6,0x1a7", 463 "SampleAfterValue": "100003", 464 "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3", 465 "Offcore": "1", 466 "CounterHTOff": "0,1,2,3" 467 }, 468 { 469 "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 470 "EventCode": "0xB7, 0xBB", 471 "MSRValue": "0x0100400122", 472 "Counter": "0,1,2,3", 473 "UMask": "0x1", 474 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", 475 "MSRIndex": "0x1a6,0x1a7", 476 "SampleAfterValue": "100003", 477 "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram", 478 "Offcore": "1", 479 "CounterHTOff": "0,1,2,3" 480 }, 481 { 482 "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 483 "EventCode": "0xB7, 0xBB", 484 "MSRValue": "0x3fffc00122", 485 "Counter": "0,1,2,3", 486 "UMask": "0x1", 487 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", 488 "MSRIndex": "0x1a6,0x1a7", 489 "SampleAfterValue": "100003", 490 "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3", 491 "Offcore": "1", 492 "CounterHTOff": "0,1,2,3" 493 }, 494 { 495 "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 496 "EventCode": "0xB7, 0xBB", 497 "MSRValue": "0x0100400091", 498 "Counter": "0,1,2,3", 499 "UMask": "0x1", 500 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", 501 "MSRIndex": "0x1a6,0x1a7", 502 "SampleAfterValue": "100003", 503 "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram", 504 "Offcore": "1", 505 "CounterHTOff": "0,1,2,3" 506 }, 507 { 508 "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 509 "EventCode": "0xB7, 0xBB", 510 "MSRValue": "0x3fffc00091", 511 "Counter": "0,1,2,3", 512 "UMask": "0x1", 513 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", 514 "MSRIndex": "0x1a6,0x1a7", 515 "SampleAfterValue": "100003", 516 "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3", 517 "Offcore": "1", 518 "CounterHTOff": "0,1,2,3" 519 }, 520 { 521 "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 522 "EventCode": "0xB7, 0xBB", 523 "MSRValue": "0x3fffc00200", 524 "Counter": "0,1,2,3", 525 "UMask": "0x1", 526 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", 527 "MSRIndex": "0x1a6,0x1a7", 528 "SampleAfterValue": "100003", 529 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3", 530 "Offcore": "1", 531 "CounterHTOff": "0,1,2,3" 532 }, 533 { 534 "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 535 "EventCode": "0xB7, 0xBB", 536 "MSRValue": "0x3fffc00100", 537 "Counter": "0,1,2,3", 538 "UMask": "0x1", 539 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", 540 "MSRIndex": "0x1a6,0x1a7", 541 "SampleAfterValue": "100003", 542 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3", 543 "Offcore": "1", 544 "CounterHTOff": "0,1,2,3" 545 }, 546 { 547 "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 548 "EventCode": "0xB7, 0xBB", 549 "MSRValue": "0x3fffc00080", 550 "Counter": "0,1,2,3", 551 "UMask": "0x1", 552 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", 553 "MSRIndex": "0x1a6,0x1a7", 554 "SampleAfterValue": "100003", 555 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3", 556 "Offcore": "1", 557 "CounterHTOff": "0,1,2,3" 558 }, 559 { 560 "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 561 "EventCode": "0xB7, 0xBB", 562 "MSRValue": "0x3fffc00040", 563 "Counter": "0,1,2,3", 564 "UMask": "0x1", 565 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", 566 "MSRIndex": "0x1a6,0x1a7", 567 "SampleAfterValue": "100003", 568 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3", 569 "Offcore": "1", 570 "CounterHTOff": "0,1,2,3" 571 }, 572 { 573 "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 574 "EventCode": "0xB7, 0xBB", 575 "MSRValue": "0x3fffc00020", 576 "Counter": "0,1,2,3", 577 "UMask": "0x1", 578 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", 579 "MSRIndex": "0x1a6,0x1a7", 580 "SampleAfterValue": "100003", 581 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3", 582 "Offcore": "1", 583 "CounterHTOff": "0,1,2,3" 584 }, 585 { 586 "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 587 "EventCode": "0xB7, 0xBB", 588 "MSRValue": "0x3fffc00010", 589 "Counter": "0,1,2,3", 590 "UMask": "0x1", 591 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", 592 "MSRIndex": "0x1a6,0x1a7", 593 "SampleAfterValue": "100003", 594 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3", 595 "Offcore": "1", 596 "CounterHTOff": "0,1,2,3" 597 }, 598 { 599 "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 600 "EventCode": "0xB7, 0xBB", 601 "MSRValue": "0x0100400004", 602 "Counter": "0,1,2,3", 603 "UMask": "0x1", 604 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", 605 "MSRIndex": "0x1a6,0x1a7", 606 "SampleAfterValue": "100003", 607 "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram", 608 "Offcore": "1", 609 "CounterHTOff": "0,1,2,3" 610 }, 611 { 612 "PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 613 "EventCode": "0xB7, 0xBB", 614 "MSRValue": "0x3fffc00004", 615 "Counter": "0,1,2,3", 616 "UMask": "0x1", 617 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE", 618 "MSRIndex": "0x1a6,0x1a7", 619 "SampleAfterValue": "100003", 620 "BriefDescription": "Counts all demand code reads that miss in the L3", 621 "Offcore": "1", 622 "CounterHTOff": "0,1,2,3" 623 }, 624 { 625 "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 626 "EventCode": "0xB7, 0xBB", 627 "MSRValue": "0x0100400002", 628 "Counter": "0,1,2,3", 629 "UMask": "0x1", 630 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", 631 "MSRIndex": "0x1a6,0x1a7", 632 "SampleAfterValue": "100003", 633 "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram", 634 "Offcore": "1", 635 "CounterHTOff": "0,1,2,3" 636 }, 637 { 638 "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 639 "EventCode": "0xB7, 0xBB", 640 "MSRValue": "0x3fffc00002", 641 "Counter": "0,1,2,3", 642 "UMask": "0x1", 643 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", 644 "MSRIndex": "0x1a6,0x1a7", 645 "SampleAfterValue": "100003", 646 "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3", 647 "Offcore": "1", 648 "CounterHTOff": "0,1,2,3" 649 }, 650 { 651 "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 652 "EventCode": "0xB7, 0xBB", 653 "MSRValue": "0x0100400001", 654 "Counter": "0,1,2,3", 655 "UMask": "0x1", 656 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", 657 "MSRIndex": "0x1a6,0x1a7", 658 "SampleAfterValue": "100003", 659 "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram", 660 "Offcore": "1", 661 "CounterHTOff": "0,1,2,3" 662 }, 663 { 664 "PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 665 "EventCode": "0xB7, 0xBB", 666 "MSRValue": "0x3fffc00001", 667 "Counter": "0,1,2,3", 668 "UMask": "0x1", 669 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE", 670 "MSRIndex": "0x1a6,0x1a7", 671 "SampleAfterValue": "100003", 672 "BriefDescription": "Counts demand data reads that miss in the L3", 673 "Offcore": "1", 674 "CounterHTOff": "0,1,2,3" 675 } 676]