1[ 2 { 3 "PublicDescription": "Demand data read requests that missed L2, no rejects.", 4 "EventCode": "0x24", 5 "Counter": "0,1,2,3", 6 "UMask": "0x21", 7 "Errata": "HSD78", 8 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 9 "SampleAfterValue": "200003", 10 "BriefDescription": "Demand Data Read miss L2, no rejects", 11 "CounterHTOff": "0,1,2,3,4,5,6,7" 12 }, 13 { 14 "PublicDescription": "Demand data read requests that hit L2 cache.", 15 "EventCode": "0x24", 16 "Counter": "0,1,2,3", 17 "UMask": "0x41", 18 "Errata": "HSD78", 19 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 20 "SampleAfterValue": "200003", 21 "BriefDescription": "Demand Data Read requests that hit L2 cache", 22 "CounterHTOff": "0,1,2,3,4,5,6,7" 23 }, 24 { 25 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", 26 "EventCode": "0x24", 27 "Counter": "0,1,2,3", 28 "UMask": "0x30", 29 "EventName": "L2_RQSTS.L2_PF_MISS", 30 "SampleAfterValue": "200003", 31 "BriefDescription": "L2 prefetch requests that miss L2 cache", 32 "CounterHTOff": "0,1,2,3,4,5,6,7" 33 }, 34 { 35 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", 36 "EventCode": "0x24", 37 "Counter": "0,1,2,3", 38 "UMask": "0x50", 39 "EventName": "L2_RQSTS.L2_PF_HIT", 40 "SampleAfterValue": "200003", 41 "BriefDescription": "L2 prefetch requests that hit L2 cache", 42 "CounterHTOff": "0,1,2,3,4,5,6,7" 43 }, 44 { 45 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", 46 "EventCode": "0x24", 47 "Counter": "0,1,2,3", 48 "UMask": "0xe1", 49 "Errata": "HSD78", 50 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 51 "SampleAfterValue": "200003", 52 "BriefDescription": "Demand Data Read requests", 53 "CounterHTOff": "0,1,2,3,4,5,6,7" 54 }, 55 { 56 "PublicDescription": "Counts all L2 store RFO requests.", 57 "EventCode": "0x24", 58 "Counter": "0,1,2,3", 59 "UMask": "0xe2", 60 "EventName": "L2_RQSTS.ALL_RFO", 61 "SampleAfterValue": "200003", 62 "BriefDescription": "RFO requests to L2 cache", 63 "CounterHTOff": "0,1,2,3,4,5,6,7" 64 }, 65 { 66 "PublicDescription": "Counts all L2 code requests.", 67 "EventCode": "0x24", 68 "Counter": "0,1,2,3", 69 "UMask": "0xe4", 70 "EventName": "L2_RQSTS.ALL_CODE_RD", 71 "SampleAfterValue": "200003", 72 "BriefDescription": "L2 code requests", 73 "CounterHTOff": "0,1,2,3,4,5,6,7" 74 }, 75 { 76 "PublicDescription": "Counts all L2 HW prefetcher requests.", 77 "EventCode": "0x24", 78 "Counter": "0,1,2,3", 79 "UMask": "0xf8", 80 "EventName": "L2_RQSTS.ALL_PF", 81 "SampleAfterValue": "200003", 82 "BriefDescription": "Requests from L2 hardware prefetchers", 83 "CounterHTOff": "0,1,2,3,4,5,6,7" 84 }, 85 { 86 "PublicDescription": "Not rejected writebacks that hit L2 cache.", 87 "EventCode": "0x27", 88 "Counter": "0,1,2,3", 89 "UMask": "0x50", 90 "EventName": "L2_DEMAND_RQSTS.WB_HIT", 91 "SampleAfterValue": "200003", 92 "BriefDescription": "Not rejected writebacks that hit L2 cache", 93 "CounterHTOff": "0,1,2,3,4,5,6,7" 94 }, 95 { 96 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", 97 "EventCode": "0x2E", 98 "Counter": "0,1,2,3", 99 "UMask": "0x41", 100 "EventName": "LONGEST_LAT_CACHE.MISS", 101 "SampleAfterValue": "100003", 102 "BriefDescription": "Core-originated cacheable demand requests missed L3", 103 "CounterHTOff": "0,1,2,3,4,5,6,7" 104 }, 105 { 106 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", 107 "EventCode": "0x2E", 108 "Counter": "0,1,2,3", 109 "UMask": "0x4f", 110 "EventName": "LONGEST_LAT_CACHE.REFERENCE", 111 "SampleAfterValue": "100003", 112 "BriefDescription": "Core-originated cacheable demand requests that refer to L3", 113 "CounterHTOff": "0,1,2,3,4,5,6,7" 114 }, 115 { 116 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", 117 "EventCode": "0x48", 118 "Counter": "2", 119 "UMask": "0x1", 120 "EventName": "L1D_PEND_MISS.PENDING", 121 "SampleAfterValue": "2000003", 122 "BriefDescription": "L1D miss oustandings duration in cycles", 123 "CounterHTOff": "2" 124 }, 125 { 126 "EventCode": "0x48", 127 "Counter": "0,1,2,3", 128 "UMask": "0x2", 129 "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", 130 "SampleAfterValue": "2000003", 131 "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", 132 "CounterHTOff": "0,1,2,3,4,5,6,7" 133 }, 134 { 135 "EventCode": "0x48", 136 "Counter": "2", 137 "UMask": "0x1", 138 "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 139 "SampleAfterValue": "2000003", 140 "BriefDescription": "Cycles with L1D load Misses outstanding.", 141 "CounterMask": "1", 142 "CounterHTOff": "2" 143 }, 144 { 145 "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", 146 "EventCode": "0x51", 147 "Counter": "0,1,2,3", 148 "UMask": "0x1", 149 "EventName": "L1D.REPLACEMENT", 150 "SampleAfterValue": "2000003", 151 "BriefDescription": "L1D data line replacements", 152 "CounterHTOff": "0,1,2,3,4,5,6,7" 153 }, 154 { 155 "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 156 "EventCode": "0x60", 157 "Counter": "0,1,2,3", 158 "UMask": "0x1", 159 "Errata": "HSD78, HSD62, HSD61", 160 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 161 "SampleAfterValue": "2000003", 162 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", 163 "CounterHTOff": "0,1,2,3,4,5,6,7" 164 }, 165 { 166 "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 167 "EventCode": "0x60", 168 "Counter": "0,1,2,3", 169 "UMask": "0x2", 170 "Errata": "HSD62, HSD61", 171 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 172 "SampleAfterValue": "2000003", 173 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", 174 "CounterHTOff": "0,1,2,3,4,5,6,7" 175 }, 176 { 177 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", 178 "EventCode": "0x60", 179 "Counter": "0,1,2,3", 180 "UMask": "0x4", 181 "Errata": "HSD62, HSD61", 182 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 183 "SampleAfterValue": "2000003", 184 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", 185 "CounterHTOff": "0,1,2,3,4,5,6,7" 186 }, 187 { 188 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", 189 "EventCode": "0x60", 190 "Counter": "0,1,2,3", 191 "UMask": "0x8", 192 "Errata": "HSD62, HSD61", 193 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 194 "SampleAfterValue": "2000003", 195 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", 196 "CounterHTOff": "0,1,2,3,4,5,6,7" 197 }, 198 { 199 "EventCode": "0x60", 200 "Counter": "0,1,2,3", 201 "UMask": "0x1", 202 "Errata": "HSD78, HSD62, HSD61", 203 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", 204 "SampleAfterValue": "2000003", 205 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 206 "CounterMask": "1", 207 "CounterHTOff": "0,1,2,3,4,5,6,7" 208 }, 209 { 210 "EventCode": "0x60", 211 "Counter": "0,1,2,3", 212 "UMask": "0x8", 213 "Errata": "HSD62, HSD61", 214 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 215 "SampleAfterValue": "2000003", 216 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", 217 "CounterMask": "1", 218 "CounterHTOff": "0,1,2,3,4,5,6,7" 219 }, 220 { 221 "EventCode": "0x60", 222 "Counter": "0,1,2,3", 223 "UMask": "0x4", 224 "Errata": "HSD62, HSD61", 225 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 226 "SampleAfterValue": "2000003", 227 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", 228 "CounterMask": "1", 229 "CounterHTOff": "0,1,2,3,4,5,6,7" 230 }, 231 { 232 "PublicDescription": "Cycles in which the L1D is locked.", 233 "EventCode": "0x63", 234 "Counter": "0,1,2,3", 235 "UMask": "0x2", 236 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", 237 "SampleAfterValue": "2000003", 238 "BriefDescription": "Cycles when L1D is locked", 239 "CounterHTOff": "0,1,2,3,4,5,6,7" 240 }, 241 { 242 "PublicDescription": "Demand data read requests sent to uncore.", 243 "EventCode": "0xB0", 244 "Counter": "0,1,2,3", 245 "UMask": "0x1", 246 "Errata": "HSD78", 247 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 248 "SampleAfterValue": "100003", 249 "BriefDescription": "Demand Data Read requests sent to uncore", 250 "CounterHTOff": "0,1,2,3,4,5,6,7" 251 }, 252 { 253 "PublicDescription": "Demand code read requests sent to uncore.", 254 "EventCode": "0xB0", 255 "Counter": "0,1,2,3", 256 "UMask": "0x2", 257 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", 258 "SampleAfterValue": "100003", 259 "BriefDescription": "Cacheable and noncachaeble code read requests", 260 "CounterHTOff": "0,1,2,3,4,5,6,7" 261 }, 262 { 263 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", 264 "EventCode": "0xB0", 265 "Counter": "0,1,2,3", 266 "UMask": "0x4", 267 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 268 "SampleAfterValue": "100003", 269 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 270 "CounterHTOff": "0,1,2,3,4,5,6,7" 271 }, 272 { 273 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", 274 "EventCode": "0xB0", 275 "Counter": "0,1,2,3", 276 "UMask": "0x8", 277 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 278 "SampleAfterValue": "100003", 279 "BriefDescription": "Demand and prefetch data reads", 280 "CounterHTOff": "0,1,2,3,4,5,6,7" 281 }, 282 { 283 "EventCode": "0xb2", 284 "Counter": "0,1,2,3", 285 "UMask": "0x1", 286 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 287 "SampleAfterValue": "2000003", 288 "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", 289 "CounterHTOff": "0,1,2,3,4,5,6,7" 290 }, 291 { 292 "PEBS": "1", 293 "EventCode": "0xD0", 294 "Counter": "0,1,2,3", 295 "UMask": "0x11", 296 "Errata": "HSD29, HSM30", 297 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", 298 "SampleAfterValue": "100003", 299 "BriefDescription": "Retired load uops that miss the STLB.", 300 "CounterHTOff": "0,1,2,3", 301 "Data_LA": "1" 302 }, 303 { 304 "PEBS": "1", 305 "EventCode": "0xD0", 306 "Counter": "0,1,2,3", 307 "UMask": "0x12", 308 "Errata": "HSD29, HSM30", 309 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", 310 "SampleAfterValue": "100003", 311 "BriefDescription": "Retired store uops that miss the STLB.", 312 "CounterHTOff": "0,1,2,3", 313 "Data_LA": "1", 314 "L1_Hit_Indication": "1" 315 }, 316 { 317 "PEBS": "1", 318 "EventCode": "0xD0", 319 "Counter": "0,1,2,3", 320 "UMask": "0x21", 321 "Errata": "HSD76, HSD29, HSM30", 322 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 323 "SampleAfterValue": "100003", 324 "BriefDescription": "Retired load uops with locked access.", 325 "CounterHTOff": "0,1,2,3", 326 "Data_LA": "1" 327 }, 328 { 329 "PEBS": "1", 330 "EventCode": "0xD0", 331 "Counter": "0,1,2,3", 332 "UMask": "0x41", 333 "Errata": "HSD29, HSM30", 334 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 335 "SampleAfterValue": "100003", 336 "BriefDescription": "Retired load uops that split across a cacheline boundary.", 337 "CounterHTOff": "0,1,2,3", 338 "Data_LA": "1" 339 }, 340 { 341 "PEBS": "1", 342 "EventCode": "0xD0", 343 "Counter": "0,1,2,3", 344 "UMask": "0x42", 345 "Errata": "HSD29, HSM30", 346 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 347 "SampleAfterValue": "100003", 348 "BriefDescription": "Retired store uops that split across a cacheline boundary.", 349 "CounterHTOff": "0,1,2,3", 350 "Data_LA": "1", 351 "L1_Hit_Indication": "1" 352 }, 353 { 354 "PEBS": "1", 355 "EventCode": "0xD0", 356 "Counter": "0,1,2,3", 357 "UMask": "0x81", 358 "Errata": "HSD29, HSM30", 359 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", 360 "SampleAfterValue": "2000003", 361 "BriefDescription": "All retired load uops.", 362 "CounterHTOff": "0,1,2,3", 363 "Data_LA": "1" 364 }, 365 { 366 "PEBS": "1", 367 "EventCode": "0xD0", 368 "Counter": "0,1,2,3", 369 "UMask": "0x82", 370 "Errata": "HSD29, HSM30", 371 "EventName": "MEM_UOPS_RETIRED.ALL_STORES", 372 "SampleAfterValue": "2000003", 373 "BriefDescription": "All retired store uops.", 374 "CounterHTOff": "0,1,2,3", 375 "Data_LA": "1", 376 "L1_Hit_Indication": "1" 377 }, 378 { 379 "PEBS": "1", 380 "EventCode": "0xD1", 381 "Counter": "0,1,2,3", 382 "UMask": "0x1", 383 "Errata": "HSD29, HSM30", 384 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 385 "SampleAfterValue": "2000003", 386 "BriefDescription": "Retired load uops with L1 cache hits as data sources.", 387 "CounterHTOff": "0,1,2,3", 388 "Data_LA": "1" 389 }, 390 { 391 "PEBS": "1", 392 "EventCode": "0xD1", 393 "Counter": "0,1,2,3", 394 "UMask": "0x2", 395 "Errata": "HSD76, HSD29, HSM30", 396 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 397 "SampleAfterValue": "100003", 398 "BriefDescription": "Retired load uops with L2 cache hits as data sources.", 399 "CounterHTOff": "0,1,2,3", 400 "Data_LA": "1" 401 }, 402 { 403 "PEBS": "1", 404 "PublicDescription": "Retired load uops with L3 cache hits as data sources.", 405 "EventCode": "0xD1", 406 "Counter": "0,1,2,3", 407 "UMask": "0x4", 408 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 409 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 410 "SampleAfterValue": "50021", 411 "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", 412 "CounterHTOff": "0,1,2,3", 413 "Data_LA": "1" 414 }, 415 { 416 "PEBS": "1", 417 "PublicDescription": "Retired load uops missed L1 cache as data sources.", 418 "EventCode": "0xD1", 419 "Counter": "0,1,2,3", 420 "UMask": "0x8", 421 "Errata": "HSM30", 422 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 423 "SampleAfterValue": "100003", 424 "BriefDescription": "Retired load uops misses in L1 cache as data sources.", 425 "CounterHTOff": "0,1,2,3", 426 "Data_LA": "1" 427 }, 428 { 429 "PEBS": "1", 430 "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", 431 "EventCode": "0xD1", 432 "Counter": "0,1,2,3", 433 "UMask": "0x10", 434 "Errata": "HSD29, HSM30", 435 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 436 "SampleAfterValue": "50021", 437 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", 438 "CounterHTOff": "0,1,2,3", 439 "Data_LA": "1" 440 }, 441 { 442 "PEBS": "1", 443 "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", 444 "EventCode": "0xD1", 445 "Counter": "0,1,2,3", 446 "UMask": "0x20", 447 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 448 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", 449 "SampleAfterValue": "100003", 450 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", 451 "CounterHTOff": "0,1,2,3", 452 "Data_LA": "1" 453 }, 454 { 455 "PEBS": "1", 456 "EventCode": "0xD1", 457 "Counter": "0,1,2,3", 458 "UMask": "0x40", 459 "Errata": "HSM30", 460 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", 461 "SampleAfterValue": "100003", 462 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", 463 "CounterHTOff": "0,1,2,3", 464 "Data_LA": "1" 465 }, 466 { 467 "PEBS": "1", 468 "EventCode": "0xD2", 469 "Counter": "0,1,2,3", 470 "UMask": "0x1", 471 "Errata": "HSD29, HSD25, HSM26, HSM30", 472 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", 473 "SampleAfterValue": "20011", 474 "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 475 "CounterHTOff": "0,1,2,3", 476 "Data_LA": "1" 477 }, 478 { 479 "PEBS": "1", 480 "EventCode": "0xD2", 481 "Counter": "0,1,2,3", 482 "UMask": "0x2", 483 "Errata": "HSD29, HSD25, HSM26, HSM30", 484 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", 485 "SampleAfterValue": "20011", 486 "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", 487 "CounterHTOff": "0,1,2,3", 488 "Data_LA": "1" 489 }, 490 { 491 "PEBS": "1", 492 "EventCode": "0xD2", 493 "Counter": "0,1,2,3", 494 "UMask": "0x4", 495 "Errata": "HSD29, HSD25, HSM26, HSM30", 496 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", 497 "SampleAfterValue": "20011", 498 "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", 499 "CounterHTOff": "0,1,2,3", 500 "Data_LA": "1" 501 }, 502 { 503 "PEBS": "1", 504 "EventCode": "0xD2", 505 "Counter": "0,1,2,3", 506 "UMask": "0x8", 507 "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", 508 "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", 509 "SampleAfterValue": "100003", 510 "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", 511 "CounterHTOff": "0,1,2,3", 512 "Data_LA": "1" 513 }, 514 { 515 "PEBS": "1", 516 "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", 517 "EventCode": "0xD3", 518 "Counter": "0,1,2,3", 519 "UMask": "0x1", 520 "Errata": "HSD74, HSD29, HSD25, HSM30", 521 "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", 522 "SampleAfterValue": "100003", 523 "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", 524 "CounterHTOff": "0,1,2,3", 525 "Data_LA": "1" 526 }, 527 { 528 "PublicDescription": "Demand data read requests that access L2 cache.", 529 "EventCode": "0xf0", 530 "Counter": "0,1,2,3", 531 "UMask": "0x1", 532 "EventName": "L2_TRANS.DEMAND_DATA_RD", 533 "SampleAfterValue": "200003", 534 "BriefDescription": "Demand Data Read requests that access L2 cache", 535 "CounterHTOff": "0,1,2,3,4,5,6,7" 536 }, 537 { 538 "PublicDescription": "RFO requests that access L2 cache.", 539 "EventCode": "0xf0", 540 "Counter": "0,1,2,3", 541 "UMask": "0x2", 542 "EventName": "L2_TRANS.RFO", 543 "SampleAfterValue": "200003", 544 "BriefDescription": "RFO requests that access L2 cache", 545 "CounterHTOff": "0,1,2,3,4,5,6,7" 546 }, 547 { 548 "PublicDescription": "L2 cache accesses when fetching instructions.", 549 "EventCode": "0xf0", 550 "Counter": "0,1,2,3", 551 "UMask": "0x4", 552 "EventName": "L2_TRANS.CODE_RD", 553 "SampleAfterValue": "200003", 554 "BriefDescription": "L2 cache accesses when fetching instructions", 555 "CounterHTOff": "0,1,2,3,4,5,6,7" 556 }, 557 { 558 "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", 559 "EventCode": "0xf0", 560 "Counter": "0,1,2,3", 561 "UMask": "0x8", 562 "EventName": "L2_TRANS.ALL_PF", 563 "SampleAfterValue": "200003", 564 "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", 565 "CounterHTOff": "0,1,2,3,4,5,6,7" 566 }, 567 { 568 "PublicDescription": "L1D writebacks that access L2 cache.", 569 "EventCode": "0xf0", 570 "Counter": "0,1,2,3", 571 "UMask": "0x10", 572 "EventName": "L2_TRANS.L1D_WB", 573 "SampleAfterValue": "200003", 574 "BriefDescription": "L1D writebacks that access L2 cache", 575 "CounterHTOff": "0,1,2,3,4,5,6,7" 576 }, 577 { 578 "PublicDescription": "L2 fill requests that access L2 cache.", 579 "EventCode": "0xf0", 580 "Counter": "0,1,2,3", 581 "UMask": "0x20", 582 "EventName": "L2_TRANS.L2_FILL", 583 "SampleAfterValue": "200003", 584 "BriefDescription": "L2 fill requests that access L2 cache", 585 "CounterHTOff": "0,1,2,3,4,5,6,7" 586 }, 587 { 588 "PublicDescription": "L2 writebacks that access L2 cache.", 589 "EventCode": "0xf0", 590 "Counter": "0,1,2,3", 591 "UMask": "0x40", 592 "EventName": "L2_TRANS.L2_WB", 593 "SampleAfterValue": "200003", 594 "BriefDescription": "L2 writebacks that access L2 cache", 595 "CounterHTOff": "0,1,2,3,4,5,6,7" 596 }, 597 { 598 "PublicDescription": "Transactions accessing L2 pipe.", 599 "EventCode": "0xf0", 600 "Counter": "0,1,2,3", 601 "UMask": "0x80", 602 "EventName": "L2_TRANS.ALL_REQUESTS", 603 "SampleAfterValue": "200003", 604 "BriefDescription": "Transactions accessing L2 pipe", 605 "CounterHTOff": "0,1,2,3,4,5,6,7" 606 }, 607 { 608 "PublicDescription": "L2 cache lines in I state filling L2.", 609 "EventCode": "0xF1", 610 "Counter": "0,1,2,3", 611 "UMask": "0x1", 612 "EventName": "L2_LINES_IN.I", 613 "SampleAfterValue": "100003", 614 "BriefDescription": "L2 cache lines in I state filling L2", 615 "CounterHTOff": "0,1,2,3,4,5,6,7" 616 }, 617 { 618 "PublicDescription": "L2 cache lines in S state filling L2.", 619 "EventCode": "0xF1", 620 "Counter": "0,1,2,3", 621 "UMask": "0x2", 622 "EventName": "L2_LINES_IN.S", 623 "SampleAfterValue": "100003", 624 "BriefDescription": "L2 cache lines in S state filling L2", 625 "CounterHTOff": "0,1,2,3,4,5,6,7" 626 }, 627 { 628 "PublicDescription": "L2 cache lines in E state filling L2.", 629 "EventCode": "0xF1", 630 "Counter": "0,1,2,3", 631 "UMask": "0x4", 632 "EventName": "L2_LINES_IN.E", 633 "SampleAfterValue": "100003", 634 "BriefDescription": "L2 cache lines in E state filling L2", 635 "CounterHTOff": "0,1,2,3,4,5,6,7" 636 }, 637 { 638 "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", 639 "EventCode": "0xF1", 640 "Counter": "0,1,2,3", 641 "UMask": "0x7", 642 "EventName": "L2_LINES_IN.ALL", 643 "SampleAfterValue": "100003", 644 "BriefDescription": "L2 cache lines filling L2", 645 "CounterHTOff": "0,1,2,3,4,5,6,7" 646 }, 647 { 648 "PublicDescription": "Clean L2 cache lines evicted by demand.", 649 "EventCode": "0xF2", 650 "Counter": "0,1,2,3", 651 "UMask": "0x5", 652 "EventName": "L2_LINES_OUT.DEMAND_CLEAN", 653 "SampleAfterValue": "100003", 654 "BriefDescription": "Clean L2 cache lines evicted by demand", 655 "CounterHTOff": "0,1,2,3,4,5,6,7" 656 }, 657 { 658 "PublicDescription": "Dirty L2 cache lines evicted by demand.", 659 "EventCode": "0xF2", 660 "Counter": "0,1,2,3", 661 "UMask": "0x6", 662 "EventName": "L2_LINES_OUT.DEMAND_DIRTY", 663 "SampleAfterValue": "100003", 664 "BriefDescription": "Dirty L2 cache lines evicted by demand", 665 "CounterHTOff": "0,1,2,3,4,5,6,7" 666 }, 667 { 668 "EventCode": "0xf4", 669 "Counter": "0,1,2,3", 670 "UMask": "0x10", 671 "EventName": "SQ_MISC.SPLIT_LOCK", 672 "SampleAfterValue": "100003", 673 "BriefDescription": "Split locks in SQ", 674 "CounterHTOff": "0,1,2,3,4,5,6,7" 675 }, 676 { 677 "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", 678 "EventCode": "0x24", 679 "Counter": "0,1,2,3", 680 "UMask": "0x42", 681 "EventName": "L2_RQSTS.RFO_HIT", 682 "SampleAfterValue": "200003", 683 "BriefDescription": "RFO requests that hit L2 cache", 684 "CounterHTOff": "0,1,2,3,4,5,6,7" 685 }, 686 { 687 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", 688 "EventCode": "0x24", 689 "Counter": "0,1,2,3", 690 "UMask": "0x22", 691 "EventName": "L2_RQSTS.RFO_MISS", 692 "SampleAfterValue": "200003", 693 "BriefDescription": "RFO requests that miss L2 cache", 694 "CounterHTOff": "0,1,2,3,4,5,6,7" 695 }, 696 { 697 "PublicDescription": "Number of instruction fetches that hit the L2 cache.", 698 "EventCode": "0x24", 699 "Counter": "0,1,2,3", 700 "UMask": "0x44", 701 "EventName": "L2_RQSTS.CODE_RD_HIT", 702 "SampleAfterValue": "200003", 703 "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 704 "CounterHTOff": "0,1,2,3,4,5,6,7" 705 }, 706 { 707 "PublicDescription": "Number of instruction fetches that missed the L2 cache.", 708 "EventCode": "0x24", 709 "Counter": "0,1,2,3", 710 "UMask": "0x24", 711 "EventName": "L2_RQSTS.CODE_RD_MISS", 712 "SampleAfterValue": "200003", 713 "BriefDescription": "L2 cache misses when fetching instructions", 714 "CounterHTOff": "0,1,2,3,4,5,6,7" 715 }, 716 { 717 "PublicDescription": "Demand requests that miss L2 cache.", 718 "EventCode": "0x24", 719 "Counter": "0,1,2,3", 720 "UMask": "0x27", 721 "Errata": "HSD78", 722 "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 723 "SampleAfterValue": "200003", 724 "BriefDescription": "Demand requests that miss L2 cache", 725 "CounterHTOff": "0,1,2,3,4,5,6,7" 726 }, 727 { 728 "PublicDescription": "Demand requests to L2 cache.", 729 "EventCode": "0x24", 730 "Counter": "0,1,2,3", 731 "UMask": "0xe7", 732 "Errata": "HSD78", 733 "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 734 "SampleAfterValue": "200003", 735 "BriefDescription": "Demand requests to L2 cache", 736 "CounterHTOff": "0,1,2,3,4,5,6,7" 737 }, 738 { 739 "PublicDescription": "All requests that missed L2.", 740 "EventCode": "0x24", 741 "Counter": "0,1,2,3", 742 "UMask": "0x3f", 743 "Errata": "HSD78", 744 "EventName": "L2_RQSTS.MISS", 745 "SampleAfterValue": "200003", 746 "BriefDescription": "All requests that miss L2 cache", 747 "CounterHTOff": "0,1,2,3,4,5,6,7" 748 }, 749 { 750 "PublicDescription": "All requests to L2 cache.", 751 "EventCode": "0x24", 752 "Counter": "0,1,2,3", 753 "UMask": "0xff", 754 "Errata": "HSD78", 755 "EventName": "L2_RQSTS.REFERENCES", 756 "SampleAfterValue": "200003", 757 "BriefDescription": "All L2 requests", 758 "CounterHTOff": "0,1,2,3,4,5,6,7" 759 }, 760 { 761 "EventCode": "0xB7, 0xBB", 762 "Counter": "0,1,2,3", 763 "UMask": "0x1", 764 "EventName": "OFFCORE_RESPONSE", 765 "SampleAfterValue": "100003", 766 "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 767 "CounterHTOff": "0,1,2,3" 768 }, 769 { 770 "EventCode": "0x60", 771 "Counter": "0,1,2,3", 772 "UMask": "0x1", 773 "Errata": "HSD78, HSD62, HSD61", 774 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", 775 "SampleAfterValue": "2000003", 776 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", 777 "CounterMask": "6", 778 "CounterHTOff": "0,1,2,3,4,5,6,7" 779 }, 780 { 781 "EventCode": "0x48", 782 "Counter": "2", 783 "UMask": "0x1", 784 "AnyThread": "1", 785 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", 786 "SampleAfterValue": "2000003", 787 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", 788 "CounterMask": "1", 789 "CounterHTOff": "2" 790 }, 791 { 792 "EventCode": "0x48", 793 "Counter": "0,1,2,3", 794 "UMask": "0x2", 795 "EventName": "L1D_PEND_MISS.FB_FULL", 796 "SampleAfterValue": "2000003", 797 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", 798 "CounterMask": "1", 799 "CounterHTOff": "0,1,2,3,4,5,6,7" 800 }, 801 { 802 "EventCode": "0xB7, 0xBB", 803 "MSRValue": "0x3f803c8fff", 804 "Counter": "0,1,2,3", 805 "UMask": "0x1", 806 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", 807 "MSRIndex": "0x1a6,0x1a7", 808 "SampleAfterValue": "100003", 809 "BriefDescription": "Counts all requests that hit in the L3", 810 "Offcore": "1", 811 "CounterHTOff": "0,1,2,3" 812 }, 813 { 814 "EventCode": "0xB7, 0xBB", 815 "MSRValue": "0x10003c07f7", 816 "Counter": "0,1,2,3", 817 "UMask": "0x1", 818 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", 819 "MSRIndex": "0x1a6,0x1a7", 820 "SampleAfterValue": "100003", 821 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 822 "Offcore": "1", 823 "CounterHTOff": "0,1,2,3" 824 }, 825 { 826 "EventCode": "0xB7, 0xBB", 827 "MSRValue": "0x04003c07f7", 828 "Counter": "0,1,2,3", 829 "UMask": "0x1", 830 "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 831 "MSRIndex": "0x1a6,0x1a7", 832 "SampleAfterValue": "100003", 833 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 834 "Offcore": "1", 835 "CounterHTOff": "0,1,2,3" 836 }, 837 { 838 "EventCode": "0xB7, 0xBB", 839 "MSRValue": "0x04003c0244", 840 "Counter": "0,1,2,3", 841 "UMask": "0x1", 842 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 843 "MSRIndex": "0x1a6,0x1a7", 844 "SampleAfterValue": "100003", 845 "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 846 "Offcore": "1", 847 "CounterHTOff": "0,1,2,3" 848 }, 849 { 850 "EventCode": "0xB7, 0xBB", 851 "MSRValue": "0x10003c0122", 852 "Counter": "0,1,2,3", 853 "UMask": "0x1", 854 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 855 "MSRIndex": "0x1a6,0x1a7", 856 "SampleAfterValue": "100003", 857 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 858 "Offcore": "1", 859 "CounterHTOff": "0,1,2,3" 860 }, 861 { 862 "EventCode": "0xB7, 0xBB", 863 "MSRValue": "0x04003c0122", 864 "Counter": "0,1,2,3", 865 "UMask": "0x1", 866 "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 867 "MSRIndex": "0x1a6,0x1a7", 868 "SampleAfterValue": "100003", 869 "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 870 "Offcore": "1", 871 "CounterHTOff": "0,1,2,3" 872 }, 873 { 874 "EventCode": "0xB7, 0xBB", 875 "MSRValue": "0x10003c0091", 876 "Counter": "0,1,2,3", 877 "UMask": "0x1", 878 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 879 "MSRIndex": "0x1a6,0x1a7", 880 "SampleAfterValue": "100003", 881 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 882 "Offcore": "1", 883 "CounterHTOff": "0,1,2,3" 884 }, 885 { 886 "EventCode": "0xB7, 0xBB", 887 "MSRValue": "0x04003c0091", 888 "Counter": "0,1,2,3", 889 "UMask": "0x1", 890 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 891 "MSRIndex": "0x1a6,0x1a7", 892 "SampleAfterValue": "100003", 893 "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 894 "Offcore": "1", 895 "CounterHTOff": "0,1,2,3" 896 }, 897 { 898 "EventCode": "0xB7, 0xBB", 899 "MSRValue": "0x3f803c0200", 900 "Counter": "0,1,2,3", 901 "UMask": "0x1", 902 "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", 903 "MSRIndex": "0x1a6,0x1a7", 904 "SampleAfterValue": "100003", 905 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", 906 "Offcore": "1", 907 "CounterHTOff": "0,1,2,3" 908 }, 909 { 910 "EventCode": "0xB7, 0xBB", 911 "MSRValue": "0x3f803c0100", 912 "Counter": "0,1,2,3", 913 "UMask": "0x1", 914 "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", 915 "MSRIndex": "0x1a6,0x1a7", 916 "SampleAfterValue": "100003", 917 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", 918 "Offcore": "1", 919 "CounterHTOff": "0,1,2,3" 920 }, 921 { 922 "EventCode": "0xB7, 0xBB", 923 "MSRValue": "0x3f803c0080", 924 "Counter": "0,1,2,3", 925 "UMask": "0x1", 926 "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", 927 "MSRIndex": "0x1a6,0x1a7", 928 "SampleAfterValue": "100003", 929 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3", 930 "Offcore": "1", 931 "CounterHTOff": "0,1,2,3" 932 }, 933 { 934 "EventCode": "0xB7, 0xBB", 935 "MSRValue": "0x3f803c0040", 936 "Counter": "0,1,2,3", 937 "UMask": "0x1", 938 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", 939 "MSRIndex": "0x1a6,0x1a7", 940 "SampleAfterValue": "100003", 941 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3", 942 "Offcore": "1", 943 "CounterHTOff": "0,1,2,3" 944 }, 945 { 946 "EventCode": "0xB7, 0xBB", 947 "MSRValue": "0x3f803c0020", 948 "Counter": "0,1,2,3", 949 "UMask": "0x1", 950 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", 951 "MSRIndex": "0x1a6,0x1a7", 952 "SampleAfterValue": "100003", 953 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3", 954 "Offcore": "1", 955 "CounterHTOff": "0,1,2,3" 956 }, 957 { 958 "EventCode": "0xB7, 0xBB", 959 "MSRValue": "0x3f803c0010", 960 "Counter": "0,1,2,3", 961 "UMask": "0x1", 962 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", 963 "MSRIndex": "0x1a6,0x1a7", 964 "SampleAfterValue": "100003", 965 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3", 966 "Offcore": "1", 967 "CounterHTOff": "0,1,2,3" 968 }, 969 { 970 "EventCode": "0xB7, 0xBB", 971 "MSRValue": "0x10003c0004", 972 "Counter": "0,1,2,3", 973 "UMask": "0x1", 974 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 975 "MSRIndex": "0x1a6,0x1a7", 976 "SampleAfterValue": "100003", 977 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 978 "Offcore": "1", 979 "CounterHTOff": "0,1,2,3" 980 }, 981 { 982 "EventCode": "0xB7, 0xBB", 983 "MSRValue": "0x04003c0004", 984 "Counter": "0,1,2,3", 985 "UMask": "0x1", 986 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 987 "MSRIndex": "0x1a6,0x1a7", 988 "SampleAfterValue": "100003", 989 "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 990 "Offcore": "1", 991 "CounterHTOff": "0,1,2,3" 992 }, 993 { 994 "EventCode": "0xB7, 0xBB", 995 "MSRValue": "0x10003c0002", 996 "Counter": "0,1,2,3", 997 "UMask": "0x1", 998 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 999 "MSRIndex": "0x1a6,0x1a7", 1000 "SampleAfterValue": "100003", 1001 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1002 "Offcore": "1", 1003 "CounterHTOff": "0,1,2,3" 1004 }, 1005 { 1006 "EventCode": "0xB7, 0xBB", 1007 "MSRValue": "0x04003c0002", 1008 "Counter": "0,1,2,3", 1009 "UMask": "0x1", 1010 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1011 "MSRIndex": "0x1a6,0x1a7", 1012 "SampleAfterValue": "100003", 1013 "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1014 "Offcore": "1", 1015 "CounterHTOff": "0,1,2,3" 1016 }, 1017 { 1018 "EventCode": "0xB7, 0xBB", 1019 "MSRValue": "0x10003c0001", 1020 "Counter": "0,1,2,3", 1021 "UMask": "0x1", 1022 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 1023 "MSRIndex": "0x1a6,0x1a7", 1024 "SampleAfterValue": "100003", 1025 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", 1026 "Offcore": "1", 1027 "CounterHTOff": "0,1,2,3" 1028 }, 1029 { 1030 "EventCode": "0xB7, 0xBB", 1031 "MSRValue": "0x04003c0001", 1032 "Counter": "0,1,2,3", 1033 "UMask": "0x1", 1034 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1035 "MSRIndex": "0x1a6,0x1a7", 1036 "SampleAfterValue": "100003", 1037 "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", 1038 "Offcore": "1", 1039 "CounterHTOff": "0,1,2,3" 1040 } 1041]