1[ 2 { 3 "BriefDescription": "All branch instructions retired.", 4 "EventCode": "0xc4", 5 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 6 "PEBS": "1", 7 "PublicDescription": "Counts all branch instructions retired.", 8 "SampleAfterValue": "400009" 9 }, 10 { 11 "BriefDescription": "All mispredicted branch instructions retired.", 12 "EventCode": "0xc5", 13 "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 14 "PEBS": "1", 15 "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", 16 "SampleAfterValue": "400009" 17 }, 18 { 19 "BriefDescription": "Reference cycles when the core is not in halt state.", 20 "EventName": "CPU_CLK_UNHALTED.REF_TSC", 21 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 22 "SampleAfterValue": "2000003", 23 "UMask": "0x3" 24 }, 25 { 26 "BriefDescription": "Reference cycles when the core is not in halt state.", 27 "EventCode": "0x3c", 28 "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", 29 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 30 "SampleAfterValue": "2000003", 31 "UMask": "0x1" 32 }, 33 { 34 "BriefDescription": "Core cycles when the thread is not in halt state", 35 "EventName": "CPU_CLK_UNHALTED.THREAD", 36 "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", 37 "SampleAfterValue": "2000003", 38 "UMask": "0x2" 39 }, 40 { 41 "BriefDescription": "Thread cycles when thread is not in halt state", 42 "EventCode": "0x3c", 43 "EventName": "CPU_CLK_UNHALTED.THREAD_P", 44 "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", 45 "SampleAfterValue": "2000003" 46 }, 47 { 48 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 49 "EventName": "INST_RETIRED.ANY", 50 "PEBS": "1", 51 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 52 "SampleAfterValue": "2000003", 53 "UMask": "0x1" 54 }, 55 { 56 "BriefDescription": "Number of instructions retired. General Counter - architectural event", 57 "EventCode": "0xc0", 58 "EventName": "INST_RETIRED.ANY_P", 59 "PEBS": "1", 60 "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 61 "SampleAfterValue": "2000003" 62 }, 63 { 64 "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 65 "EventCode": "0x03", 66 "EventName": "LD_BLOCKS.STORE_FORWARD", 67 "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", 68 "SampleAfterValue": "100003", 69 "UMask": "0x82" 70 }, 71 { 72 "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", 73 "EventCode": "0xa4", 74 "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", 75 "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 76 "SampleAfterValue": "10000003", 77 "UMask": "0x2" 78 }, 79 { 80 "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", 81 "EventName": "TOPDOWN.SLOTS", 82 "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", 83 "SampleAfterValue": "10000003", 84 "UMask": "0x4" 85 }, 86 { 87 "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", 88 "EventCode": "0xa4", 89 "EventName": "TOPDOWN.SLOTS_P", 90 "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", 91 "SampleAfterValue": "10000003", 92 "UMask": "0x1" 93 }, 94 { 95 "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", 96 "EventCode": "0xc2", 97 "EventName": "UOPS_RETIRED.SLOTS", 98 "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 99 "SampleAfterValue": "2000003", 100 "UMask": "0x2" 101 } 102] 103