1[ 2 { 3 "BriefDescription": "ASSISTS.PAGE_FAULT", 4 "Counter": "0,1,2,3,4,5,6,7", 5 "EventCode": "0xc1", 6 "EventName": "ASSISTS.PAGE_FAULT", 7 "SampleAfterValue": "1000003", 8 "UMask": "0x8" 9 }, 10 { 11 "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.", 12 "Counter": "0,1,2,3,4,5,6,7", 13 "EventCode": "0xb7", 14 "EventName": "EXE.AMX_BUSY", 15 "SampleAfterValue": "2000003", 16 "UMask": "0x2" 17 }, 18 { 19 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 20 "Counter": "0,1,2,3", 21 "EventCode": "0x2A,0x2B", 22 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 23 "MSRIndex": "0x1a6,0x1a7", 24 "MSRValue": "0x10004", 25 "SampleAfterValue": "100003", 26 "UMask": "0x1" 27 }, 28 { 29 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 30 "Counter": "0,1,2,3", 31 "EventCode": "0x2A,0x2B", 32 "EventName": "OCR.DEMAND_CODE_RD.DRAM", 33 "MSRIndex": "0x1a6,0x1a7", 34 "MSRValue": "0x73C000004", 35 "SampleAfterValue": "100003", 36 "UMask": "0x1" 37 }, 38 { 39 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 40 "Counter": "0,1,2,3", 41 "EventCode": "0x2A,0x2B", 42 "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 43 "MSRIndex": "0x1a6,0x1a7", 44 "MSRValue": "0x104000004", 45 "SampleAfterValue": "100003", 46 "UMask": "0x1" 47 }, 48 { 49 "BriefDescription": "Counts demand data reads that have any type of response.", 50 "Counter": "0,1,2,3", 51 "EventCode": "0x2A,0x2B", 52 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 53 "MSRIndex": "0x1a6,0x1a7", 54 "MSRValue": "0x10001", 55 "SampleAfterValue": "100003", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 60 "Counter": "0,1,2,3", 61 "EventCode": "0x2A,0x2B", 62 "EventName": "OCR.DEMAND_DATA_RD.DRAM", 63 "MSRIndex": "0x1a6,0x1a7", 64 "MSRValue": "0x73C000001", 65 "SampleAfterValue": "100003", 66 "UMask": "0x1" 67 }, 68 { 69 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", 70 "Counter": "0,1,2,3", 71 "EventCode": "0x2A,0x2B", 72 "EventName": "OCR.DEMAND_RFO.DRAM", 73 "MSRIndex": "0x1a6,0x1a7", 74 "MSRValue": "0x73C000002", 75 "SampleAfterValue": "100003", 76 "UMask": "0x1" 77 }, 78 { 79 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", 80 "Counter": "0,1,2,3", 81 "EventCode": "0x2A,0x2B", 82 "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 83 "MSRIndex": "0x1a6,0x1a7", 84 "MSRValue": "0x104000002", 85 "SampleAfterValue": "100003", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.", 90 "Counter": "0,1,2,3", 91 "EventCode": "0x2A,0x2B", 92 "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", 93 "MSRIndex": "0x1a6,0x1a7", 94 "MSRValue": "0x10808", 95 "SampleAfterValue": "100003", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", 100 "Counter": "0,1,2,3", 101 "EventCode": "0x2A,0x2B", 102 "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", 103 "MSRIndex": "0x1a6,0x1a7", 104 "MSRValue": "0x3F3FFC4477", 105 "SampleAfterValue": "100003", 106 "UMask": "0x1" 107 }, 108 { 109 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", 110 "Counter": "0,1,2,3", 111 "EventCode": "0x2A,0x2B", 112 "EventName": "OCR.READS_TO_CORE.DRAM", 113 "MSRIndex": "0x1a6,0x1a7", 114 "MSRValue": "0x73C004477", 115 "SampleAfterValue": "100003", 116 "UMask": "0x1" 117 }, 118 { 119 "BriefDescription": "Counts streaming stores that have any type of response.", 120 "Counter": "0,1,2,3", 121 "EventCode": "0x2A,0x2B", 122 "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 123 "MSRIndex": "0x1a6,0x1a7", 124 "MSRValue": "0x10800", 125 "SampleAfterValue": "100003", 126 "UMask": "0x1" 127 }, 128 { 129 "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 130 "Counter": "0,1,2,3,4,5,6,7", 131 "EventCode": "0xa5", 132 "EventName": "RS.EMPTY", 133 "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 134 "SampleAfterValue": "1000003", 135 "UMask": "0x7" 136 }, 137 { 138 "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 139 "Counter": "0,1,2,3,4,5,6,7", 140 "CounterMask": "1", 141 "EdgeDetect": "1", 142 "EventCode": "0xa5", 143 "EventName": "RS.EMPTY_COUNT", 144 "Invert": "1", 145 "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 146 "SampleAfterValue": "100003", 147 "UMask": "0x7" 148 }, 149 { 150 "BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted", 151 "Counter": "0,1,2,3,4,5,6,7", 152 "EventCode": "0xa5", 153 "EventName": "RS.EMPTY_RESOURCE", 154 "SampleAfterValue": "1000003", 155 "UMask": "0x1" 156 }, 157 { 158 "BriefDescription": "Cycles the uncore cannot take further requests", 159 "Counter": "0,1,2,3", 160 "CounterMask": "1", 161 "EventCode": "0x2d", 162 "EventName": "XQ.FULL_CYCLES", 163 "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", 164 "SampleAfterValue": "1000003", 165 "UMask": "0x1" 166 } 167] 168