1[ 2 { 3 "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 4 "Counter": "0,1,2,3", 5 "CounterMask": "6", 6 "EventCode": "0xa3", 7 "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 8 "SampleAfterValue": "1000003", 9 "UMask": "0x6" 10 }, 11 { 12 "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 13 "Counter": "0,1,2,3,4,5,6,7", 14 "EventCode": "0xc3", 15 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 16 "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 17 "SampleAfterValue": "100003", 18 "UMask": "0x2" 19 }, 20 { 21 "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 22 "Counter": "0,1,2,3", 23 "CounterMask": "2", 24 "EventCode": "0x47", 25 "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", 26 "SampleAfterValue": "1000003", 27 "UMask": "0x2" 28 }, 29 { 30 "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 31 "Counter": "0,1,2,3", 32 "CounterMask": "3", 33 "EventCode": "0x47", 34 "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", 35 "SampleAfterValue": "1000003", 36 "UMask": "0x3" 37 }, 38 { 39 "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.", 40 "Counter": "0,1,2,3", 41 "CounterMask": "5", 42 "EventCode": "0x47", 43 "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", 44 "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", 45 "SampleAfterValue": "1000003", 46 "UMask": "0x5" 47 }, 48 { 49 "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.", 50 "Counter": "0,1,2,3", 51 "CounterMask": "9", 52 "EventCode": "0x47", 53 "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", 54 "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", 55 "SampleAfterValue": "1000003", 56 "UMask": "0x9" 57 }, 58 { 59 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", 60 "Counter": "1,2,3,4,5,6,7", 61 "Data_LA": "1", 62 "EventCode": "0xcd", 63 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", 64 "MSRIndex": "0x3F6", 65 "MSRValue": "0x400", 66 "PEBS": "2", 67 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", 68 "SampleAfterValue": "53", 69 "UMask": "0x1" 70 }, 71 { 72 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 73 "Counter": "1,2,3,4,5,6,7", 74 "Data_LA": "1", 75 "EventCode": "0xcd", 76 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 77 "MSRIndex": "0x3F6", 78 "MSRValue": "0x80", 79 "PEBS": "2", 80 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 81 "SampleAfterValue": "1009", 82 "UMask": "0x1" 83 }, 84 { 85 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 86 "Counter": "1,2,3,4,5,6,7", 87 "Data_LA": "1", 88 "EventCode": "0xcd", 89 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 90 "MSRIndex": "0x3F6", 91 "MSRValue": "0x10", 92 "PEBS": "2", 93 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 94 "SampleAfterValue": "20011", 95 "UMask": "0x1" 96 }, 97 { 98 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 99 "Counter": "1,2,3,4,5,6,7", 100 "Data_LA": "1", 101 "EventCode": "0xcd", 102 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 103 "MSRIndex": "0x3F6", 104 "MSRValue": "0x100", 105 "PEBS": "2", 106 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 107 "SampleAfterValue": "503", 108 "UMask": "0x1" 109 }, 110 { 111 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 112 "Counter": "1,2,3,4,5,6,7", 113 "Data_LA": "1", 114 "EventCode": "0xcd", 115 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 116 "MSRIndex": "0x3F6", 117 "MSRValue": "0x20", 118 "PEBS": "2", 119 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 120 "SampleAfterValue": "100007", 121 "UMask": "0x1" 122 }, 123 { 124 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 125 "Counter": "1,2,3,4,5,6,7", 126 "Data_LA": "1", 127 "EventCode": "0xcd", 128 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 129 "MSRIndex": "0x3F6", 130 "MSRValue": "0x4", 131 "PEBS": "2", 132 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 133 "SampleAfterValue": "100003", 134 "UMask": "0x1" 135 }, 136 { 137 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 138 "Counter": "1,2,3,4,5,6,7", 139 "Data_LA": "1", 140 "EventCode": "0xcd", 141 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 142 "MSRIndex": "0x3F6", 143 "MSRValue": "0x200", 144 "PEBS": "2", 145 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 146 "SampleAfterValue": "101", 147 "UMask": "0x1" 148 }, 149 { 150 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 151 "Counter": "1,2,3,4,5,6,7", 152 "Data_LA": "1", 153 "EventCode": "0xcd", 154 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 155 "MSRIndex": "0x3F6", 156 "MSRValue": "0x40", 157 "PEBS": "2", 158 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 159 "SampleAfterValue": "2003", 160 "UMask": "0x1" 161 }, 162 { 163 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 164 "Counter": "1,2,3,4,5,6,7", 165 "Data_LA": "1", 166 "EventCode": "0xcd", 167 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 168 "MSRIndex": "0x3F6", 169 "MSRValue": "0x8", 170 "PEBS": "2", 171 "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 172 "SampleAfterValue": "50021", 173 "UMask": "0x1" 174 }, 175 { 176 "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", 177 "Counter": "0", 178 "Data_LA": "1", 179 "EventCode": "0xcd", 180 "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", 181 "PEBS": "2", 182 "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", 183 "SampleAfterValue": "1000003", 184 "UMask": "0x2" 185 }, 186 { 187 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 188 "Counter": "0,1,2,3", 189 "EventCode": "0x2A,0x2B", 190 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 191 "MSRIndex": "0x1a6,0x1a7", 192 "MSRValue": "0x3FBFC00004", 193 "SampleAfterValue": "100003", 194 "UMask": "0x1" 195 }, 196 { 197 "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 198 "Counter": "0,1,2,3", 199 "EventCode": "0x2A,0x2B", 200 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 201 "MSRIndex": "0x1a6,0x1a7", 202 "MSRValue": "0x3FBFC00001", 203 "SampleAfterValue": "100003", 204 "UMask": "0x1" 205 }, 206 { 207 "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 208 "Counter": "0,1,2,3", 209 "EventCode": "0x2A,0x2B", 210 "EventName": "OCR.DEMAND_RFO.L3_MISS", 211 "MSRIndex": "0x1a6,0x1a7", 212 "MSRValue": "0x3F3FC00002", 213 "SampleAfterValue": "100003", 214 "UMask": "0x1" 215 }, 216 { 217 "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 218 "Counter": "0,1,2,3", 219 "EventCode": "0x2A,0x2B", 220 "EventName": "OCR.HWPF_L3.L3_MISS", 221 "MSRIndex": "0x1a6,0x1a7", 222 "MSRValue": "0x94002380", 223 "SampleAfterValue": "100003", 224 "UMask": "0x1" 225 }, 226 { 227 "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 228 "Counter": "0,1,2,3", 229 "EventCode": "0x2A,0x2B", 230 "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", 231 "MSRIndex": "0x1a6,0x1a7", 232 "MSRValue": "0x84002380", 233 "SampleAfterValue": "100003", 234 "UMask": "0x1" 235 }, 236 { 237 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", 238 "Counter": "0,1,2,3", 239 "EventCode": "0x2A,0x2B", 240 "EventName": "OCR.READS_TO_CORE.L3_MISS", 241 "MSRIndex": "0x1a6,0x1a7", 242 "MSRValue": "0x3F3FC04477", 243 "SampleAfterValue": "100003", 244 "UMask": "0x1" 245 }, 246 { 247 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 248 "Counter": "0,1,2,3", 249 "EventCode": "0x2A,0x2B", 250 "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 251 "MSRIndex": "0x1a6,0x1a7", 252 "MSRValue": "0x3F04C04477", 253 "SampleAfterValue": "100003", 254 "UMask": "0x1" 255 }, 256 { 257 "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.", 258 "Counter": "0,1,2,3", 259 "EventCode": "0x2A,0x2B", 260 "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", 261 "MSRIndex": "0x1a6,0x1a7", 262 "MSRValue": "0x70CC04477", 263 "SampleAfterValue": "100003", 264 "UMask": "0x1" 265 }, 266 { 267 "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 268 "Counter": "0,1,2,3", 269 "EventCode": "0x2A,0x2B", 270 "EventName": "OCR.STREAMING_WR.L3_MISS", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x94000800", 273 "SampleAfterValue": "100003", 274 "UMask": "0x1" 275 }, 276 { 277 "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", 278 "Counter": "0,1,2,3", 279 "EventCode": "0x2A,0x2B", 280 "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 281 "MSRIndex": "0x1a6,0x1a7", 282 "MSRValue": "0x84000800", 283 "SampleAfterValue": "100003", 284 "UMask": "0x1" 285 }, 286 { 287 "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 288 "Counter": "0,1,2,3", 289 "EventCode": "0x21", 290 "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 291 "SampleAfterValue": "100003", 292 "UMask": "0x10" 293 }, 294 { 295 "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", 296 "Counter": "0,1,2,3", 297 "EventCode": "0x20", 298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 299 "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.", 300 "SampleAfterValue": "2000003", 301 "UMask": "0x10" 302 }, 303 { 304 "BriefDescription": "Number of times an RTM execution aborted.", 305 "Counter": "0,1,2,3,4,5,6,7", 306 "EventCode": "0xc9", 307 "EventName": "RTM_RETIRED.ABORTED", 308 "PEBS": "1", 309 "PublicDescription": "Counts the number of times RTM abort was triggered.", 310 "SampleAfterValue": "100003", 311 "UMask": "0x4" 312 }, 313 { 314 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 315 "Counter": "0,1,2,3,4,5,6,7", 316 "EventCode": "0xc9", 317 "EventName": "RTM_RETIRED.ABORTED_EVENTS", 318 "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 319 "SampleAfterValue": "100003", 320 "UMask": "0x80" 321 }, 322 { 323 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 324 "Counter": "0,1,2,3,4,5,6,7", 325 "EventCode": "0xc9", 326 "EventName": "RTM_RETIRED.ABORTED_MEM", 327 "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 328 "SampleAfterValue": "100003", 329 "UMask": "0x8" 330 }, 331 { 332 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 333 "Counter": "0,1,2,3,4,5,6,7", 334 "EventCode": "0xc9", 335 "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 336 "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 337 "SampleAfterValue": "100003", 338 "UMask": "0x40" 339 }, 340 { 341 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 342 "Counter": "0,1,2,3,4,5,6,7", 343 "EventCode": "0xc9", 344 "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 345 "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 346 "SampleAfterValue": "100003", 347 "UMask": "0x20" 348 }, 349 { 350 "BriefDescription": "Number of times an RTM execution successfully committed", 351 "Counter": "0,1,2,3,4,5,6,7", 352 "EventCode": "0xc9", 353 "EventName": "RTM_RETIRED.COMMIT", 354 "PublicDescription": "Counts the number of times RTM commit succeeded.", 355 "SampleAfterValue": "100003", 356 "UMask": "0x2" 357 }, 358 { 359 "BriefDescription": "Number of times an RTM execution started.", 360 "Counter": "0,1,2,3,4,5,6,7", 361 "EventCode": "0xc9", 362 "EventName": "RTM_RETIRED.START", 363 "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 364 "SampleAfterValue": "100003", 365 "UMask": "0x1" 366 }, 367 { 368 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 369 "Counter": "0,1,2,3", 370 "EventCode": "0x54", 371 "EventName": "TX_MEM.ABORT_CAPACITY_READ", 372 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 373 "SampleAfterValue": "100003", 374 "UMask": "0x80" 375 }, 376 { 377 "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 378 "Counter": "0,1,2,3", 379 "EventCode": "0x54", 380 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 381 "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 382 "SampleAfterValue": "100003", 383 "UMask": "0x2" 384 }, 385 { 386 "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 387 "Counter": "0,1,2,3", 388 "EventCode": "0x54", 389 "EventName": "TX_MEM.ABORT_CONFLICT", 390 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 391 "SampleAfterValue": "100003", 392 "UMask": "0x1" 393 } 394] 395