1[ 2 { 3 "BriefDescription": "ARITH.FPDIV_ACTIVE", 4 "Counter": "0,1,2,3,4,5,6,7", 5 "CounterMask": "1", 6 "EventCode": "0xb0", 7 "EventName": "ARITH.FPDIV_ACTIVE", 8 "PublicDescription": "ARITH.FPDIV_ACTIVE Available PDIST counters: 0", 9 "SampleAfterValue": "1000003", 10 "UMask": "0x1" 11 }, 12 { 13 "BriefDescription": "Counts all microcode FP assists.", 14 "Counter": "0,1,2,3,4,5,6,7", 15 "EventCode": "0xc1", 16 "EventName": "ASSISTS.FP", 17 "PublicDescription": "Counts all microcode Floating Point assists. Available PDIST counters: 0", 18 "SampleAfterValue": "100003", 19 "UMask": "0x2" 20 }, 21 { 22 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 23 "Counter": "0,1,2,3,4,5,6,7", 24 "EventCode": "0xc1", 25 "EventName": "ASSISTS.SSE_AVX_MIX", 26 "PublicDescription": "ASSISTS.SSE_AVX_MIX Available PDIST counters: 0", 27 "SampleAfterValue": "1000003", 28 "UMask": "0x10" 29 }, 30 { 31 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]", 32 "Counter": "0,1,2,3,4,5,6,7", 33 "EventCode": "0xb3", 34 "EventName": "FP_ARITH_DISPATCHED.PORT_0", 35 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0] Available PDIST counters: 0", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x1" 38 }, 39 { 40 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]", 41 "Counter": "0,1,2,3,4,5,6,7", 42 "EventCode": "0xb3", 43 "EventName": "FP_ARITH_DISPATCHED.PORT_1", 44 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1] Available PDIST counters: 0", 45 "SampleAfterValue": "2000003", 46 "UMask": "0x2" 47 }, 48 { 49 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]", 50 "Counter": "0,1,2,3,4,5,6,7", 51 "EventCode": "0xb3", 52 "EventName": "FP_ARITH_DISPATCHED.PORT_5", 53 "PublicDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2] Available PDIST counters: 0", 54 "SampleAfterValue": "2000003", 55 "UMask": "0x4" 56 }, 57 { 58 "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]", 59 "Counter": "0,1,2,3,4,5,6,7", 60 "EventCode": "0xb3", 61 "EventName": "FP_ARITH_DISPATCHED.V0", 62 "PublicDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0] Available PDIST counters: 0", 63 "SampleAfterValue": "2000003", 64 "UMask": "0x1" 65 }, 66 { 67 "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]", 68 "Counter": "0,1,2,3,4,5,6,7", 69 "EventCode": "0xb3", 70 "EventName": "FP_ARITH_DISPATCHED.V1", 71 "PublicDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1] Available PDIST counters: 0", 72 "SampleAfterValue": "2000003", 73 "UMask": "0x2" 74 }, 75 { 76 "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]", 77 "Counter": "0,1,2,3,4,5,6,7", 78 "EventCode": "0xb3", 79 "EventName": "FP_ARITH_DISPATCHED.V2", 80 "PublicDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5] Available PDIST counters: 0", 81 "SampleAfterValue": "2000003", 82 "UMask": "0x4" 83 }, 84 { 85 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 86 "Counter": "0,1,2,3,4,5,6,7", 87 "EventCode": "0xc7", 88 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 89 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 90 "SampleAfterValue": "100003", 91 "UMask": "0x4" 92 }, 93 { 94 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 95 "Counter": "0,1,2,3,4,5,6,7", 96 "EventCode": "0xc7", 97 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 98 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 99 "SampleAfterValue": "100003", 100 "UMask": "0x8" 101 }, 102 { 103 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 104 "Counter": "0,1,2,3,4,5,6,7", 105 "EventCode": "0xc7", 106 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 107 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 108 "SampleAfterValue": "100003", 109 "UMask": "0x10" 110 }, 111 { 112 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 113 "Counter": "0,1,2,3,4,5,6,7", 114 "EventCode": "0xc7", 115 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 116 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 117 "SampleAfterValue": "100003", 118 "UMask": "0x20" 119 }, 120 { 121 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 122 "Counter": "0,1,2,3,4,5,6,7", 123 "EventCode": "0xc7", 124 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 125 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 126 "SampleAfterValue": "100003", 127 "UMask": "0x18" 128 }, 129 { 130 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 131 "Counter": "0,1,2,3,4,5,6,7", 132 "EventCode": "0xc7", 133 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 134 "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 135 "SampleAfterValue": "100003", 136 "UMask": "0x40" 137 }, 138 { 139 "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 140 "Counter": "0,1,2,3,4,5,6,7", 141 "EventCode": "0xc7", 142 "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 143 "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 144 "SampleAfterValue": "100003", 145 "UMask": "0x80" 146 }, 147 { 148 "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 149 "Counter": "0,1,2,3,4,5,6,7", 150 "EventCode": "0xc7", 151 "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", 152 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 153 "SampleAfterValue": "100003", 154 "UMask": "0x60" 155 }, 156 { 157 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 158 "Counter": "0,1,2,3,4,5,6,7", 159 "EventCode": "0xc7", 160 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 161 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 162 "SampleAfterValue": "1000003", 163 "UMask": "0x3" 164 }, 165 { 166 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 167 "Counter": "0,1,2,3,4,5,6,7", 168 "EventCode": "0xc7", 169 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 170 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 171 "SampleAfterValue": "100003", 172 "UMask": "0x1" 173 }, 174 { 175 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 176 "Counter": "0,1,2,3,4,5,6,7", 177 "EventCode": "0xc7", 178 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 179 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 180 "SampleAfterValue": "100003", 181 "UMask": "0x2" 182 }, 183 { 184 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 185 "Counter": "0,1,2,3,4,5,6,7", 186 "EventCode": "0xc7", 187 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 188 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. Available PDIST counters: 0", 189 "SampleAfterValue": "1000003", 190 "UMask": "0xfc" 191 }, 192 { 193 "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 194 "Counter": "0,1,2,3,4,5,6,7", 195 "EventCode": "0xcf", 196 "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", 197 "PublicDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF Available PDIST counters: 0", 198 "SampleAfterValue": "100003", 199 "UMask": "0x4" 200 }, 201 { 202 "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 203 "Counter": "0,1,2,3,4,5,6,7", 204 "EventCode": "0xcf", 205 "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", 206 "PublicDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF Available PDIST counters: 0", 207 "SampleAfterValue": "100003", 208 "UMask": "0x8" 209 }, 210 { 211 "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 212 "Counter": "0,1,2,3,4,5,6,7", 213 "EventCode": "0xcf", 214 "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", 215 "PublicDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF Available PDIST counters: 0", 216 "SampleAfterValue": "100003", 217 "UMask": "0x10" 218 }, 219 { 220 "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 221 "Counter": "0,1,2,3,4,5,6,7", 222 "EventCode": "0xcf", 223 "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", 224 "PublicDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF Available PDIST counters: 0", 225 "SampleAfterValue": "100003", 226 "UMask": "0x2" 227 }, 228 { 229 "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.", 230 "Counter": "0,1,2,3,4,5,6,7", 231 "EventCode": "0xcf", 232 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", 233 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR Available PDIST counters: 0", 234 "SampleAfterValue": "100003", 235 "UMask": "0x3" 236 }, 237 { 238 "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 239 "Counter": "0,1,2,3,4,5,6,7", 240 "EventCode": "0xcf", 241 "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", 242 "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF Available PDIST counters: 0", 243 "SampleAfterValue": "100003", 244 "UMask": "0x1" 245 }, 246 { 247 "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.", 248 "Counter": "0,1,2,3,4,5,6,7", 249 "EventCode": "0xcf", 250 "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", 251 "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR Available PDIST counters: 0", 252 "SampleAfterValue": "100003", 253 "UMask": "0x1c" 254 } 255] 256