1[ 2 { 3 "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xc3", 6 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 7 "SampleAfterValue": "20003", 8 "UMask": "0x2" 9 }, 10 { 11 "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", 12 "Counter": "0,1,2,3", 13 "EventCode": "0x13", 14 "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", 15 "PEBS": "1", 16 "SampleAfterValue": "200003", 17 "UMask": "0x2" 18 }, 19 { 20 "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", 21 "Counter": "0,1,2,3", 22 "EventCode": "0x13", 23 "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", 24 "PEBS": "1", 25 "SampleAfterValue": "200003", 26 "UMask": "0x4" 27 }, 28 { 29 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 30 "Counter": "0,1,2,3", 31 "EventCode": "0XB7", 32 "EventName": "OCR.ALL_CODE_RD.L3_MISS", 33 "MSRIndex": "0x1a6,0x1a7", 34 "MSRValue": "0x2184000044", 35 "SampleAfterValue": "100003", 36 "UMask": "0x1" 37 }, 38 { 39 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 40 "Counter": "0,1,2,3", 41 "EventCode": "0XB7", 42 "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", 43 "MSRIndex": "0x1a6,0x1a7", 44 "MSRValue": "0x2184000044", 45 "SampleAfterValue": "100003", 46 "UMask": "0x1" 47 }, 48 { 49 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 50 "Counter": "0,1,2,3", 51 "EventCode": "0XB7", 52 "EventName": "OCR.COREWB_M.L3_MISS", 53 "MSRIndex": "0x1a6,0x1a7", 54 "MSRValue": "0x3002184000000", 55 "SampleAfterValue": "100003", 56 "UMask": "0x1" 57 }, 58 { 59 "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", 60 "Counter": "0,1,2,3", 61 "EventCode": "0XB7", 62 "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", 63 "MSRIndex": "0x1a6,0x1a7", 64 "MSRValue": "0x3002184000000", 65 "SampleAfterValue": "100003", 66 "UMask": "0x1" 67 }, 68 { 69 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 70 "Counter": "0,1,2,3", 71 "EventCode": "0XB7", 72 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 73 "MSRIndex": "0x1a6,0x1a7", 74 "MSRValue": "0x2184000004", 75 "SampleAfterValue": "100003", 76 "UMask": "0x1" 77 }, 78 { 79 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 80 "Counter": "0,1,2,3", 81 "EventCode": "0XB7", 82 "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", 83 "MSRIndex": "0x1a6,0x1a7", 84 "MSRValue": "0x2184000004", 85 "SampleAfterValue": "100003", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 90 "Counter": "0,1,2,3", 91 "EventCode": "0XB7", 92 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 93 "MSRIndex": "0x1a6,0x1a7", 94 "MSRValue": "0x2184000001", 95 "SampleAfterValue": "100003", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", 100 "Counter": "0,1,2,3", 101 "EventCode": "0XB7", 102 "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 103 "MSRIndex": "0x1a6,0x1a7", 104 "MSRValue": "0x2184000001", 105 "SampleAfterValue": "100003", 106 "UMask": "0x1" 107 }, 108 { 109 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", 110 "Counter": "0,1,2,3", 111 "Deprecated": "1", 112 "EventCode": "0XB7", 113 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 114 "MSRIndex": "0x1a6,0x1a7", 115 "MSRValue": "0x2184000001", 116 "SampleAfterValue": "100003", 117 "UMask": "0x1" 118 }, 119 { 120 "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", 121 "Counter": "0,1,2,3", 122 "Deprecated": "1", 123 "EventCode": "0XB7", 124 "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", 125 "MSRIndex": "0x1a6,0x1a7", 126 "MSRValue": "0x2184000001", 127 "SampleAfterValue": "100003", 128 "UMask": "0x1" 129 }, 130 { 131 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 132 "Counter": "0,1,2,3", 133 "EventCode": "0XB7", 134 "EventName": "OCR.DEMAND_RFO.L3_MISS", 135 "MSRIndex": "0x1a6,0x1a7", 136 "MSRValue": "0x2184000002", 137 "SampleAfterValue": "100003", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 142 "Counter": "0,1,2,3", 143 "EventCode": "0XB7", 144 "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", 145 "MSRIndex": "0x1a6,0x1a7", 146 "MSRValue": "0x2184000002", 147 "SampleAfterValue": "100003", 148 "UMask": "0x1" 149 }, 150 { 151 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", 152 "Counter": "0,1,2,3", 153 "EventCode": "0XB7", 154 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", 155 "MSRIndex": "0x1a6,0x1a7", 156 "MSRValue": "0x802184000000", 157 "SampleAfterValue": "100003", 158 "UMask": "0x1" 159 }, 160 { 161 "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", 162 "Counter": "0,1,2,3", 163 "EventCode": "0XB7", 164 "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", 165 "MSRIndex": "0x1a6,0x1a7", 166 "MSRValue": "0x802184000000", 167 "SampleAfterValue": "100003", 168 "UMask": "0x1" 169 }, 170 { 171 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", 172 "Counter": "0,1,2,3", 173 "EventCode": "0XB7", 174 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", 175 "MSRIndex": "0x1a6,0x1a7", 176 "MSRValue": "0x2184000040", 177 "SampleAfterValue": "100003", 178 "UMask": "0x1" 179 }, 180 { 181 "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", 182 "Counter": "0,1,2,3", 183 "EventCode": "0XB7", 184 "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", 185 "MSRIndex": "0x1a6,0x1a7", 186 "MSRValue": "0x2184000040", 187 "SampleAfterValue": "100003", 188 "UMask": "0x1" 189 }, 190 { 191 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", 192 "Counter": "0,1,2,3", 193 "EventCode": "0XB7", 194 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", 195 "MSRIndex": "0x1a6,0x1a7", 196 "MSRValue": "0x2184000010", 197 "SampleAfterValue": "100003", 198 "UMask": "0x1" 199 }, 200 { 201 "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", 202 "Counter": "0,1,2,3", 203 "EventCode": "0XB7", 204 "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", 205 "MSRIndex": "0x1a6,0x1a7", 206 "MSRValue": "0x2184000010", 207 "SampleAfterValue": "100003", 208 "UMask": "0x1" 209 }, 210 { 211 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", 212 "Counter": "0,1,2,3", 213 "EventCode": "0XB7", 214 "EventName": "OCR.HWPF_L2_RFO.L3_MISS", 215 "MSRIndex": "0x1a6,0x1a7", 216 "MSRValue": "0x2184000020", 217 "SampleAfterValue": "100003", 218 "UMask": "0x1" 219 }, 220 { 221 "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", 222 "Counter": "0,1,2,3", 223 "EventCode": "0XB7", 224 "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", 225 "MSRIndex": "0x1a6,0x1a7", 226 "MSRValue": "0x2184000020", 227 "SampleAfterValue": "100003", 228 "UMask": "0x1" 229 }, 230 { 231 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", 232 "Counter": "0,1,2,3", 233 "EventCode": "0XB7", 234 "EventName": "OCR.L1WB_M.L3_MISS", 235 "MSRIndex": "0x1a6,0x1a7", 236 "MSRValue": "0x1002184000000", 237 "SampleAfterValue": "100003", 238 "UMask": "0x1" 239 }, 240 { 241 "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", 242 "Counter": "0,1,2,3", 243 "EventCode": "0XB7", 244 "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", 245 "MSRIndex": "0x1a6,0x1a7", 246 "MSRValue": "0x1002184000000", 247 "SampleAfterValue": "100003", 248 "UMask": "0x1" 249 }, 250 { 251 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", 252 "Counter": "0,1,2,3", 253 "EventCode": "0XB7", 254 "EventName": "OCR.L2WB_M.L3_MISS", 255 "MSRIndex": "0x1a6,0x1a7", 256 "MSRValue": "0x2002184000000", 257 "SampleAfterValue": "100003", 258 "UMask": "0x1" 259 }, 260 { 261 "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", 262 "Counter": "0,1,2,3", 263 "EventCode": "0XB7", 264 "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", 265 "MSRIndex": "0x1a6,0x1a7", 266 "MSRValue": "0x2002184000000", 267 "SampleAfterValue": "100003", 268 "UMask": "0x1" 269 }, 270 { 271 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", 272 "Counter": "0,1,2,3", 273 "EventCode": "0XB7", 274 "EventName": "OCR.OTHER.L3_MISS", 275 "MSRIndex": "0x1a6,0x1a7", 276 "MSRValue": "0x2184008000", 277 "SampleAfterValue": "100003", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", 282 "Counter": "0,1,2,3", 283 "EventCode": "0XB7", 284 "EventName": "OCR.OTHER.L3_MISS_LOCAL", 285 "MSRIndex": "0x1a6,0x1a7", 286 "MSRValue": "0x2184008000", 287 "SampleAfterValue": "100003", 288 "UMask": "0x1" 289 }, 290 { 291 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", 292 "Counter": "0,1,2,3", 293 "EventCode": "0XB7", 294 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", 295 "MSRIndex": "0x1a6,0x1a7", 296 "MSRValue": "0x402184000000", 297 "SampleAfterValue": "100003", 298 "UMask": "0x1" 299 }, 300 { 301 "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", 302 "Counter": "0,1,2,3", 303 "EventCode": "0XB7", 304 "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", 305 "MSRIndex": "0x1a6,0x1a7", 306 "MSRValue": "0x402184000000", 307 "SampleAfterValue": "100003", 308 "UMask": "0x1" 309 }, 310 { 311 "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.", 312 "Counter": "0,1,2,3", 313 "EventCode": "0XB7", 314 "EventName": "OCR.PREFETCHES.L3_MISS", 315 "MSRIndex": "0x1a6,0x1a7", 316 "MSRValue": "0x2184000470", 317 "SampleAfterValue": "100003", 318 "UMask": "0x1" 319 }, 320 { 321 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", 322 "Counter": "0,1,2,3", 323 "EventCode": "0XB7", 324 "EventName": "OCR.READS_TO_CORE.L3_MISS", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x2184000477", 327 "SampleAfterValue": "100003", 328 "UMask": "0x1" 329 }, 330 { 331 "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", 332 "Counter": "0,1,2,3", 333 "EventCode": "0XB7", 334 "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", 335 "MSRIndex": "0x1a6,0x1a7", 336 "MSRValue": "0x2184000477", 337 "SampleAfterValue": "100003", 338 "UMask": "0x1" 339 }, 340 { 341 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", 342 "Counter": "0,1,2,3", 343 "EventCode": "0XB7", 344 "EventName": "OCR.STREAMING_WR.L3_MISS", 345 "MSRIndex": "0x1a6,0x1a7", 346 "MSRValue": "0x2184000800", 347 "SampleAfterValue": "100003", 348 "UMask": "0x1" 349 }, 350 { 351 "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", 352 "Counter": "0,1,2,3", 353 "EventCode": "0XB7", 354 "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", 355 "MSRIndex": "0x1a6,0x1a7", 356 "MSRValue": "0x2184000800", 357 "SampleAfterValue": "100003", 358 "UMask": "0x1" 359 }, 360 { 361 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", 362 "Counter": "0,1,2,3", 363 "EventCode": "0XB7", 364 "EventName": "OCR.UC_RD.L3_MISS", 365 "MSRIndex": "0x1a6,0x1a7", 366 "MSRValue": "0x102184000000", 367 "SampleAfterValue": "100003", 368 "UMask": "0x1" 369 }, 370 { 371 "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", 372 "Counter": "0,1,2,3", 373 "EventCode": "0XB7", 374 "EventName": "OCR.UC_RD.L3_MISS_LOCAL", 375 "MSRIndex": "0x1a6,0x1a7", 376 "MSRValue": "0x102184000000", 377 "SampleAfterValue": "100003", 378 "UMask": "0x1" 379 }, 380 { 381 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", 382 "Counter": "0,1,2,3", 383 "EventCode": "0XB7", 384 "EventName": "OCR.UC_WR.L3_MISS", 385 "MSRIndex": "0x1a6,0x1a7", 386 "MSRValue": "0x202184000000", 387 "SampleAfterValue": "100003", 388 "UMask": "0x1" 389 }, 390 { 391 "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", 392 "Counter": "0,1,2,3", 393 "EventCode": "0XB7", 394 "EventName": "OCR.UC_WR.L3_MISS_LOCAL", 395 "MSRIndex": "0x1a6,0x1a7", 396 "MSRValue": "0x202184000000", 397 "SampleAfterValue": "100003", 398 "UMask": "0x1" 399 } 400] 401