1[ 2 { 3 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 "Counter": "0,1,2,3", 5 "CounterHTOff": "0,1,2,3,4,5,6,7", 6 "EventCode": "0x28", 7 "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 8 "PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 9 "SampleAfterValue": "200003", 10 "UMask": "0x7" 11 }, 12 { 13 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 14 "Counter": "0,1,2,3", 15 "CounterHTOff": "0,1,2,3,4,5,6,7", 16 "EventCode": "0x28", 17 "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 18 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 19 "SampleAfterValue": "200003", 20 "UMask": "0x18" 21 }, 22 { 23 "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 24 "Counter": "0,1,2,3", 25 "CounterHTOff": "0,1,2,3,4,5,6,7", 26 "EventCode": "0x28", 27 "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 28 "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.", 29 "SampleAfterValue": "200003", 30 "UMask": "0x20" 31 }, 32 { 33 "BriefDescription": "Core cycles the core was throttled due to a pending power level request.", 34 "Counter": "0,1,2,3", 35 "CounterHTOff": "0,1,2,3,4,5,6,7", 36 "EventCode": "0x28", 37 "EventName": "CORE_POWER.THROTTLE", 38 "PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.", 39 "SampleAfterValue": "200003", 40 "UMask": "0x40" 41 }, 42 { 43 "BriefDescription": "Number of hardware interrupts received by the processor.", 44 "Counter": "0,1,2,3", 45 "CounterHTOff": "0,1,2,3,4,5,6,7", 46 "EventCode": "0xCB", 47 "EventName": "HW_INTERRUPTS.RECEIVED", 48 "PublicDescription": "Counts the number of hardware interruptions received by the processor.", 49 "SampleAfterValue": "203", 50 "UMask": "0x1" 51 }, 52 { 53 "BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly", 54 "Counter": "0,1,2,3", 55 "CounterHTOff": "0,1,2,3,4,5,6,7", 56 "EventCode": "0xFE", 57 "EventName": "IDI_MISC.WB_DOWNGRADE", 58 "PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.", 59 "SampleAfterValue": "100003", 60 "UMask": "0x4" 61 }, 62 { 63 "BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly", 64 "Counter": "0,1,2,3", 65 "CounterHTOff": "0,1,2,3,4,5,6,7", 66 "EventCode": "0xFE", 67 "EventName": "IDI_MISC.WB_UPGRADE", 68 "PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.", 69 "SampleAfterValue": "100003", 70 "UMask": "0x2" 71 }, 72 { 73 "BriefDescription": "OCR.ALL_DATA_RD.ANY_RESPONSE have any response type.", 74 "Counter": "0,1,2,3", 75 "CounterHTOff": "0,1,2,3", 76 "EventCode": "0xB7, 0xBB", 77 "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", 78 "MSRIndex": "0x1a6,0x1a7", 79 "MSRValue": "0x0000010491", 80 "Offcore": "1", 81 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 82 "SampleAfterValue": "100003", 83 "UMask": "0x1" 84 }, 85 { 86 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", 87 "Counter": "0,1,2,3", 88 "CounterHTOff": "0,1,2,3", 89 "EventCode": "0xB7, 0xBB", 90 "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", 91 "MSRIndex": "0x1a6,0x1a7", 92 "MSRValue": "0x3F803C0491", 93 "Offcore": "1", 94 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 95 "SampleAfterValue": "100003", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 100 "Counter": "0,1,2,3", 101 "CounterHTOff": "0,1,2,3", 102 "EventCode": "0xB7, 0xBB", 103 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", 104 "MSRIndex": "0x1a6,0x1a7", 105 "MSRValue": "0x10003C0491", 106 "Offcore": "1", 107 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 108 "SampleAfterValue": "100003", 109 "UMask": "0x1" 110 }, 111 { 112 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 113 "Counter": "0,1,2,3", 114 "CounterHTOff": "0,1,2,3", 115 "EventCode": "0xB7, 0xBB", 116 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 117 "MSRIndex": "0x1a6,0x1a7", 118 "MSRValue": "0x08003C0491", 119 "Offcore": "1", 120 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 121 "SampleAfterValue": "100003", 122 "UMask": "0x1" 123 }, 124 { 125 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 126 "Counter": "0,1,2,3", 127 "CounterHTOff": "0,1,2,3", 128 "EventCode": "0xB7, 0xBB", 129 "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 130 "MSRIndex": "0x1a6,0x1a7", 131 "MSRValue": "0x04003C0491", 132 "Offcore": "1", 133 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 134 "SampleAfterValue": "100003", 135 "UMask": "0x1" 136 }, 137 { 138 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 139 "Counter": "0,1,2,3", 140 "CounterHTOff": "0,1,2,3", 141 "EventCode": "0xB7, 0xBB", 142 "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 143 "MSRIndex": "0x1a6,0x1a7", 144 "MSRValue": "0x01003C0491", 145 "Offcore": "1", 146 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 147 "SampleAfterValue": "100003", 148 "UMask": "0x1" 149 }, 150 { 151 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 152 "Counter": "0,1,2,3", 153 "CounterHTOff": "0,1,2,3", 154 "EventCode": "0xB7, 0xBB", 155 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 156 "MSRIndex": "0x1a6,0x1a7", 157 "MSRValue": "0x08007C0491", 158 "Offcore": "1", 159 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 160 "SampleAfterValue": "100003", 161 "UMask": "0x1" 162 }, 163 { 164 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", 165 "Counter": "0,1,2,3", 166 "CounterHTOff": "0,1,2,3", 167 "EventCode": "0xB7, 0xBB", 168 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", 169 "MSRIndex": "0x1a6,0x1a7", 170 "MSRValue": "0x02003C0491", 171 "Offcore": "1", 172 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 173 "SampleAfterValue": "100003", 174 "UMask": "0x1" 175 }, 176 { 177 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", 178 "Counter": "0,1,2,3", 179 "CounterHTOff": "0,1,2,3", 180 "EventCode": "0xB7, 0xBB", 181 "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", 182 "MSRIndex": "0x1a6,0x1a7", 183 "MSRValue": "0x00803C0491", 184 "Offcore": "1", 185 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 186 "SampleAfterValue": "100003", 187 "UMask": "0x1" 188 }, 189 { 190 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", 191 "Counter": "0,1,2,3", 192 "CounterHTOff": "0,1,2,3", 193 "EventCode": "0xB7, 0xBB", 194 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", 195 "MSRIndex": "0x1a6,0x1a7", 196 "MSRValue": "0x3F80080491", 197 "Offcore": "1", 198 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 199 "SampleAfterValue": "100003", 200 "UMask": "0x1" 201 }, 202 { 203 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 204 "Counter": "0,1,2,3", 205 "CounterHTOff": "0,1,2,3", 206 "EventCode": "0xB7, 0xBB", 207 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 208 "MSRIndex": "0x1a6,0x1a7", 209 "MSRValue": "0x1000080491", 210 "Offcore": "1", 211 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 212 "SampleAfterValue": "100003", 213 "UMask": "0x1" 214 }, 215 { 216 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 217 "Counter": "0,1,2,3", 218 "CounterHTOff": "0,1,2,3", 219 "EventCode": "0xB7, 0xBB", 220 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 221 "MSRIndex": "0x1a6,0x1a7", 222 "MSRValue": "0x0800080491", 223 "Offcore": "1", 224 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 225 "SampleAfterValue": "100003", 226 "UMask": "0x1" 227 }, 228 { 229 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 230 "Counter": "0,1,2,3", 231 "CounterHTOff": "0,1,2,3", 232 "EventCode": "0xB7, 0xBB", 233 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 234 "MSRIndex": "0x1a6,0x1a7", 235 "MSRValue": "0x0400080491", 236 "Offcore": "1", 237 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 238 "SampleAfterValue": "100003", 239 "UMask": "0x1" 240 }, 241 { 242 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 243 "Counter": "0,1,2,3", 244 "CounterHTOff": "0,1,2,3", 245 "EventCode": "0xB7, 0xBB", 246 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 247 "MSRIndex": "0x1a6,0x1a7", 248 "MSRValue": "0x0100080491", 249 "Offcore": "1", 250 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", 256 "Counter": "0,1,2,3", 257 "CounterHTOff": "0,1,2,3", 258 "EventCode": "0xB7, 0xBB", 259 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", 260 "MSRIndex": "0x1a6,0x1a7", 261 "MSRValue": "0x0200080491", 262 "Offcore": "1", 263 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 264 "SampleAfterValue": "100003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", 269 "Counter": "0,1,2,3", 270 "CounterHTOff": "0,1,2,3", 271 "EventCode": "0xB7, 0xBB", 272 "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", 273 "MSRIndex": "0x1a6,0x1a7", 274 "MSRValue": "0x0080080491", 275 "Offcore": "1", 276 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 277 "SampleAfterValue": "100003", 278 "UMask": "0x1" 279 }, 280 { 281 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", 282 "Counter": "0,1,2,3", 283 "CounterHTOff": "0,1,2,3", 284 "EventCode": "0xB7, 0xBB", 285 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", 286 "MSRIndex": "0x1a6,0x1a7", 287 "MSRValue": "0x3F80200491", 288 "Offcore": "1", 289 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 290 "SampleAfterValue": "100003", 291 "UMask": "0x1" 292 }, 293 { 294 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 295 "Counter": "0,1,2,3", 296 "CounterHTOff": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x1000200491", 301 "Offcore": "1", 302 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 303 "SampleAfterValue": "100003", 304 "UMask": "0x1" 305 }, 306 { 307 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 308 "Counter": "0,1,2,3", 309 "CounterHTOff": "0,1,2,3", 310 "EventCode": "0xB7, 0xBB", 311 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 312 "MSRIndex": "0x1a6,0x1a7", 313 "MSRValue": "0x0800200491", 314 "Offcore": "1", 315 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 316 "SampleAfterValue": "100003", 317 "UMask": "0x1" 318 }, 319 { 320 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 321 "Counter": "0,1,2,3", 322 "CounterHTOff": "0,1,2,3", 323 "EventCode": "0xB7, 0xBB", 324 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x0400200491", 327 "Offcore": "1", 328 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 329 "SampleAfterValue": "100003", 330 "UMask": "0x1" 331 }, 332 { 333 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 334 "Counter": "0,1,2,3", 335 "CounterHTOff": "0,1,2,3", 336 "EventCode": "0xB7, 0xBB", 337 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 338 "MSRIndex": "0x1a6,0x1a7", 339 "MSRValue": "0x0100200491", 340 "Offcore": "1", 341 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 342 "SampleAfterValue": "100003", 343 "UMask": "0x1" 344 }, 345 { 346 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", 347 "Counter": "0,1,2,3", 348 "CounterHTOff": "0,1,2,3", 349 "EventCode": "0xB7, 0xBB", 350 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", 351 "MSRIndex": "0x1a6,0x1a7", 352 "MSRValue": "0x0200200491", 353 "Offcore": "1", 354 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 355 "SampleAfterValue": "100003", 356 "UMask": "0x1" 357 }, 358 { 359 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", 360 "Counter": "0,1,2,3", 361 "CounterHTOff": "0,1,2,3", 362 "EventCode": "0xB7, 0xBB", 363 "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", 364 "MSRIndex": "0x1a6,0x1a7", 365 "MSRValue": "0x0080200491", 366 "Offcore": "1", 367 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 368 "SampleAfterValue": "100003", 369 "UMask": "0x1" 370 }, 371 { 372 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", 373 "Counter": "0,1,2,3", 374 "CounterHTOff": "0,1,2,3", 375 "EventCode": "0xB7, 0xBB", 376 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", 377 "MSRIndex": "0x1a6,0x1a7", 378 "MSRValue": "0x3F80040491", 379 "Offcore": "1", 380 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 386 "Counter": "0,1,2,3", 387 "CounterHTOff": "0,1,2,3", 388 "EventCode": "0xB7, 0xBB", 389 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 390 "MSRIndex": "0x1a6,0x1a7", 391 "MSRValue": "0x1000040491", 392 "Offcore": "1", 393 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 394 "SampleAfterValue": "100003", 395 "UMask": "0x1" 396 }, 397 { 398 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 399 "Counter": "0,1,2,3", 400 "CounterHTOff": "0,1,2,3", 401 "EventCode": "0xB7, 0xBB", 402 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 403 "MSRIndex": "0x1a6,0x1a7", 404 "MSRValue": "0x0800040491", 405 "Offcore": "1", 406 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 407 "SampleAfterValue": "100003", 408 "UMask": "0x1" 409 }, 410 { 411 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 412 "Counter": "0,1,2,3", 413 "CounterHTOff": "0,1,2,3", 414 "EventCode": "0xB7, 0xBB", 415 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 416 "MSRIndex": "0x1a6,0x1a7", 417 "MSRValue": "0x0400040491", 418 "Offcore": "1", 419 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 420 "SampleAfterValue": "100003", 421 "UMask": "0x1" 422 }, 423 { 424 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 425 "Counter": "0,1,2,3", 426 "CounterHTOff": "0,1,2,3", 427 "EventCode": "0xB7, 0xBB", 428 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 429 "MSRIndex": "0x1a6,0x1a7", 430 "MSRValue": "0x0100040491", 431 "Offcore": "1", 432 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 433 "SampleAfterValue": "100003", 434 "UMask": "0x1" 435 }, 436 { 437 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", 438 "Counter": "0,1,2,3", 439 "CounterHTOff": "0,1,2,3", 440 "EventCode": "0xB7, 0xBB", 441 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", 442 "MSRIndex": "0x1a6,0x1a7", 443 "MSRValue": "0x0200040491", 444 "Offcore": "1", 445 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 446 "SampleAfterValue": "100003", 447 "UMask": "0x1" 448 }, 449 { 450 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", 451 "Counter": "0,1,2,3", 452 "CounterHTOff": "0,1,2,3", 453 "EventCode": "0xB7, 0xBB", 454 "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", 455 "MSRIndex": "0x1a6,0x1a7", 456 "MSRValue": "0x0080040491", 457 "Offcore": "1", 458 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 459 "SampleAfterValue": "100003", 460 "UMask": "0x1" 461 }, 462 { 463 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", 464 "Counter": "0,1,2,3", 465 "CounterHTOff": "0,1,2,3", 466 "EventCode": "0xB7, 0xBB", 467 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", 468 "MSRIndex": "0x1a6,0x1a7", 469 "MSRValue": "0x3F80100491", 470 "Offcore": "1", 471 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 472 "SampleAfterValue": "100003", 473 "UMask": "0x1" 474 }, 475 { 476 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 477 "Counter": "0,1,2,3", 478 "CounterHTOff": "0,1,2,3", 479 "EventCode": "0xB7, 0xBB", 480 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 481 "MSRIndex": "0x1a6,0x1a7", 482 "MSRValue": "0x1000100491", 483 "Offcore": "1", 484 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 485 "SampleAfterValue": "100003", 486 "UMask": "0x1" 487 }, 488 { 489 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 490 "Counter": "0,1,2,3", 491 "CounterHTOff": "0,1,2,3", 492 "EventCode": "0xB7, 0xBB", 493 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 494 "MSRIndex": "0x1a6,0x1a7", 495 "MSRValue": "0x0800100491", 496 "Offcore": "1", 497 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 498 "SampleAfterValue": "100003", 499 "UMask": "0x1" 500 }, 501 { 502 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 503 "Counter": "0,1,2,3", 504 "CounterHTOff": "0,1,2,3", 505 "EventCode": "0xB7, 0xBB", 506 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 507 "MSRIndex": "0x1a6,0x1a7", 508 "MSRValue": "0x0400100491", 509 "Offcore": "1", 510 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 511 "SampleAfterValue": "100003", 512 "UMask": "0x1" 513 }, 514 { 515 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 516 "Counter": "0,1,2,3", 517 "CounterHTOff": "0,1,2,3", 518 "EventCode": "0xB7, 0xBB", 519 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 520 "MSRIndex": "0x1a6,0x1a7", 521 "MSRValue": "0x0100100491", 522 "Offcore": "1", 523 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 524 "SampleAfterValue": "100003", 525 "UMask": "0x1" 526 }, 527 { 528 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", 529 "Counter": "0,1,2,3", 530 "CounterHTOff": "0,1,2,3", 531 "EventCode": "0xB7, 0xBB", 532 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", 533 "MSRIndex": "0x1a6,0x1a7", 534 "MSRValue": "0x0200100491", 535 "Offcore": "1", 536 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 537 "SampleAfterValue": "100003", 538 "UMask": "0x1" 539 }, 540 { 541 "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", 542 "Counter": "0,1,2,3", 543 "CounterHTOff": "0,1,2,3", 544 "EventCode": "0xB7, 0xBB", 545 "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", 546 "MSRIndex": "0x1a6,0x1a7", 547 "MSRValue": "0x0080100491", 548 "Offcore": "1", 549 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 550 "SampleAfterValue": "100003", 551 "UMask": "0x1" 552 }, 553 { 554 "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 555 "Counter": "0,1,2,3", 556 "CounterHTOff": "0,1,2,3", 557 "EventCode": "0xB7, 0xBB", 558 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 559 "MSRIndex": "0x1a6,0x1a7", 560 "MSRValue": "0x3F80400491", 561 "Offcore": "1", 562 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 563 "SampleAfterValue": "100003", 564 "UMask": "0x1" 565 }, 566 { 567 "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 568 "Counter": "0,1,2,3", 569 "CounterHTOff": "0,1,2,3", 570 "EventCode": "0xB7, 0xBB", 571 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 572 "MSRIndex": "0x1a6,0x1a7", 573 "MSRValue": "0x0080400491", 574 "Offcore": "1", 575 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 576 "SampleAfterValue": "100003", 577 "UMask": "0x1" 578 }, 579 { 580 "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 581 "Counter": "0,1,2,3", 582 "CounterHTOff": "0,1,2,3", 583 "EventCode": "0xB7, 0xBB", 584 "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 585 "MSRIndex": "0x1a6,0x1a7", 586 "MSRValue": "0x0100400491", 587 "Offcore": "1", 588 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 589 "SampleAfterValue": "100003", 590 "UMask": "0x1" 591 }, 592 { 593 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 594 "Counter": "0,1,2,3", 595 "CounterHTOff": "0,1,2,3", 596 "EventCode": "0xB7, 0xBB", 597 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 598 "MSRIndex": "0x1a6,0x1a7", 599 "MSRValue": "0x3F80020491", 600 "Offcore": "1", 601 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 602 "SampleAfterValue": "100003", 603 "UMask": "0x1" 604 }, 605 { 606 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 607 "Counter": "0,1,2,3", 608 "CounterHTOff": "0,1,2,3", 609 "EventCode": "0xB7, 0xBB", 610 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 611 "MSRIndex": "0x1a6,0x1a7", 612 "MSRValue": "0x1000020491", 613 "Offcore": "1", 614 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 615 "SampleAfterValue": "100003", 616 "UMask": "0x1" 617 }, 618 { 619 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 620 "Counter": "0,1,2,3", 621 "CounterHTOff": "0,1,2,3", 622 "EventCode": "0xB7, 0xBB", 623 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 624 "MSRIndex": "0x1a6,0x1a7", 625 "MSRValue": "0x0800020491", 626 "Offcore": "1", 627 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 628 "SampleAfterValue": "100003", 629 "UMask": "0x1" 630 }, 631 { 632 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 633 "Counter": "0,1,2,3", 634 "CounterHTOff": "0,1,2,3", 635 "EventCode": "0xB7, 0xBB", 636 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 637 "MSRIndex": "0x1a6,0x1a7", 638 "MSRValue": "0x0400020491", 639 "Offcore": "1", 640 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 641 "SampleAfterValue": "100003", 642 "UMask": "0x1" 643 }, 644 { 645 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 646 "Counter": "0,1,2,3", 647 "CounterHTOff": "0,1,2,3", 648 "EventCode": "0xB7, 0xBB", 649 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 650 "MSRIndex": "0x1a6,0x1a7", 651 "MSRValue": "0x0100020491", 652 "Offcore": "1", 653 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 654 "SampleAfterValue": "100003", 655 "UMask": "0x1" 656 }, 657 { 658 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 659 "Counter": "0,1,2,3", 660 "CounterHTOff": "0,1,2,3", 661 "EventCode": "0xB7, 0xBB", 662 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 663 "MSRIndex": "0x1a6,0x1a7", 664 "MSRValue": "0x0200020491", 665 "Offcore": "1", 666 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 667 "SampleAfterValue": "100003", 668 "UMask": "0x1" 669 }, 670 { 671 "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 672 "Counter": "0,1,2,3", 673 "CounterHTOff": "0,1,2,3", 674 "EventCode": "0xB7, 0xBB", 675 "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 676 "MSRIndex": "0x1a6,0x1a7", 677 "MSRValue": "0x0080020491", 678 "Offcore": "1", 679 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 680 "SampleAfterValue": "100003", 681 "UMask": "0x1" 682 }, 683 { 684 "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.", 685 "Counter": "0,1,2,3", 686 "CounterHTOff": "0,1,2,3", 687 "EventCode": "0xB7, 0xBB", 688 "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", 689 "MSRIndex": "0x1a6,0x1a7", 690 "MSRValue": "0x0000010490", 691 "Offcore": "1", 692 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 693 "SampleAfterValue": "100003", 694 "UMask": "0x1" 695 }, 696 { 697 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", 698 "Counter": "0,1,2,3", 699 "CounterHTOff": "0,1,2,3", 700 "EventCode": "0xB7, 0xBB", 701 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", 702 "MSRIndex": "0x1a6,0x1a7", 703 "MSRValue": "0x3F803C0490", 704 "Offcore": "1", 705 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 706 "SampleAfterValue": "100003", 707 "UMask": "0x1" 708 }, 709 { 710 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", 711 "Counter": "0,1,2,3", 712 "CounterHTOff": "0,1,2,3", 713 "EventCode": "0xB7, 0xBB", 714 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", 715 "MSRIndex": "0x1a6,0x1a7", 716 "MSRValue": "0x10003C0490", 717 "Offcore": "1", 718 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 719 "SampleAfterValue": "100003", 720 "UMask": "0x1" 721 }, 722 { 723 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 724 "Counter": "0,1,2,3", 725 "CounterHTOff": "0,1,2,3", 726 "EventCode": "0xB7, 0xBB", 727 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 728 "MSRIndex": "0x1a6,0x1a7", 729 "MSRValue": "0x08003C0490", 730 "Offcore": "1", 731 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 732 "SampleAfterValue": "100003", 733 "UMask": "0x1" 734 }, 735 { 736 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 737 "Counter": "0,1,2,3", 738 "CounterHTOff": "0,1,2,3", 739 "EventCode": "0xB7, 0xBB", 740 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 741 "MSRIndex": "0x1a6,0x1a7", 742 "MSRValue": "0x04003C0490", 743 "Offcore": "1", 744 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 745 "SampleAfterValue": "100003", 746 "UMask": "0x1" 747 }, 748 { 749 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 750 "Counter": "0,1,2,3", 751 "CounterHTOff": "0,1,2,3", 752 "EventCode": "0xB7, 0xBB", 753 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 754 "MSRIndex": "0x1a6,0x1a7", 755 "MSRValue": "0x01003C0490", 756 "Offcore": "1", 757 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 758 "SampleAfterValue": "100003", 759 "UMask": "0x1" 760 }, 761 { 762 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 763 "Counter": "0,1,2,3", 764 "CounterHTOff": "0,1,2,3", 765 "EventCode": "0xB7, 0xBB", 766 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 767 "MSRIndex": "0x1a6,0x1a7", 768 "MSRValue": "0x08007C0490", 769 "Offcore": "1", 770 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 771 "SampleAfterValue": "100003", 772 "UMask": "0x1" 773 }, 774 { 775 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", 776 "Counter": "0,1,2,3", 777 "CounterHTOff": "0,1,2,3", 778 "EventCode": "0xB7, 0xBB", 779 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", 780 "MSRIndex": "0x1a6,0x1a7", 781 "MSRValue": "0x02003C0490", 782 "Offcore": "1", 783 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 784 "SampleAfterValue": "100003", 785 "UMask": "0x1" 786 }, 787 { 788 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", 789 "Counter": "0,1,2,3", 790 "CounterHTOff": "0,1,2,3", 791 "EventCode": "0xB7, 0xBB", 792 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", 793 "MSRIndex": "0x1a6,0x1a7", 794 "MSRValue": "0x00803C0490", 795 "Offcore": "1", 796 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 797 "SampleAfterValue": "100003", 798 "UMask": "0x1" 799 }, 800 { 801 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", 802 "Counter": "0,1,2,3", 803 "CounterHTOff": "0,1,2,3", 804 "EventCode": "0xB7, 0xBB", 805 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", 806 "MSRIndex": "0x1a6,0x1a7", 807 "MSRValue": "0x3F80080490", 808 "Offcore": "1", 809 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 810 "SampleAfterValue": "100003", 811 "UMask": "0x1" 812 }, 813 { 814 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 815 "Counter": "0,1,2,3", 816 "CounterHTOff": "0,1,2,3", 817 "EventCode": "0xB7, 0xBB", 818 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 819 "MSRIndex": "0x1a6,0x1a7", 820 "MSRValue": "0x1000080490", 821 "Offcore": "1", 822 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 823 "SampleAfterValue": "100003", 824 "UMask": "0x1" 825 }, 826 { 827 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 828 "Counter": "0,1,2,3", 829 "CounterHTOff": "0,1,2,3", 830 "EventCode": "0xB7, 0xBB", 831 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 832 "MSRIndex": "0x1a6,0x1a7", 833 "MSRValue": "0x0800080490", 834 "Offcore": "1", 835 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 836 "SampleAfterValue": "100003", 837 "UMask": "0x1" 838 }, 839 { 840 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 841 "Counter": "0,1,2,3", 842 "CounterHTOff": "0,1,2,3", 843 "EventCode": "0xB7, 0xBB", 844 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 845 "MSRIndex": "0x1a6,0x1a7", 846 "MSRValue": "0x0400080490", 847 "Offcore": "1", 848 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 849 "SampleAfterValue": "100003", 850 "UMask": "0x1" 851 }, 852 { 853 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 854 "Counter": "0,1,2,3", 855 "CounterHTOff": "0,1,2,3", 856 "EventCode": "0xB7, 0xBB", 857 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 858 "MSRIndex": "0x1a6,0x1a7", 859 "MSRValue": "0x0100080490", 860 "Offcore": "1", 861 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 862 "SampleAfterValue": "100003", 863 "UMask": "0x1" 864 }, 865 { 866 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", 867 "Counter": "0,1,2,3", 868 "CounterHTOff": "0,1,2,3", 869 "EventCode": "0xB7, 0xBB", 870 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", 871 "MSRIndex": "0x1a6,0x1a7", 872 "MSRValue": "0x0200080490", 873 "Offcore": "1", 874 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 875 "SampleAfterValue": "100003", 876 "UMask": "0x1" 877 }, 878 { 879 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", 880 "Counter": "0,1,2,3", 881 "CounterHTOff": "0,1,2,3", 882 "EventCode": "0xB7, 0xBB", 883 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", 884 "MSRIndex": "0x1a6,0x1a7", 885 "MSRValue": "0x0080080490", 886 "Offcore": "1", 887 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 888 "SampleAfterValue": "100003", 889 "UMask": "0x1" 890 }, 891 { 892 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", 893 "Counter": "0,1,2,3", 894 "CounterHTOff": "0,1,2,3", 895 "EventCode": "0xB7, 0xBB", 896 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", 897 "MSRIndex": "0x1a6,0x1a7", 898 "MSRValue": "0x3F80200490", 899 "Offcore": "1", 900 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 901 "SampleAfterValue": "100003", 902 "UMask": "0x1" 903 }, 904 { 905 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 906 "Counter": "0,1,2,3", 907 "CounterHTOff": "0,1,2,3", 908 "EventCode": "0xB7, 0xBB", 909 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 910 "MSRIndex": "0x1a6,0x1a7", 911 "MSRValue": "0x1000200490", 912 "Offcore": "1", 913 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 914 "SampleAfterValue": "100003", 915 "UMask": "0x1" 916 }, 917 { 918 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 919 "Counter": "0,1,2,3", 920 "CounterHTOff": "0,1,2,3", 921 "EventCode": "0xB7, 0xBB", 922 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 923 "MSRIndex": "0x1a6,0x1a7", 924 "MSRValue": "0x0800200490", 925 "Offcore": "1", 926 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 927 "SampleAfterValue": "100003", 928 "UMask": "0x1" 929 }, 930 { 931 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 932 "Counter": "0,1,2,3", 933 "CounterHTOff": "0,1,2,3", 934 "EventCode": "0xB7, 0xBB", 935 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 936 "MSRIndex": "0x1a6,0x1a7", 937 "MSRValue": "0x0400200490", 938 "Offcore": "1", 939 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 940 "SampleAfterValue": "100003", 941 "UMask": "0x1" 942 }, 943 { 944 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 945 "Counter": "0,1,2,3", 946 "CounterHTOff": "0,1,2,3", 947 "EventCode": "0xB7, 0xBB", 948 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 949 "MSRIndex": "0x1a6,0x1a7", 950 "MSRValue": "0x0100200490", 951 "Offcore": "1", 952 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 953 "SampleAfterValue": "100003", 954 "UMask": "0x1" 955 }, 956 { 957 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", 958 "Counter": "0,1,2,3", 959 "CounterHTOff": "0,1,2,3", 960 "EventCode": "0xB7, 0xBB", 961 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", 962 "MSRIndex": "0x1a6,0x1a7", 963 "MSRValue": "0x0200200490", 964 "Offcore": "1", 965 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 966 "SampleAfterValue": "100003", 967 "UMask": "0x1" 968 }, 969 { 970 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", 971 "Counter": "0,1,2,3", 972 "CounterHTOff": "0,1,2,3", 973 "EventCode": "0xB7, 0xBB", 974 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", 975 "MSRIndex": "0x1a6,0x1a7", 976 "MSRValue": "0x0080200490", 977 "Offcore": "1", 978 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 979 "SampleAfterValue": "100003", 980 "UMask": "0x1" 981 }, 982 { 983 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", 984 "Counter": "0,1,2,3", 985 "CounterHTOff": "0,1,2,3", 986 "EventCode": "0xB7, 0xBB", 987 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", 988 "MSRIndex": "0x1a6,0x1a7", 989 "MSRValue": "0x3F80040490", 990 "Offcore": "1", 991 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 992 "SampleAfterValue": "100003", 993 "UMask": "0x1" 994 }, 995 { 996 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 997 "Counter": "0,1,2,3", 998 "CounterHTOff": "0,1,2,3", 999 "EventCode": "0xB7, 0xBB", 1000 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 1001 "MSRIndex": "0x1a6,0x1a7", 1002 "MSRValue": "0x1000040490", 1003 "Offcore": "1", 1004 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1005 "SampleAfterValue": "100003", 1006 "UMask": "0x1" 1007 }, 1008 { 1009 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 1010 "Counter": "0,1,2,3", 1011 "CounterHTOff": "0,1,2,3", 1012 "EventCode": "0xB7, 0xBB", 1013 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 1014 "MSRIndex": "0x1a6,0x1a7", 1015 "MSRValue": "0x0800040490", 1016 "Offcore": "1", 1017 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1018 "SampleAfterValue": "100003", 1019 "UMask": "0x1" 1020 }, 1021 { 1022 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1023 "Counter": "0,1,2,3", 1024 "CounterHTOff": "0,1,2,3", 1025 "EventCode": "0xB7, 0xBB", 1026 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1027 "MSRIndex": "0x1a6,0x1a7", 1028 "MSRValue": "0x0400040490", 1029 "Offcore": "1", 1030 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1031 "SampleAfterValue": "100003", 1032 "UMask": "0x1" 1033 }, 1034 { 1035 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 1036 "Counter": "0,1,2,3", 1037 "CounterHTOff": "0,1,2,3", 1038 "EventCode": "0xB7, 0xBB", 1039 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 1040 "MSRIndex": "0x1a6,0x1a7", 1041 "MSRValue": "0x0100040490", 1042 "Offcore": "1", 1043 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1044 "SampleAfterValue": "100003", 1045 "UMask": "0x1" 1046 }, 1047 { 1048 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", 1049 "Counter": "0,1,2,3", 1050 "CounterHTOff": "0,1,2,3", 1051 "EventCode": "0xB7, 0xBB", 1052 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", 1053 "MSRIndex": "0x1a6,0x1a7", 1054 "MSRValue": "0x0200040490", 1055 "Offcore": "1", 1056 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1057 "SampleAfterValue": "100003", 1058 "UMask": "0x1" 1059 }, 1060 { 1061 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", 1062 "Counter": "0,1,2,3", 1063 "CounterHTOff": "0,1,2,3", 1064 "EventCode": "0xB7, 0xBB", 1065 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", 1066 "MSRIndex": "0x1a6,0x1a7", 1067 "MSRValue": "0x0080040490", 1068 "Offcore": "1", 1069 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1070 "SampleAfterValue": "100003", 1071 "UMask": "0x1" 1072 }, 1073 { 1074 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", 1075 "Counter": "0,1,2,3", 1076 "CounterHTOff": "0,1,2,3", 1077 "EventCode": "0xB7, 0xBB", 1078 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", 1079 "MSRIndex": "0x1a6,0x1a7", 1080 "MSRValue": "0x3F80100490", 1081 "Offcore": "1", 1082 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1083 "SampleAfterValue": "100003", 1084 "UMask": "0x1" 1085 }, 1086 { 1087 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 1088 "Counter": "0,1,2,3", 1089 "CounterHTOff": "0,1,2,3", 1090 "EventCode": "0xB7, 0xBB", 1091 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 1092 "MSRIndex": "0x1a6,0x1a7", 1093 "MSRValue": "0x1000100490", 1094 "Offcore": "1", 1095 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1096 "SampleAfterValue": "100003", 1097 "UMask": "0x1" 1098 }, 1099 { 1100 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 1101 "Counter": "0,1,2,3", 1102 "CounterHTOff": "0,1,2,3", 1103 "EventCode": "0xB7, 0xBB", 1104 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 1105 "MSRIndex": "0x1a6,0x1a7", 1106 "MSRValue": "0x0800100490", 1107 "Offcore": "1", 1108 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1109 "SampleAfterValue": "100003", 1110 "UMask": "0x1" 1111 }, 1112 { 1113 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1114 "Counter": "0,1,2,3", 1115 "CounterHTOff": "0,1,2,3", 1116 "EventCode": "0xB7, 0xBB", 1117 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1118 "MSRIndex": "0x1a6,0x1a7", 1119 "MSRValue": "0x0400100490", 1120 "Offcore": "1", 1121 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1122 "SampleAfterValue": "100003", 1123 "UMask": "0x1" 1124 }, 1125 { 1126 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 1127 "Counter": "0,1,2,3", 1128 "CounterHTOff": "0,1,2,3", 1129 "EventCode": "0xB7, 0xBB", 1130 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 1131 "MSRIndex": "0x1a6,0x1a7", 1132 "MSRValue": "0x0100100490", 1133 "Offcore": "1", 1134 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1135 "SampleAfterValue": "100003", 1136 "UMask": "0x1" 1137 }, 1138 { 1139 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", 1140 "Counter": "0,1,2,3", 1141 "CounterHTOff": "0,1,2,3", 1142 "EventCode": "0xB7, 0xBB", 1143 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", 1144 "MSRIndex": "0x1a6,0x1a7", 1145 "MSRValue": "0x0200100490", 1146 "Offcore": "1", 1147 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1148 "SampleAfterValue": "100003", 1149 "UMask": "0x1" 1150 }, 1151 { 1152 "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", 1153 "Counter": "0,1,2,3", 1154 "CounterHTOff": "0,1,2,3", 1155 "EventCode": "0xB7, 0xBB", 1156 "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", 1157 "MSRIndex": "0x1a6,0x1a7", 1158 "MSRValue": "0x0080100490", 1159 "Offcore": "1", 1160 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1161 "SampleAfterValue": "100003", 1162 "UMask": "0x1" 1163 }, 1164 { 1165 "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 1166 "Counter": "0,1,2,3", 1167 "CounterHTOff": "0,1,2,3", 1168 "EventCode": "0xB7, 0xBB", 1169 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 1170 "MSRIndex": "0x1a6,0x1a7", 1171 "MSRValue": "0x3F80400490", 1172 "Offcore": "1", 1173 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1174 "SampleAfterValue": "100003", 1175 "UMask": "0x1" 1176 }, 1177 { 1178 "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1179 "Counter": "0,1,2,3", 1180 "CounterHTOff": "0,1,2,3", 1181 "EventCode": "0xB7, 0xBB", 1182 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1183 "MSRIndex": "0x1a6,0x1a7", 1184 "MSRValue": "0x0080400490", 1185 "Offcore": "1", 1186 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1187 "SampleAfterValue": "100003", 1188 "UMask": "0x1" 1189 }, 1190 { 1191 "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1192 "Counter": "0,1,2,3", 1193 "CounterHTOff": "0,1,2,3", 1194 "EventCode": "0xB7, 0xBB", 1195 "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1196 "MSRIndex": "0x1a6,0x1a7", 1197 "MSRValue": "0x0100400490", 1198 "Offcore": "1", 1199 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1200 "SampleAfterValue": "100003", 1201 "UMask": "0x1" 1202 }, 1203 { 1204 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 1205 "Counter": "0,1,2,3", 1206 "CounterHTOff": "0,1,2,3", 1207 "EventCode": "0xB7, 0xBB", 1208 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 1209 "MSRIndex": "0x1a6,0x1a7", 1210 "MSRValue": "0x3F80020490", 1211 "Offcore": "1", 1212 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1213 "SampleAfterValue": "100003", 1214 "UMask": "0x1" 1215 }, 1216 { 1217 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 1218 "Counter": "0,1,2,3", 1219 "CounterHTOff": "0,1,2,3", 1220 "EventCode": "0xB7, 0xBB", 1221 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 1222 "MSRIndex": "0x1a6,0x1a7", 1223 "MSRValue": "0x1000020490", 1224 "Offcore": "1", 1225 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1226 "SampleAfterValue": "100003", 1227 "UMask": "0x1" 1228 }, 1229 { 1230 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1231 "Counter": "0,1,2,3", 1232 "CounterHTOff": "0,1,2,3", 1233 "EventCode": "0xB7, 0xBB", 1234 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1235 "MSRIndex": "0x1a6,0x1a7", 1236 "MSRValue": "0x0800020490", 1237 "Offcore": "1", 1238 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1239 "SampleAfterValue": "100003", 1240 "UMask": "0x1" 1241 }, 1242 { 1243 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1244 "Counter": "0,1,2,3", 1245 "CounterHTOff": "0,1,2,3", 1246 "EventCode": "0xB7, 0xBB", 1247 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1248 "MSRIndex": "0x1a6,0x1a7", 1249 "MSRValue": "0x0400020490", 1250 "Offcore": "1", 1251 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1252 "SampleAfterValue": "100003", 1253 "UMask": "0x1" 1254 }, 1255 { 1256 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1257 "Counter": "0,1,2,3", 1258 "CounterHTOff": "0,1,2,3", 1259 "EventCode": "0xB7, 0xBB", 1260 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1261 "MSRIndex": "0x1a6,0x1a7", 1262 "MSRValue": "0x0100020490", 1263 "Offcore": "1", 1264 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1265 "SampleAfterValue": "100003", 1266 "UMask": "0x1" 1267 }, 1268 { 1269 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 1270 "Counter": "0,1,2,3", 1271 "CounterHTOff": "0,1,2,3", 1272 "EventCode": "0xB7, 0xBB", 1273 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 1274 "MSRIndex": "0x1a6,0x1a7", 1275 "MSRValue": "0x0200020490", 1276 "Offcore": "1", 1277 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1278 "SampleAfterValue": "100003", 1279 "UMask": "0x1" 1280 }, 1281 { 1282 "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 1283 "Counter": "0,1,2,3", 1284 "CounterHTOff": "0,1,2,3", 1285 "EventCode": "0xB7, 0xBB", 1286 "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 1287 "MSRIndex": "0x1a6,0x1a7", 1288 "MSRValue": "0x0080020490", 1289 "Offcore": "1", 1290 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1291 "SampleAfterValue": "100003", 1292 "UMask": "0x1" 1293 }, 1294 { 1295 "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.", 1296 "Counter": "0,1,2,3", 1297 "CounterHTOff": "0,1,2,3", 1298 "EventCode": "0xB7, 0xBB", 1299 "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", 1300 "MSRIndex": "0x1a6,0x1a7", 1301 "MSRValue": "0x0000010120", 1302 "Offcore": "1", 1303 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1304 "SampleAfterValue": "100003", 1305 "UMask": "0x1" 1306 }, 1307 { 1308 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", 1309 "Counter": "0,1,2,3", 1310 "CounterHTOff": "0,1,2,3", 1311 "EventCode": "0xB7, 0xBB", 1312 "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", 1313 "MSRIndex": "0x1a6,0x1a7", 1314 "MSRValue": "0x3F803C0120", 1315 "Offcore": "1", 1316 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1317 "SampleAfterValue": "100003", 1318 "UMask": "0x1" 1319 }, 1320 { 1321 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", 1322 "Counter": "0,1,2,3", 1323 "CounterHTOff": "0,1,2,3", 1324 "EventCode": "0xB7, 0xBB", 1325 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", 1326 "MSRIndex": "0x1a6,0x1a7", 1327 "MSRValue": "0x10003C0120", 1328 "Offcore": "1", 1329 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1330 "SampleAfterValue": "100003", 1331 "UMask": "0x1" 1332 }, 1333 { 1334 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 1335 "Counter": "0,1,2,3", 1336 "CounterHTOff": "0,1,2,3", 1337 "EventCode": "0xB7, 0xBB", 1338 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 1339 "MSRIndex": "0x1a6,0x1a7", 1340 "MSRValue": "0x08003C0120", 1341 "Offcore": "1", 1342 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1343 "SampleAfterValue": "100003", 1344 "UMask": "0x1" 1345 }, 1346 { 1347 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1348 "Counter": "0,1,2,3", 1349 "CounterHTOff": "0,1,2,3", 1350 "EventCode": "0xB7, 0xBB", 1351 "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1352 "MSRIndex": "0x1a6,0x1a7", 1353 "MSRValue": "0x04003C0120", 1354 "Offcore": "1", 1355 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1356 "SampleAfterValue": "100003", 1357 "UMask": "0x1" 1358 }, 1359 { 1360 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", 1361 "Counter": "0,1,2,3", 1362 "CounterHTOff": "0,1,2,3", 1363 "EventCode": "0xB7, 0xBB", 1364 "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", 1365 "MSRIndex": "0x1a6,0x1a7", 1366 "MSRValue": "0x01003C0120", 1367 "Offcore": "1", 1368 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1369 "SampleAfterValue": "100003", 1370 "UMask": "0x1" 1371 }, 1372 { 1373 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 1374 "Counter": "0,1,2,3", 1375 "CounterHTOff": "0,1,2,3", 1376 "EventCode": "0xB7, 0xBB", 1377 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 1378 "MSRIndex": "0x1a6,0x1a7", 1379 "MSRValue": "0x08007C0120", 1380 "Offcore": "1", 1381 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1382 "SampleAfterValue": "100003", 1383 "UMask": "0x1" 1384 }, 1385 { 1386 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", 1387 "Counter": "0,1,2,3", 1388 "CounterHTOff": "0,1,2,3", 1389 "EventCode": "0xB7, 0xBB", 1390 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", 1391 "MSRIndex": "0x1a6,0x1a7", 1392 "MSRValue": "0x02003C0120", 1393 "Offcore": "1", 1394 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1395 "SampleAfterValue": "100003", 1396 "UMask": "0x1" 1397 }, 1398 { 1399 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", 1400 "Counter": "0,1,2,3", 1401 "CounterHTOff": "0,1,2,3", 1402 "EventCode": "0xB7, 0xBB", 1403 "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", 1404 "MSRIndex": "0x1a6,0x1a7", 1405 "MSRValue": "0x00803C0120", 1406 "Offcore": "1", 1407 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1408 "SampleAfterValue": "100003", 1409 "UMask": "0x1" 1410 }, 1411 { 1412 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", 1413 "Counter": "0,1,2,3", 1414 "CounterHTOff": "0,1,2,3", 1415 "EventCode": "0xB7, 0xBB", 1416 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", 1417 "MSRIndex": "0x1a6,0x1a7", 1418 "MSRValue": "0x3F80080120", 1419 "Offcore": "1", 1420 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1421 "SampleAfterValue": "100003", 1422 "UMask": "0x1" 1423 }, 1424 { 1425 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", 1426 "Counter": "0,1,2,3", 1427 "CounterHTOff": "0,1,2,3", 1428 "EventCode": "0xB7, 0xBB", 1429 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", 1430 "MSRIndex": "0x1a6,0x1a7", 1431 "MSRValue": "0x1000080120", 1432 "Offcore": "1", 1433 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1434 "SampleAfterValue": "100003", 1435 "UMask": "0x1" 1436 }, 1437 { 1438 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 1439 "Counter": "0,1,2,3", 1440 "CounterHTOff": "0,1,2,3", 1441 "EventCode": "0xB7, 0xBB", 1442 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 1443 "MSRIndex": "0x1a6,0x1a7", 1444 "MSRValue": "0x0800080120", 1445 "Offcore": "1", 1446 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1447 "SampleAfterValue": "100003", 1448 "UMask": "0x1" 1449 }, 1450 { 1451 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 1452 "Counter": "0,1,2,3", 1453 "CounterHTOff": "0,1,2,3", 1454 "EventCode": "0xB7, 0xBB", 1455 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 1456 "MSRIndex": "0x1a6,0x1a7", 1457 "MSRValue": "0x0400080120", 1458 "Offcore": "1", 1459 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1460 "SampleAfterValue": "100003", 1461 "UMask": "0x1" 1462 }, 1463 { 1464 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 1465 "Counter": "0,1,2,3", 1466 "CounterHTOff": "0,1,2,3", 1467 "EventCode": "0xB7, 0xBB", 1468 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 1469 "MSRIndex": "0x1a6,0x1a7", 1470 "MSRValue": "0x0100080120", 1471 "Offcore": "1", 1472 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1473 "SampleAfterValue": "100003", 1474 "UMask": "0x1" 1475 }, 1476 { 1477 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", 1478 "Counter": "0,1,2,3", 1479 "CounterHTOff": "0,1,2,3", 1480 "EventCode": "0xB7, 0xBB", 1481 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", 1482 "MSRIndex": "0x1a6,0x1a7", 1483 "MSRValue": "0x0200080120", 1484 "Offcore": "1", 1485 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1486 "SampleAfterValue": "100003", 1487 "UMask": "0x1" 1488 }, 1489 { 1490 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", 1491 "Counter": "0,1,2,3", 1492 "CounterHTOff": "0,1,2,3", 1493 "EventCode": "0xB7, 0xBB", 1494 "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", 1495 "MSRIndex": "0x1a6,0x1a7", 1496 "MSRValue": "0x0080080120", 1497 "Offcore": "1", 1498 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1499 "SampleAfterValue": "100003", 1500 "UMask": "0x1" 1501 }, 1502 { 1503 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", 1504 "Counter": "0,1,2,3", 1505 "CounterHTOff": "0,1,2,3", 1506 "EventCode": "0xB7, 0xBB", 1507 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", 1508 "MSRIndex": "0x1a6,0x1a7", 1509 "MSRValue": "0x3F80200120", 1510 "Offcore": "1", 1511 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1512 "SampleAfterValue": "100003", 1513 "UMask": "0x1" 1514 }, 1515 { 1516 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", 1517 "Counter": "0,1,2,3", 1518 "CounterHTOff": "0,1,2,3", 1519 "EventCode": "0xB7, 0xBB", 1520 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", 1521 "MSRIndex": "0x1a6,0x1a7", 1522 "MSRValue": "0x1000200120", 1523 "Offcore": "1", 1524 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1525 "SampleAfterValue": "100003", 1526 "UMask": "0x1" 1527 }, 1528 { 1529 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 1530 "Counter": "0,1,2,3", 1531 "CounterHTOff": "0,1,2,3", 1532 "EventCode": "0xB7, 0xBB", 1533 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 1534 "MSRIndex": "0x1a6,0x1a7", 1535 "MSRValue": "0x0800200120", 1536 "Offcore": "1", 1537 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1538 "SampleAfterValue": "100003", 1539 "UMask": "0x1" 1540 }, 1541 { 1542 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1543 "Counter": "0,1,2,3", 1544 "CounterHTOff": "0,1,2,3", 1545 "EventCode": "0xB7, 0xBB", 1546 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 1547 "MSRIndex": "0x1a6,0x1a7", 1548 "MSRValue": "0x0400200120", 1549 "Offcore": "1", 1550 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1551 "SampleAfterValue": "100003", 1552 "UMask": "0x1" 1553 }, 1554 { 1555 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 1556 "Counter": "0,1,2,3", 1557 "CounterHTOff": "0,1,2,3", 1558 "EventCode": "0xB7, 0xBB", 1559 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 1560 "MSRIndex": "0x1a6,0x1a7", 1561 "MSRValue": "0x0100200120", 1562 "Offcore": "1", 1563 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1564 "SampleAfterValue": "100003", 1565 "UMask": "0x1" 1566 }, 1567 { 1568 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", 1569 "Counter": "0,1,2,3", 1570 "CounterHTOff": "0,1,2,3", 1571 "EventCode": "0xB7, 0xBB", 1572 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", 1573 "MSRIndex": "0x1a6,0x1a7", 1574 "MSRValue": "0x0200200120", 1575 "Offcore": "1", 1576 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1577 "SampleAfterValue": "100003", 1578 "UMask": "0x1" 1579 }, 1580 { 1581 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", 1582 "Counter": "0,1,2,3", 1583 "CounterHTOff": "0,1,2,3", 1584 "EventCode": "0xB7, 0xBB", 1585 "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", 1586 "MSRIndex": "0x1a6,0x1a7", 1587 "MSRValue": "0x0080200120", 1588 "Offcore": "1", 1589 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1590 "SampleAfterValue": "100003", 1591 "UMask": "0x1" 1592 }, 1593 { 1594 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", 1595 "Counter": "0,1,2,3", 1596 "CounterHTOff": "0,1,2,3", 1597 "EventCode": "0xB7, 0xBB", 1598 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", 1599 "MSRIndex": "0x1a6,0x1a7", 1600 "MSRValue": "0x3F80040120", 1601 "Offcore": "1", 1602 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1603 "SampleAfterValue": "100003", 1604 "UMask": "0x1" 1605 }, 1606 { 1607 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", 1608 "Counter": "0,1,2,3", 1609 "CounterHTOff": "0,1,2,3", 1610 "EventCode": "0xB7, 0xBB", 1611 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", 1612 "MSRIndex": "0x1a6,0x1a7", 1613 "MSRValue": "0x1000040120", 1614 "Offcore": "1", 1615 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1616 "SampleAfterValue": "100003", 1617 "UMask": "0x1" 1618 }, 1619 { 1620 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 1621 "Counter": "0,1,2,3", 1622 "CounterHTOff": "0,1,2,3", 1623 "EventCode": "0xB7, 0xBB", 1624 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 1625 "MSRIndex": "0x1a6,0x1a7", 1626 "MSRValue": "0x0800040120", 1627 "Offcore": "1", 1628 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1629 "SampleAfterValue": "100003", 1630 "UMask": "0x1" 1631 }, 1632 { 1633 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1634 "Counter": "0,1,2,3", 1635 "CounterHTOff": "0,1,2,3", 1636 "EventCode": "0xB7, 0xBB", 1637 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 1638 "MSRIndex": "0x1a6,0x1a7", 1639 "MSRValue": "0x0400040120", 1640 "Offcore": "1", 1641 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1642 "SampleAfterValue": "100003", 1643 "UMask": "0x1" 1644 }, 1645 { 1646 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 1647 "Counter": "0,1,2,3", 1648 "CounterHTOff": "0,1,2,3", 1649 "EventCode": "0xB7, 0xBB", 1650 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 1651 "MSRIndex": "0x1a6,0x1a7", 1652 "MSRValue": "0x0100040120", 1653 "Offcore": "1", 1654 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1655 "SampleAfterValue": "100003", 1656 "UMask": "0x1" 1657 }, 1658 { 1659 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", 1660 "Counter": "0,1,2,3", 1661 "CounterHTOff": "0,1,2,3", 1662 "EventCode": "0xB7, 0xBB", 1663 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", 1664 "MSRIndex": "0x1a6,0x1a7", 1665 "MSRValue": "0x0200040120", 1666 "Offcore": "1", 1667 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1668 "SampleAfterValue": "100003", 1669 "UMask": "0x1" 1670 }, 1671 { 1672 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", 1673 "Counter": "0,1,2,3", 1674 "CounterHTOff": "0,1,2,3", 1675 "EventCode": "0xB7, 0xBB", 1676 "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", 1677 "MSRIndex": "0x1a6,0x1a7", 1678 "MSRValue": "0x0080040120", 1679 "Offcore": "1", 1680 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1681 "SampleAfterValue": "100003", 1682 "UMask": "0x1" 1683 }, 1684 { 1685 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", 1686 "Counter": "0,1,2,3", 1687 "CounterHTOff": "0,1,2,3", 1688 "EventCode": "0xB7, 0xBB", 1689 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", 1690 "MSRIndex": "0x1a6,0x1a7", 1691 "MSRValue": "0x3F80100120", 1692 "Offcore": "1", 1693 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1694 "SampleAfterValue": "100003", 1695 "UMask": "0x1" 1696 }, 1697 { 1698 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", 1699 "Counter": "0,1,2,3", 1700 "CounterHTOff": "0,1,2,3", 1701 "EventCode": "0xB7, 0xBB", 1702 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", 1703 "MSRIndex": "0x1a6,0x1a7", 1704 "MSRValue": "0x1000100120", 1705 "Offcore": "1", 1706 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1707 "SampleAfterValue": "100003", 1708 "UMask": "0x1" 1709 }, 1710 { 1711 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 1712 "Counter": "0,1,2,3", 1713 "CounterHTOff": "0,1,2,3", 1714 "EventCode": "0xB7, 0xBB", 1715 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 1716 "MSRIndex": "0x1a6,0x1a7", 1717 "MSRValue": "0x0800100120", 1718 "Offcore": "1", 1719 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1720 "SampleAfterValue": "100003", 1721 "UMask": "0x1" 1722 }, 1723 { 1724 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1725 "Counter": "0,1,2,3", 1726 "CounterHTOff": "0,1,2,3", 1727 "EventCode": "0xB7, 0xBB", 1728 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 1729 "MSRIndex": "0x1a6,0x1a7", 1730 "MSRValue": "0x0400100120", 1731 "Offcore": "1", 1732 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1733 "SampleAfterValue": "100003", 1734 "UMask": "0x1" 1735 }, 1736 { 1737 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 1738 "Counter": "0,1,2,3", 1739 "CounterHTOff": "0,1,2,3", 1740 "EventCode": "0xB7, 0xBB", 1741 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 1742 "MSRIndex": "0x1a6,0x1a7", 1743 "MSRValue": "0x0100100120", 1744 "Offcore": "1", 1745 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1746 "SampleAfterValue": "100003", 1747 "UMask": "0x1" 1748 }, 1749 { 1750 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", 1751 "Counter": "0,1,2,3", 1752 "CounterHTOff": "0,1,2,3", 1753 "EventCode": "0xB7, 0xBB", 1754 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", 1755 "MSRIndex": "0x1a6,0x1a7", 1756 "MSRValue": "0x0200100120", 1757 "Offcore": "1", 1758 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1759 "SampleAfterValue": "100003", 1760 "UMask": "0x1" 1761 }, 1762 { 1763 "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", 1764 "Counter": "0,1,2,3", 1765 "CounterHTOff": "0,1,2,3", 1766 "EventCode": "0xB7, 0xBB", 1767 "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", 1768 "MSRIndex": "0x1a6,0x1a7", 1769 "MSRValue": "0x0080100120", 1770 "Offcore": "1", 1771 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1772 "SampleAfterValue": "100003", 1773 "UMask": "0x1" 1774 }, 1775 { 1776 "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 1777 "Counter": "0,1,2,3", 1778 "CounterHTOff": "0,1,2,3", 1779 "EventCode": "0xB7, 0xBB", 1780 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 1781 "MSRIndex": "0x1a6,0x1a7", 1782 "MSRValue": "0x3F80400120", 1783 "Offcore": "1", 1784 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1785 "SampleAfterValue": "100003", 1786 "UMask": "0x1" 1787 }, 1788 { 1789 "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1790 "Counter": "0,1,2,3", 1791 "CounterHTOff": "0,1,2,3", 1792 "EventCode": "0xB7, 0xBB", 1793 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 1794 "MSRIndex": "0x1a6,0x1a7", 1795 "MSRValue": "0x0080400120", 1796 "Offcore": "1", 1797 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1798 "SampleAfterValue": "100003", 1799 "UMask": "0x1" 1800 }, 1801 { 1802 "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1803 "Counter": "0,1,2,3", 1804 "CounterHTOff": "0,1,2,3", 1805 "EventCode": "0xB7, 0xBB", 1806 "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 1807 "MSRIndex": "0x1a6,0x1a7", 1808 "MSRValue": "0x0100400120", 1809 "Offcore": "1", 1810 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1811 "SampleAfterValue": "100003", 1812 "UMask": "0x1" 1813 }, 1814 { 1815 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", 1816 "Counter": "0,1,2,3", 1817 "CounterHTOff": "0,1,2,3", 1818 "EventCode": "0xB7, 0xBB", 1819 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", 1820 "MSRIndex": "0x1a6,0x1a7", 1821 "MSRValue": "0x3F80020120", 1822 "Offcore": "1", 1823 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1824 "SampleAfterValue": "100003", 1825 "UMask": "0x1" 1826 }, 1827 { 1828 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 1829 "Counter": "0,1,2,3", 1830 "CounterHTOff": "0,1,2,3", 1831 "EventCode": "0xB7, 0xBB", 1832 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 1833 "MSRIndex": "0x1a6,0x1a7", 1834 "MSRValue": "0x1000020120", 1835 "Offcore": "1", 1836 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1837 "SampleAfterValue": "100003", 1838 "UMask": "0x1" 1839 }, 1840 { 1841 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1842 "Counter": "0,1,2,3", 1843 "CounterHTOff": "0,1,2,3", 1844 "EventCode": "0xB7, 0xBB", 1845 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 1846 "MSRIndex": "0x1a6,0x1a7", 1847 "MSRValue": "0x0800020120", 1848 "Offcore": "1", 1849 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1850 "SampleAfterValue": "100003", 1851 "UMask": "0x1" 1852 }, 1853 { 1854 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1855 "Counter": "0,1,2,3", 1856 "CounterHTOff": "0,1,2,3", 1857 "EventCode": "0xB7, 0xBB", 1858 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 1859 "MSRIndex": "0x1a6,0x1a7", 1860 "MSRValue": "0x0400020120", 1861 "Offcore": "1", 1862 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1863 "SampleAfterValue": "100003", 1864 "UMask": "0x1" 1865 }, 1866 { 1867 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1868 "Counter": "0,1,2,3", 1869 "CounterHTOff": "0,1,2,3", 1870 "EventCode": "0xB7, 0xBB", 1871 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 1872 "MSRIndex": "0x1a6,0x1a7", 1873 "MSRValue": "0x0100020120", 1874 "Offcore": "1", 1875 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1876 "SampleAfterValue": "100003", 1877 "UMask": "0x1" 1878 }, 1879 { 1880 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", 1881 "Counter": "0,1,2,3", 1882 "CounterHTOff": "0,1,2,3", 1883 "EventCode": "0xB7, 0xBB", 1884 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", 1885 "MSRIndex": "0x1a6,0x1a7", 1886 "MSRValue": "0x0200020120", 1887 "Offcore": "1", 1888 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1889 "SampleAfterValue": "100003", 1890 "UMask": "0x1" 1891 }, 1892 { 1893 "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", 1894 "Counter": "0,1,2,3", 1895 "CounterHTOff": "0,1,2,3", 1896 "EventCode": "0xB7, 0xBB", 1897 "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", 1898 "MSRIndex": "0x1a6,0x1a7", 1899 "MSRValue": "0x0080020120", 1900 "Offcore": "1", 1901 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1902 "SampleAfterValue": "100003", 1903 "UMask": "0x1" 1904 }, 1905 { 1906 "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.", 1907 "Counter": "0,1,2,3", 1908 "CounterHTOff": "0,1,2,3", 1909 "EventCode": "0xB7, 0xBB", 1910 "EventName": "OCR.ALL_READS.ANY_RESPONSE", 1911 "MSRIndex": "0x1a6,0x1a7", 1912 "MSRValue": "0x00000107F7", 1913 "Offcore": "1", 1914 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1915 "SampleAfterValue": "100003", 1916 "UMask": "0x1" 1917 }, 1918 { 1919 "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", 1920 "Counter": "0,1,2,3", 1921 "CounterHTOff": "0,1,2,3", 1922 "EventCode": "0xB7, 0xBB", 1923 "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", 1924 "MSRIndex": "0x1a6,0x1a7", 1925 "MSRValue": "0x3F803C07F7", 1926 "Offcore": "1", 1927 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1928 "SampleAfterValue": "100003", 1929 "UMask": "0x1" 1930 }, 1931 { 1932 "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", 1933 "Counter": "0,1,2,3", 1934 "CounterHTOff": "0,1,2,3", 1935 "EventCode": "0xB7, 0xBB", 1936 "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", 1937 "MSRIndex": "0x1a6,0x1a7", 1938 "MSRValue": "0x10003C07F7", 1939 "Offcore": "1", 1940 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1941 "SampleAfterValue": "100003", 1942 "UMask": "0x1" 1943 }, 1944 { 1945 "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", 1946 "Counter": "0,1,2,3", 1947 "CounterHTOff": "0,1,2,3", 1948 "EventCode": "0xB7, 0xBB", 1949 "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", 1950 "MSRIndex": "0x1a6,0x1a7", 1951 "MSRValue": "0x08003C07F7", 1952 "Offcore": "1", 1953 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1954 "SampleAfterValue": "100003", 1955 "UMask": "0x1" 1956 }, 1957 { 1958 "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1959 "Counter": "0,1,2,3", 1960 "CounterHTOff": "0,1,2,3", 1961 "EventCode": "0xB7, 0xBB", 1962 "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", 1963 "MSRIndex": "0x1a6,0x1a7", 1964 "MSRValue": "0x04003C07F7", 1965 "Offcore": "1", 1966 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1967 "SampleAfterValue": "100003", 1968 "UMask": "0x1" 1969 }, 1970 { 1971 "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", 1972 "Counter": "0,1,2,3", 1973 "CounterHTOff": "0,1,2,3", 1974 "EventCode": "0xB7, 0xBB", 1975 "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", 1976 "MSRIndex": "0x1a6,0x1a7", 1977 "MSRValue": "0x01003C07F7", 1978 "Offcore": "1", 1979 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1980 "SampleAfterValue": "100003", 1981 "UMask": "0x1" 1982 }, 1983 { 1984 "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", 1985 "Counter": "0,1,2,3", 1986 "CounterHTOff": "0,1,2,3", 1987 "EventCode": "0xB7, 0xBB", 1988 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", 1989 "MSRIndex": "0x1a6,0x1a7", 1990 "MSRValue": "0x08007C07F7", 1991 "Offcore": "1", 1992 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 1993 "SampleAfterValue": "100003", 1994 "UMask": "0x1" 1995 }, 1996 { 1997 "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", 1998 "Counter": "0,1,2,3", 1999 "CounterHTOff": "0,1,2,3", 2000 "EventCode": "0xB7, 0xBB", 2001 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", 2002 "MSRIndex": "0x1a6,0x1a7", 2003 "MSRValue": "0x02003C07F7", 2004 "Offcore": "1", 2005 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2006 "SampleAfterValue": "100003", 2007 "UMask": "0x1" 2008 }, 2009 { 2010 "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", 2011 "Counter": "0,1,2,3", 2012 "CounterHTOff": "0,1,2,3", 2013 "EventCode": "0xB7, 0xBB", 2014 "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", 2015 "MSRIndex": "0x1a6,0x1a7", 2016 "MSRValue": "0x00803C07F7", 2017 "Offcore": "1", 2018 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2019 "SampleAfterValue": "100003", 2020 "UMask": "0x1" 2021 }, 2022 { 2023 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", 2024 "Counter": "0,1,2,3", 2025 "CounterHTOff": "0,1,2,3", 2026 "EventCode": "0xB7, 0xBB", 2027 "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", 2028 "MSRIndex": "0x1a6,0x1a7", 2029 "MSRValue": "0x3F800807F7", 2030 "Offcore": "1", 2031 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2032 "SampleAfterValue": "100003", 2033 "UMask": "0x1" 2034 }, 2035 { 2036 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", 2037 "Counter": "0,1,2,3", 2038 "CounterHTOff": "0,1,2,3", 2039 "EventCode": "0xB7, 0xBB", 2040 "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", 2041 "MSRIndex": "0x1a6,0x1a7", 2042 "MSRValue": "0x10000807F7", 2043 "Offcore": "1", 2044 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2045 "SampleAfterValue": "100003", 2046 "UMask": "0x1" 2047 }, 2048 { 2049 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", 2050 "Counter": "0,1,2,3", 2051 "CounterHTOff": "0,1,2,3", 2052 "EventCode": "0xB7, 0xBB", 2053 "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", 2054 "MSRIndex": "0x1a6,0x1a7", 2055 "MSRValue": "0x08000807F7", 2056 "Offcore": "1", 2057 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2058 "SampleAfterValue": "100003", 2059 "UMask": "0x1" 2060 }, 2061 { 2062 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2063 "Counter": "0,1,2,3", 2064 "CounterHTOff": "0,1,2,3", 2065 "EventCode": "0xB7, 0xBB", 2066 "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2067 "MSRIndex": "0x1a6,0x1a7", 2068 "MSRValue": "0x04000807F7", 2069 "Offcore": "1", 2070 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2071 "SampleAfterValue": "100003", 2072 "UMask": "0x1" 2073 }, 2074 { 2075 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", 2076 "Counter": "0,1,2,3", 2077 "CounterHTOff": "0,1,2,3", 2078 "EventCode": "0xB7, 0xBB", 2079 "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", 2080 "MSRIndex": "0x1a6,0x1a7", 2081 "MSRValue": "0x01000807F7", 2082 "Offcore": "1", 2083 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2084 "SampleAfterValue": "100003", 2085 "UMask": "0x1" 2086 }, 2087 { 2088 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", 2089 "Counter": "0,1,2,3", 2090 "CounterHTOff": "0,1,2,3", 2091 "EventCode": "0xB7, 0xBB", 2092 "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", 2093 "MSRIndex": "0x1a6,0x1a7", 2094 "MSRValue": "0x02000807F7", 2095 "Offcore": "1", 2096 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2097 "SampleAfterValue": "100003", 2098 "UMask": "0x1" 2099 }, 2100 { 2101 "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", 2102 "Counter": "0,1,2,3", 2103 "CounterHTOff": "0,1,2,3", 2104 "EventCode": "0xB7, 0xBB", 2105 "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", 2106 "MSRIndex": "0x1a6,0x1a7", 2107 "MSRValue": "0x00800807F7", 2108 "Offcore": "1", 2109 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2110 "SampleAfterValue": "100003", 2111 "UMask": "0x1" 2112 }, 2113 { 2114 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", 2115 "Counter": "0,1,2,3", 2116 "CounterHTOff": "0,1,2,3", 2117 "EventCode": "0xB7, 0xBB", 2118 "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", 2119 "MSRIndex": "0x1a6,0x1a7", 2120 "MSRValue": "0x3F802007F7", 2121 "Offcore": "1", 2122 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2123 "SampleAfterValue": "100003", 2124 "UMask": "0x1" 2125 }, 2126 { 2127 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", 2128 "Counter": "0,1,2,3", 2129 "CounterHTOff": "0,1,2,3", 2130 "EventCode": "0xB7, 0xBB", 2131 "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", 2132 "MSRIndex": "0x1a6,0x1a7", 2133 "MSRValue": "0x10002007F7", 2134 "Offcore": "1", 2135 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2136 "SampleAfterValue": "100003", 2137 "UMask": "0x1" 2138 }, 2139 { 2140 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", 2141 "Counter": "0,1,2,3", 2142 "CounterHTOff": "0,1,2,3", 2143 "EventCode": "0xB7, 0xBB", 2144 "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", 2145 "MSRIndex": "0x1a6,0x1a7", 2146 "MSRValue": "0x08002007F7", 2147 "Offcore": "1", 2148 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2149 "SampleAfterValue": "100003", 2150 "UMask": "0x1" 2151 }, 2152 { 2153 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2154 "Counter": "0,1,2,3", 2155 "CounterHTOff": "0,1,2,3", 2156 "EventCode": "0xB7, 0xBB", 2157 "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2158 "MSRIndex": "0x1a6,0x1a7", 2159 "MSRValue": "0x04002007F7", 2160 "Offcore": "1", 2161 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2162 "SampleAfterValue": "100003", 2163 "UMask": "0x1" 2164 }, 2165 { 2166 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", 2167 "Counter": "0,1,2,3", 2168 "CounterHTOff": "0,1,2,3", 2169 "EventCode": "0xB7, 0xBB", 2170 "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", 2171 "MSRIndex": "0x1a6,0x1a7", 2172 "MSRValue": "0x01002007F7", 2173 "Offcore": "1", 2174 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2175 "SampleAfterValue": "100003", 2176 "UMask": "0x1" 2177 }, 2178 { 2179 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", 2180 "Counter": "0,1,2,3", 2181 "CounterHTOff": "0,1,2,3", 2182 "EventCode": "0xB7, 0xBB", 2183 "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", 2184 "MSRIndex": "0x1a6,0x1a7", 2185 "MSRValue": "0x02002007F7", 2186 "Offcore": "1", 2187 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2188 "SampleAfterValue": "100003", 2189 "UMask": "0x1" 2190 }, 2191 { 2192 "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", 2193 "Counter": "0,1,2,3", 2194 "CounterHTOff": "0,1,2,3", 2195 "EventCode": "0xB7, 0xBB", 2196 "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", 2197 "MSRIndex": "0x1a6,0x1a7", 2198 "MSRValue": "0x00802007F7", 2199 "Offcore": "1", 2200 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2201 "SampleAfterValue": "100003", 2202 "UMask": "0x1" 2203 }, 2204 { 2205 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", 2206 "Counter": "0,1,2,3", 2207 "CounterHTOff": "0,1,2,3", 2208 "EventCode": "0xB7, 0xBB", 2209 "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", 2210 "MSRIndex": "0x1a6,0x1a7", 2211 "MSRValue": "0x3F800407F7", 2212 "Offcore": "1", 2213 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2214 "SampleAfterValue": "100003", 2215 "UMask": "0x1" 2216 }, 2217 { 2218 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", 2219 "Counter": "0,1,2,3", 2220 "CounterHTOff": "0,1,2,3", 2221 "EventCode": "0xB7, 0xBB", 2222 "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", 2223 "MSRIndex": "0x1a6,0x1a7", 2224 "MSRValue": "0x10000407F7", 2225 "Offcore": "1", 2226 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2227 "SampleAfterValue": "100003", 2228 "UMask": "0x1" 2229 }, 2230 { 2231 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", 2232 "Counter": "0,1,2,3", 2233 "CounterHTOff": "0,1,2,3", 2234 "EventCode": "0xB7, 0xBB", 2235 "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", 2236 "MSRIndex": "0x1a6,0x1a7", 2237 "MSRValue": "0x08000407F7", 2238 "Offcore": "1", 2239 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2240 "SampleAfterValue": "100003", 2241 "UMask": "0x1" 2242 }, 2243 { 2244 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2245 "Counter": "0,1,2,3", 2246 "CounterHTOff": "0,1,2,3", 2247 "EventCode": "0xB7, 0xBB", 2248 "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2249 "MSRIndex": "0x1a6,0x1a7", 2250 "MSRValue": "0x04000407F7", 2251 "Offcore": "1", 2252 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2253 "SampleAfterValue": "100003", 2254 "UMask": "0x1" 2255 }, 2256 { 2257 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", 2258 "Counter": "0,1,2,3", 2259 "CounterHTOff": "0,1,2,3", 2260 "EventCode": "0xB7, 0xBB", 2261 "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", 2262 "MSRIndex": "0x1a6,0x1a7", 2263 "MSRValue": "0x01000407F7", 2264 "Offcore": "1", 2265 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2266 "SampleAfterValue": "100003", 2267 "UMask": "0x1" 2268 }, 2269 { 2270 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", 2271 "Counter": "0,1,2,3", 2272 "CounterHTOff": "0,1,2,3", 2273 "EventCode": "0xB7, 0xBB", 2274 "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", 2275 "MSRIndex": "0x1a6,0x1a7", 2276 "MSRValue": "0x02000407F7", 2277 "Offcore": "1", 2278 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2279 "SampleAfterValue": "100003", 2280 "UMask": "0x1" 2281 }, 2282 { 2283 "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", 2284 "Counter": "0,1,2,3", 2285 "CounterHTOff": "0,1,2,3", 2286 "EventCode": "0xB7, 0xBB", 2287 "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", 2288 "MSRIndex": "0x1a6,0x1a7", 2289 "MSRValue": "0x00800407F7", 2290 "Offcore": "1", 2291 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2292 "SampleAfterValue": "100003", 2293 "UMask": "0x1" 2294 }, 2295 { 2296 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", 2297 "Counter": "0,1,2,3", 2298 "CounterHTOff": "0,1,2,3", 2299 "EventCode": "0xB7, 0xBB", 2300 "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", 2301 "MSRIndex": "0x1a6,0x1a7", 2302 "MSRValue": "0x3F801007F7", 2303 "Offcore": "1", 2304 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2305 "SampleAfterValue": "100003", 2306 "UMask": "0x1" 2307 }, 2308 { 2309 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", 2310 "Counter": "0,1,2,3", 2311 "CounterHTOff": "0,1,2,3", 2312 "EventCode": "0xB7, 0xBB", 2313 "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", 2314 "MSRIndex": "0x1a6,0x1a7", 2315 "MSRValue": "0x10001007F7", 2316 "Offcore": "1", 2317 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2318 "SampleAfterValue": "100003", 2319 "UMask": "0x1" 2320 }, 2321 { 2322 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", 2323 "Counter": "0,1,2,3", 2324 "CounterHTOff": "0,1,2,3", 2325 "EventCode": "0xB7, 0xBB", 2326 "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", 2327 "MSRIndex": "0x1a6,0x1a7", 2328 "MSRValue": "0x08001007F7", 2329 "Offcore": "1", 2330 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2331 "SampleAfterValue": "100003", 2332 "UMask": "0x1" 2333 }, 2334 { 2335 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2336 "Counter": "0,1,2,3", 2337 "CounterHTOff": "0,1,2,3", 2338 "EventCode": "0xB7, 0xBB", 2339 "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2340 "MSRIndex": "0x1a6,0x1a7", 2341 "MSRValue": "0x04001007F7", 2342 "Offcore": "1", 2343 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2344 "SampleAfterValue": "100003", 2345 "UMask": "0x1" 2346 }, 2347 { 2348 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", 2349 "Counter": "0,1,2,3", 2350 "CounterHTOff": "0,1,2,3", 2351 "EventCode": "0xB7, 0xBB", 2352 "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", 2353 "MSRIndex": "0x1a6,0x1a7", 2354 "MSRValue": "0x01001007F7", 2355 "Offcore": "1", 2356 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2357 "SampleAfterValue": "100003", 2358 "UMask": "0x1" 2359 }, 2360 { 2361 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", 2362 "Counter": "0,1,2,3", 2363 "CounterHTOff": "0,1,2,3", 2364 "EventCode": "0xB7, 0xBB", 2365 "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", 2366 "MSRIndex": "0x1a6,0x1a7", 2367 "MSRValue": "0x02001007F7", 2368 "Offcore": "1", 2369 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2370 "SampleAfterValue": "100003", 2371 "UMask": "0x1" 2372 }, 2373 { 2374 "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", 2375 "Counter": "0,1,2,3", 2376 "CounterHTOff": "0,1,2,3", 2377 "EventCode": "0xB7, 0xBB", 2378 "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", 2379 "MSRIndex": "0x1a6,0x1a7", 2380 "MSRValue": "0x00801007F7", 2381 "Offcore": "1", 2382 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2383 "SampleAfterValue": "100003", 2384 "UMask": "0x1" 2385 }, 2386 { 2387 "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 2388 "Counter": "0,1,2,3", 2389 "CounterHTOff": "0,1,2,3", 2390 "EventCode": "0xB7, 0xBB", 2391 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 2392 "MSRIndex": "0x1a6,0x1a7", 2393 "MSRValue": "0x3F804007F7", 2394 "Offcore": "1", 2395 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2396 "SampleAfterValue": "100003", 2397 "UMask": "0x1" 2398 }, 2399 { 2400 "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 2401 "Counter": "0,1,2,3", 2402 "CounterHTOff": "0,1,2,3", 2403 "EventCode": "0xB7, 0xBB", 2404 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 2405 "MSRIndex": "0x1a6,0x1a7", 2406 "MSRValue": "0x00804007F7", 2407 "Offcore": "1", 2408 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2409 "SampleAfterValue": "100003", 2410 "UMask": "0x1" 2411 }, 2412 { 2413 "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 2414 "Counter": "0,1,2,3", 2415 "CounterHTOff": "0,1,2,3", 2416 "EventCode": "0xB7, 0xBB", 2417 "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 2418 "MSRIndex": "0x1a6,0x1a7", 2419 "MSRValue": "0x01004007F7", 2420 "Offcore": "1", 2421 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2422 "SampleAfterValue": "100003", 2423 "UMask": "0x1" 2424 }, 2425 { 2426 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", 2427 "Counter": "0,1,2,3", 2428 "CounterHTOff": "0,1,2,3", 2429 "EventCode": "0xB7, 0xBB", 2430 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", 2431 "MSRIndex": "0x1a6,0x1a7", 2432 "MSRValue": "0x3F800207F7", 2433 "Offcore": "1", 2434 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2435 "SampleAfterValue": "100003", 2436 "UMask": "0x1" 2437 }, 2438 { 2439 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", 2440 "Counter": "0,1,2,3", 2441 "CounterHTOff": "0,1,2,3", 2442 "EventCode": "0xB7, 0xBB", 2443 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", 2444 "MSRIndex": "0x1a6,0x1a7", 2445 "MSRValue": "0x10000207F7", 2446 "Offcore": "1", 2447 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2448 "SampleAfterValue": "100003", 2449 "UMask": "0x1" 2450 }, 2451 { 2452 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2453 "Counter": "0,1,2,3", 2454 "CounterHTOff": "0,1,2,3", 2455 "EventCode": "0xB7, 0xBB", 2456 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 2457 "MSRIndex": "0x1a6,0x1a7", 2458 "MSRValue": "0x08000207F7", 2459 "Offcore": "1", 2460 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2461 "SampleAfterValue": "100003", 2462 "UMask": "0x1" 2463 }, 2464 { 2465 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 2466 "Counter": "0,1,2,3", 2467 "CounterHTOff": "0,1,2,3", 2468 "EventCode": "0xB7, 0xBB", 2469 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 2470 "MSRIndex": "0x1a6,0x1a7", 2471 "MSRValue": "0x04000207F7", 2472 "Offcore": "1", 2473 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2474 "SampleAfterValue": "100003", 2475 "UMask": "0x1" 2476 }, 2477 { 2478 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", 2479 "Counter": "0,1,2,3", 2480 "CounterHTOff": "0,1,2,3", 2481 "EventCode": "0xB7, 0xBB", 2482 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", 2483 "MSRIndex": "0x1a6,0x1a7", 2484 "MSRValue": "0x01000207F7", 2485 "Offcore": "1", 2486 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2487 "SampleAfterValue": "100003", 2488 "UMask": "0x1" 2489 }, 2490 { 2491 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", 2492 "Counter": "0,1,2,3", 2493 "CounterHTOff": "0,1,2,3", 2494 "EventCode": "0xB7, 0xBB", 2495 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", 2496 "MSRIndex": "0x1a6,0x1a7", 2497 "MSRValue": "0x02000207F7", 2498 "Offcore": "1", 2499 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2500 "SampleAfterValue": "100003", 2501 "UMask": "0x1" 2502 }, 2503 { 2504 "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", 2505 "Counter": "0,1,2,3", 2506 "CounterHTOff": "0,1,2,3", 2507 "EventCode": "0xB7, 0xBB", 2508 "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", 2509 "MSRIndex": "0x1a6,0x1a7", 2510 "MSRValue": "0x00800207F7", 2511 "Offcore": "1", 2512 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2513 "SampleAfterValue": "100003", 2514 "UMask": "0x1" 2515 }, 2516 { 2517 "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.", 2518 "Counter": "0,1,2,3", 2519 "CounterHTOff": "0,1,2,3", 2520 "EventCode": "0xB7, 0xBB", 2521 "EventName": "OCR.ALL_RFO.ANY_RESPONSE", 2522 "MSRIndex": "0x1a6,0x1a7", 2523 "MSRValue": "0x0000010122", 2524 "Offcore": "1", 2525 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2526 "SampleAfterValue": "100003", 2527 "UMask": "0x1" 2528 }, 2529 { 2530 "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", 2531 "Counter": "0,1,2,3", 2532 "CounterHTOff": "0,1,2,3", 2533 "EventCode": "0xB7, 0xBB", 2534 "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", 2535 "MSRIndex": "0x1a6,0x1a7", 2536 "MSRValue": "0x3F803C0122", 2537 "Offcore": "1", 2538 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2539 "SampleAfterValue": "100003", 2540 "UMask": "0x1" 2541 }, 2542 { 2543 "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 2544 "Counter": "0,1,2,3", 2545 "CounterHTOff": "0,1,2,3", 2546 "EventCode": "0xB7, 0xBB", 2547 "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", 2548 "MSRIndex": "0x1a6,0x1a7", 2549 "MSRValue": "0x10003C0122", 2550 "Offcore": "1", 2551 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2552 "SampleAfterValue": "100003", 2553 "UMask": "0x1" 2554 }, 2555 { 2556 "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 2557 "Counter": "0,1,2,3", 2558 "CounterHTOff": "0,1,2,3", 2559 "EventCode": "0xB7, 0xBB", 2560 "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 2561 "MSRIndex": "0x1a6,0x1a7", 2562 "MSRValue": "0x08003C0122", 2563 "Offcore": "1", 2564 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2565 "SampleAfterValue": "100003", 2566 "UMask": "0x1" 2567 }, 2568 { 2569 "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2570 "Counter": "0,1,2,3", 2571 "CounterHTOff": "0,1,2,3", 2572 "EventCode": "0xB7, 0xBB", 2573 "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 2574 "MSRIndex": "0x1a6,0x1a7", 2575 "MSRValue": "0x04003C0122", 2576 "Offcore": "1", 2577 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2578 "SampleAfterValue": "100003", 2579 "UMask": "0x1" 2580 }, 2581 { 2582 "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", 2583 "Counter": "0,1,2,3", 2584 "CounterHTOff": "0,1,2,3", 2585 "EventCode": "0xB7, 0xBB", 2586 "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", 2587 "MSRIndex": "0x1a6,0x1a7", 2588 "MSRValue": "0x01003C0122", 2589 "Offcore": "1", 2590 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2591 "SampleAfterValue": "100003", 2592 "UMask": "0x1" 2593 }, 2594 { 2595 "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 2596 "Counter": "0,1,2,3", 2597 "CounterHTOff": "0,1,2,3", 2598 "EventCode": "0xB7, 0xBB", 2599 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 2600 "MSRIndex": "0x1a6,0x1a7", 2601 "MSRValue": "0x08007C0122", 2602 "Offcore": "1", 2603 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2604 "SampleAfterValue": "100003", 2605 "UMask": "0x1" 2606 }, 2607 { 2608 "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", 2609 "Counter": "0,1,2,3", 2610 "CounterHTOff": "0,1,2,3", 2611 "EventCode": "0xB7, 0xBB", 2612 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", 2613 "MSRIndex": "0x1a6,0x1a7", 2614 "MSRValue": "0x02003C0122", 2615 "Offcore": "1", 2616 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2617 "SampleAfterValue": "100003", 2618 "UMask": "0x1" 2619 }, 2620 { 2621 "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", 2622 "Counter": "0,1,2,3", 2623 "CounterHTOff": "0,1,2,3", 2624 "EventCode": "0xB7, 0xBB", 2625 "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", 2626 "MSRIndex": "0x1a6,0x1a7", 2627 "MSRValue": "0x00803C0122", 2628 "Offcore": "1", 2629 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2630 "SampleAfterValue": "100003", 2631 "UMask": "0x1" 2632 }, 2633 { 2634 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", 2635 "Counter": "0,1,2,3", 2636 "CounterHTOff": "0,1,2,3", 2637 "EventCode": "0xB7, 0xBB", 2638 "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", 2639 "MSRIndex": "0x1a6,0x1a7", 2640 "MSRValue": "0x3F80080122", 2641 "Offcore": "1", 2642 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2643 "SampleAfterValue": "100003", 2644 "UMask": "0x1" 2645 }, 2646 { 2647 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", 2648 "Counter": "0,1,2,3", 2649 "CounterHTOff": "0,1,2,3", 2650 "EventCode": "0xB7, 0xBB", 2651 "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", 2652 "MSRIndex": "0x1a6,0x1a7", 2653 "MSRValue": "0x1000080122", 2654 "Offcore": "1", 2655 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2656 "SampleAfterValue": "100003", 2657 "UMask": "0x1" 2658 }, 2659 { 2660 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 2661 "Counter": "0,1,2,3", 2662 "CounterHTOff": "0,1,2,3", 2663 "EventCode": "0xB7, 0xBB", 2664 "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 2665 "MSRIndex": "0x1a6,0x1a7", 2666 "MSRValue": "0x0800080122", 2667 "Offcore": "1", 2668 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2669 "SampleAfterValue": "100003", 2670 "UMask": "0x1" 2671 }, 2672 { 2673 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2674 "Counter": "0,1,2,3", 2675 "CounterHTOff": "0,1,2,3", 2676 "EventCode": "0xB7, 0xBB", 2677 "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 2678 "MSRIndex": "0x1a6,0x1a7", 2679 "MSRValue": "0x0400080122", 2680 "Offcore": "1", 2681 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2682 "SampleAfterValue": "100003", 2683 "UMask": "0x1" 2684 }, 2685 { 2686 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 2687 "Counter": "0,1,2,3", 2688 "CounterHTOff": "0,1,2,3", 2689 "EventCode": "0xB7, 0xBB", 2690 "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 2691 "MSRIndex": "0x1a6,0x1a7", 2692 "MSRValue": "0x0100080122", 2693 "Offcore": "1", 2694 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2695 "SampleAfterValue": "100003", 2696 "UMask": "0x1" 2697 }, 2698 { 2699 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", 2700 "Counter": "0,1,2,3", 2701 "CounterHTOff": "0,1,2,3", 2702 "EventCode": "0xB7, 0xBB", 2703 "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", 2704 "MSRIndex": "0x1a6,0x1a7", 2705 "MSRValue": "0x0200080122", 2706 "Offcore": "1", 2707 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2708 "SampleAfterValue": "100003", 2709 "UMask": "0x1" 2710 }, 2711 { 2712 "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", 2713 "Counter": "0,1,2,3", 2714 "CounterHTOff": "0,1,2,3", 2715 "EventCode": "0xB7, 0xBB", 2716 "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", 2717 "MSRIndex": "0x1a6,0x1a7", 2718 "MSRValue": "0x0080080122", 2719 "Offcore": "1", 2720 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2721 "SampleAfterValue": "100003", 2722 "UMask": "0x1" 2723 }, 2724 { 2725 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", 2726 "Counter": "0,1,2,3", 2727 "CounterHTOff": "0,1,2,3", 2728 "EventCode": "0xB7, 0xBB", 2729 "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", 2730 "MSRIndex": "0x1a6,0x1a7", 2731 "MSRValue": "0x3F80200122", 2732 "Offcore": "1", 2733 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2734 "SampleAfterValue": "100003", 2735 "UMask": "0x1" 2736 }, 2737 { 2738 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", 2739 "Counter": "0,1,2,3", 2740 "CounterHTOff": "0,1,2,3", 2741 "EventCode": "0xB7, 0xBB", 2742 "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", 2743 "MSRIndex": "0x1a6,0x1a7", 2744 "MSRValue": "0x1000200122", 2745 "Offcore": "1", 2746 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2747 "SampleAfterValue": "100003", 2748 "UMask": "0x1" 2749 }, 2750 { 2751 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 2752 "Counter": "0,1,2,3", 2753 "CounterHTOff": "0,1,2,3", 2754 "EventCode": "0xB7, 0xBB", 2755 "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 2756 "MSRIndex": "0x1a6,0x1a7", 2757 "MSRValue": "0x0800200122", 2758 "Offcore": "1", 2759 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2760 "SampleAfterValue": "100003", 2761 "UMask": "0x1" 2762 }, 2763 { 2764 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2765 "Counter": "0,1,2,3", 2766 "CounterHTOff": "0,1,2,3", 2767 "EventCode": "0xB7, 0xBB", 2768 "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 2769 "MSRIndex": "0x1a6,0x1a7", 2770 "MSRValue": "0x0400200122", 2771 "Offcore": "1", 2772 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2773 "SampleAfterValue": "100003", 2774 "UMask": "0x1" 2775 }, 2776 { 2777 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 2778 "Counter": "0,1,2,3", 2779 "CounterHTOff": "0,1,2,3", 2780 "EventCode": "0xB7, 0xBB", 2781 "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 2782 "MSRIndex": "0x1a6,0x1a7", 2783 "MSRValue": "0x0100200122", 2784 "Offcore": "1", 2785 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2786 "SampleAfterValue": "100003", 2787 "UMask": "0x1" 2788 }, 2789 { 2790 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", 2791 "Counter": "0,1,2,3", 2792 "CounterHTOff": "0,1,2,3", 2793 "EventCode": "0xB7, 0xBB", 2794 "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", 2795 "MSRIndex": "0x1a6,0x1a7", 2796 "MSRValue": "0x0200200122", 2797 "Offcore": "1", 2798 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2799 "SampleAfterValue": "100003", 2800 "UMask": "0x1" 2801 }, 2802 { 2803 "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", 2804 "Counter": "0,1,2,3", 2805 "CounterHTOff": "0,1,2,3", 2806 "EventCode": "0xB7, 0xBB", 2807 "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", 2808 "MSRIndex": "0x1a6,0x1a7", 2809 "MSRValue": "0x0080200122", 2810 "Offcore": "1", 2811 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2812 "SampleAfterValue": "100003", 2813 "UMask": "0x1" 2814 }, 2815 { 2816 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", 2817 "Counter": "0,1,2,3", 2818 "CounterHTOff": "0,1,2,3", 2819 "EventCode": "0xB7, 0xBB", 2820 "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", 2821 "MSRIndex": "0x1a6,0x1a7", 2822 "MSRValue": "0x3F80040122", 2823 "Offcore": "1", 2824 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2825 "SampleAfterValue": "100003", 2826 "UMask": "0x1" 2827 }, 2828 { 2829 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", 2830 "Counter": "0,1,2,3", 2831 "CounterHTOff": "0,1,2,3", 2832 "EventCode": "0xB7, 0xBB", 2833 "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", 2834 "MSRIndex": "0x1a6,0x1a7", 2835 "MSRValue": "0x1000040122", 2836 "Offcore": "1", 2837 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2838 "SampleAfterValue": "100003", 2839 "UMask": "0x1" 2840 }, 2841 { 2842 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 2843 "Counter": "0,1,2,3", 2844 "CounterHTOff": "0,1,2,3", 2845 "EventCode": "0xB7, 0xBB", 2846 "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 2847 "MSRIndex": "0x1a6,0x1a7", 2848 "MSRValue": "0x0800040122", 2849 "Offcore": "1", 2850 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2851 "SampleAfterValue": "100003", 2852 "UMask": "0x1" 2853 }, 2854 { 2855 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2856 "Counter": "0,1,2,3", 2857 "CounterHTOff": "0,1,2,3", 2858 "EventCode": "0xB7, 0xBB", 2859 "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 2860 "MSRIndex": "0x1a6,0x1a7", 2861 "MSRValue": "0x0400040122", 2862 "Offcore": "1", 2863 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2864 "SampleAfterValue": "100003", 2865 "UMask": "0x1" 2866 }, 2867 { 2868 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 2869 "Counter": "0,1,2,3", 2870 "CounterHTOff": "0,1,2,3", 2871 "EventCode": "0xB7, 0xBB", 2872 "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 2873 "MSRIndex": "0x1a6,0x1a7", 2874 "MSRValue": "0x0100040122", 2875 "Offcore": "1", 2876 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2877 "SampleAfterValue": "100003", 2878 "UMask": "0x1" 2879 }, 2880 { 2881 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", 2882 "Counter": "0,1,2,3", 2883 "CounterHTOff": "0,1,2,3", 2884 "EventCode": "0xB7, 0xBB", 2885 "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", 2886 "MSRIndex": "0x1a6,0x1a7", 2887 "MSRValue": "0x0200040122", 2888 "Offcore": "1", 2889 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2890 "SampleAfterValue": "100003", 2891 "UMask": "0x1" 2892 }, 2893 { 2894 "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", 2895 "Counter": "0,1,2,3", 2896 "CounterHTOff": "0,1,2,3", 2897 "EventCode": "0xB7, 0xBB", 2898 "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", 2899 "MSRIndex": "0x1a6,0x1a7", 2900 "MSRValue": "0x0080040122", 2901 "Offcore": "1", 2902 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2903 "SampleAfterValue": "100003", 2904 "UMask": "0x1" 2905 }, 2906 { 2907 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", 2908 "Counter": "0,1,2,3", 2909 "CounterHTOff": "0,1,2,3", 2910 "EventCode": "0xB7, 0xBB", 2911 "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", 2912 "MSRIndex": "0x1a6,0x1a7", 2913 "MSRValue": "0x3F80100122", 2914 "Offcore": "1", 2915 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2916 "SampleAfterValue": "100003", 2917 "UMask": "0x1" 2918 }, 2919 { 2920 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", 2921 "Counter": "0,1,2,3", 2922 "CounterHTOff": "0,1,2,3", 2923 "EventCode": "0xB7, 0xBB", 2924 "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", 2925 "MSRIndex": "0x1a6,0x1a7", 2926 "MSRValue": "0x1000100122", 2927 "Offcore": "1", 2928 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2929 "SampleAfterValue": "100003", 2930 "UMask": "0x1" 2931 }, 2932 { 2933 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 2934 "Counter": "0,1,2,3", 2935 "CounterHTOff": "0,1,2,3", 2936 "EventCode": "0xB7, 0xBB", 2937 "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 2938 "MSRIndex": "0x1a6,0x1a7", 2939 "MSRValue": "0x0800100122", 2940 "Offcore": "1", 2941 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2942 "SampleAfterValue": "100003", 2943 "UMask": "0x1" 2944 }, 2945 { 2946 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2947 "Counter": "0,1,2,3", 2948 "CounterHTOff": "0,1,2,3", 2949 "EventCode": "0xB7, 0xBB", 2950 "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 2951 "MSRIndex": "0x1a6,0x1a7", 2952 "MSRValue": "0x0400100122", 2953 "Offcore": "1", 2954 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2955 "SampleAfterValue": "100003", 2956 "UMask": "0x1" 2957 }, 2958 { 2959 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 2960 "Counter": "0,1,2,3", 2961 "CounterHTOff": "0,1,2,3", 2962 "EventCode": "0xB7, 0xBB", 2963 "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 2964 "MSRIndex": "0x1a6,0x1a7", 2965 "MSRValue": "0x0100100122", 2966 "Offcore": "1", 2967 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2968 "SampleAfterValue": "100003", 2969 "UMask": "0x1" 2970 }, 2971 { 2972 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", 2973 "Counter": "0,1,2,3", 2974 "CounterHTOff": "0,1,2,3", 2975 "EventCode": "0xB7, 0xBB", 2976 "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", 2977 "MSRIndex": "0x1a6,0x1a7", 2978 "MSRValue": "0x0200100122", 2979 "Offcore": "1", 2980 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2981 "SampleAfterValue": "100003", 2982 "UMask": "0x1" 2983 }, 2984 { 2985 "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", 2986 "Counter": "0,1,2,3", 2987 "CounterHTOff": "0,1,2,3", 2988 "EventCode": "0xB7, 0xBB", 2989 "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", 2990 "MSRIndex": "0x1a6,0x1a7", 2991 "MSRValue": "0x0080100122", 2992 "Offcore": "1", 2993 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 2994 "SampleAfterValue": "100003", 2995 "UMask": "0x1" 2996 }, 2997 { 2998 "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 2999 "Counter": "0,1,2,3", 3000 "CounterHTOff": "0,1,2,3", 3001 "EventCode": "0xB7, 0xBB", 3002 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 3003 "MSRIndex": "0x1a6,0x1a7", 3004 "MSRValue": "0x3F80400122", 3005 "Offcore": "1", 3006 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3007 "SampleAfterValue": "100003", 3008 "UMask": "0x1" 3009 }, 3010 { 3011 "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3012 "Counter": "0,1,2,3", 3013 "CounterHTOff": "0,1,2,3", 3014 "EventCode": "0xB7, 0xBB", 3015 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3016 "MSRIndex": "0x1a6,0x1a7", 3017 "MSRValue": "0x0080400122", 3018 "Offcore": "1", 3019 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3020 "SampleAfterValue": "100003", 3021 "UMask": "0x1" 3022 }, 3023 { 3024 "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3025 "Counter": "0,1,2,3", 3026 "CounterHTOff": "0,1,2,3", 3027 "EventCode": "0xB7, 0xBB", 3028 "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3029 "MSRIndex": "0x1a6,0x1a7", 3030 "MSRValue": "0x0100400122", 3031 "Offcore": "1", 3032 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3033 "SampleAfterValue": "100003", 3034 "UMask": "0x1" 3035 }, 3036 { 3037 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", 3038 "Counter": "0,1,2,3", 3039 "CounterHTOff": "0,1,2,3", 3040 "EventCode": "0xB7, 0xBB", 3041 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", 3042 "MSRIndex": "0x1a6,0x1a7", 3043 "MSRValue": "0x3F80020122", 3044 "Offcore": "1", 3045 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3046 "SampleAfterValue": "100003", 3047 "UMask": "0x1" 3048 }, 3049 { 3050 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 3051 "Counter": "0,1,2,3", 3052 "CounterHTOff": "0,1,2,3", 3053 "EventCode": "0xB7, 0xBB", 3054 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 3055 "MSRIndex": "0x1a6,0x1a7", 3056 "MSRValue": "0x1000020122", 3057 "Offcore": "1", 3058 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3059 "SampleAfterValue": "100003", 3060 "UMask": "0x1" 3061 }, 3062 { 3063 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3064 "Counter": "0,1,2,3", 3065 "CounterHTOff": "0,1,2,3", 3066 "EventCode": "0xB7, 0xBB", 3067 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3068 "MSRIndex": "0x1a6,0x1a7", 3069 "MSRValue": "0x0800020122", 3070 "Offcore": "1", 3071 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3072 "SampleAfterValue": "100003", 3073 "UMask": "0x1" 3074 }, 3075 { 3076 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3077 "Counter": "0,1,2,3", 3078 "CounterHTOff": "0,1,2,3", 3079 "EventCode": "0xB7, 0xBB", 3080 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3081 "MSRIndex": "0x1a6,0x1a7", 3082 "MSRValue": "0x0400020122", 3083 "Offcore": "1", 3084 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3085 "SampleAfterValue": "100003", 3086 "UMask": "0x1" 3087 }, 3088 { 3089 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3090 "Counter": "0,1,2,3", 3091 "CounterHTOff": "0,1,2,3", 3092 "EventCode": "0xB7, 0xBB", 3093 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3094 "MSRIndex": "0x1a6,0x1a7", 3095 "MSRValue": "0x0100020122", 3096 "Offcore": "1", 3097 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3098 "SampleAfterValue": "100003", 3099 "UMask": "0x1" 3100 }, 3101 { 3102 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", 3103 "Counter": "0,1,2,3", 3104 "CounterHTOff": "0,1,2,3", 3105 "EventCode": "0xB7, 0xBB", 3106 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", 3107 "MSRIndex": "0x1a6,0x1a7", 3108 "MSRValue": "0x0200020122", 3109 "Offcore": "1", 3110 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3111 "SampleAfterValue": "100003", 3112 "UMask": "0x1" 3113 }, 3114 { 3115 "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", 3116 "Counter": "0,1,2,3", 3117 "CounterHTOff": "0,1,2,3", 3118 "EventCode": "0xB7, 0xBB", 3119 "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", 3120 "MSRIndex": "0x1a6,0x1a7", 3121 "MSRValue": "0x0080020122", 3122 "Offcore": "1", 3123 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3124 "SampleAfterValue": "100003", 3125 "UMask": "0x1" 3126 }, 3127 { 3128 "BriefDescription": "Counts all demand code reads have any response type.", 3129 "Counter": "0,1,2,3", 3130 "CounterHTOff": "0,1,2,3", 3131 "EventCode": "0xB7, 0xBB", 3132 "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 3133 "MSRIndex": "0x1a6,0x1a7", 3134 "MSRValue": "0x0000010004", 3135 "Offcore": "1", 3136 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3137 "SampleAfterValue": "100003", 3138 "UMask": "0x1" 3139 }, 3140 { 3141 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", 3142 "Counter": "0,1,2,3", 3143 "CounterHTOff": "0,1,2,3", 3144 "EventCode": "0xB7, 0xBB", 3145 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", 3146 "MSRIndex": "0x1a6,0x1a7", 3147 "MSRValue": "0x3F803C0004", 3148 "Offcore": "1", 3149 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3150 "SampleAfterValue": "100003", 3151 "UMask": "0x1" 3152 }, 3153 { 3154 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 3155 "Counter": "0,1,2,3", 3156 "CounterHTOff": "0,1,2,3", 3157 "EventCode": "0xB7, 0xBB", 3158 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", 3159 "MSRIndex": "0x1a6,0x1a7", 3160 "MSRValue": "0x10003C0004", 3161 "Offcore": "1", 3162 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3163 "SampleAfterValue": "100003", 3164 "UMask": "0x1" 3165 }, 3166 { 3167 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3168 "Counter": "0,1,2,3", 3169 "CounterHTOff": "0,1,2,3", 3170 "EventCode": "0xB7, 0xBB", 3171 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3172 "MSRIndex": "0x1a6,0x1a7", 3173 "MSRValue": "0x08003C0004", 3174 "Offcore": "1", 3175 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3176 "SampleAfterValue": "100003", 3177 "UMask": "0x1" 3178 }, 3179 { 3180 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3181 "Counter": "0,1,2,3", 3182 "CounterHTOff": "0,1,2,3", 3183 "EventCode": "0xB7, 0xBB", 3184 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3185 "MSRIndex": "0x1a6,0x1a7", 3186 "MSRValue": "0x04003C0004", 3187 "Offcore": "1", 3188 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3189 "SampleAfterValue": "100003", 3190 "UMask": "0x1" 3191 }, 3192 { 3193 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", 3194 "Counter": "0,1,2,3", 3195 "CounterHTOff": "0,1,2,3", 3196 "EventCode": "0xB7, 0xBB", 3197 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", 3198 "MSRIndex": "0x1a6,0x1a7", 3199 "MSRValue": "0x01003C0004", 3200 "Offcore": "1", 3201 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3202 "SampleAfterValue": "100003", 3203 "UMask": "0x1" 3204 }, 3205 { 3206 "BriefDescription": "Counts all demand code reads", 3207 "Counter": "0,1,2,3", 3208 "CounterHTOff": "0,1,2,3", 3209 "EventCode": "0xB7, 0xBB", 3210 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 3211 "MSRIndex": "0x1a6,0x1a7", 3212 "MSRValue": "0x08007C0004", 3213 "Offcore": "1", 3214 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3215 "SampleAfterValue": "100003", 3216 "UMask": "0x1" 3217 }, 3218 { 3219 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 3220 "Counter": "0,1,2,3", 3221 "CounterHTOff": "0,1,2,3", 3222 "EventCode": "0xB7, 0xBB", 3223 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 3224 "MSRIndex": "0x1a6,0x1a7", 3225 "MSRValue": "0x02003C0004", 3226 "Offcore": "1", 3227 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3228 "SampleAfterValue": "100003", 3229 "UMask": "0x1" 3230 }, 3231 { 3232 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", 3233 "Counter": "0,1,2,3", 3234 "CounterHTOff": "0,1,2,3", 3235 "EventCode": "0xB7, 0xBB", 3236 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", 3237 "MSRIndex": "0x1a6,0x1a7", 3238 "MSRValue": "0x00803C0004", 3239 "Offcore": "1", 3240 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3241 "SampleAfterValue": "100003", 3242 "UMask": "0x1" 3243 }, 3244 { 3245 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", 3246 "Counter": "0,1,2,3", 3247 "CounterHTOff": "0,1,2,3", 3248 "EventCode": "0xB7, 0xBB", 3249 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", 3250 "MSRIndex": "0x1a6,0x1a7", 3251 "MSRValue": "0x3F80080004", 3252 "Offcore": "1", 3253 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3254 "SampleAfterValue": "100003", 3255 "UMask": "0x1" 3256 }, 3257 { 3258 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", 3259 "Counter": "0,1,2,3", 3260 "CounterHTOff": "0,1,2,3", 3261 "EventCode": "0xB7, 0xBB", 3262 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", 3263 "MSRIndex": "0x1a6,0x1a7", 3264 "MSRValue": "0x1000080004", 3265 "Offcore": "1", 3266 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3267 "SampleAfterValue": "100003", 3268 "UMask": "0x1" 3269 }, 3270 { 3271 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 3272 "Counter": "0,1,2,3", 3273 "CounterHTOff": "0,1,2,3", 3274 "EventCode": "0xB7, 0xBB", 3275 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 3276 "MSRIndex": "0x1a6,0x1a7", 3277 "MSRValue": "0x0800080004", 3278 "Offcore": "1", 3279 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3280 "SampleAfterValue": "100003", 3281 "UMask": "0x1" 3282 }, 3283 { 3284 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3285 "Counter": "0,1,2,3", 3286 "CounterHTOff": "0,1,2,3", 3287 "EventCode": "0xB7, 0xBB", 3288 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3289 "MSRIndex": "0x1a6,0x1a7", 3290 "MSRValue": "0x0400080004", 3291 "Offcore": "1", 3292 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3293 "SampleAfterValue": "100003", 3294 "UMask": "0x1" 3295 }, 3296 { 3297 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", 3298 "Counter": "0,1,2,3", 3299 "CounterHTOff": "0,1,2,3", 3300 "EventCode": "0xB7, 0xBB", 3301 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", 3302 "MSRIndex": "0x1a6,0x1a7", 3303 "MSRValue": "0x0100080004", 3304 "Offcore": "1", 3305 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3306 "SampleAfterValue": "100003", 3307 "UMask": "0x1" 3308 }, 3309 { 3310 "BriefDescription": "Counts all demand code reads", 3311 "Counter": "0,1,2,3", 3312 "CounterHTOff": "0,1,2,3", 3313 "EventCode": "0xB7, 0xBB", 3314 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", 3315 "MSRIndex": "0x1a6,0x1a7", 3316 "MSRValue": "0x0200080004", 3317 "Offcore": "1", 3318 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3319 "SampleAfterValue": "100003", 3320 "UMask": "0x1" 3321 }, 3322 { 3323 "BriefDescription": "Counts all demand code reads", 3324 "Counter": "0,1,2,3", 3325 "CounterHTOff": "0,1,2,3", 3326 "EventCode": "0xB7, 0xBB", 3327 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", 3328 "MSRIndex": "0x1a6,0x1a7", 3329 "MSRValue": "0x0080080004", 3330 "Offcore": "1", 3331 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3332 "SampleAfterValue": "100003", 3333 "UMask": "0x1" 3334 }, 3335 { 3336 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", 3337 "Counter": "0,1,2,3", 3338 "CounterHTOff": "0,1,2,3", 3339 "EventCode": "0xB7, 0xBB", 3340 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", 3341 "MSRIndex": "0x1a6,0x1a7", 3342 "MSRValue": "0x3F80200004", 3343 "Offcore": "1", 3344 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3345 "SampleAfterValue": "100003", 3346 "UMask": "0x1" 3347 }, 3348 { 3349 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", 3350 "Counter": "0,1,2,3", 3351 "CounterHTOff": "0,1,2,3", 3352 "EventCode": "0xB7, 0xBB", 3353 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", 3354 "MSRIndex": "0x1a6,0x1a7", 3355 "MSRValue": "0x1000200004", 3356 "Offcore": "1", 3357 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3358 "SampleAfterValue": "100003", 3359 "UMask": "0x1" 3360 }, 3361 { 3362 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3363 "Counter": "0,1,2,3", 3364 "CounterHTOff": "0,1,2,3", 3365 "EventCode": "0xB7, 0xBB", 3366 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3367 "MSRIndex": "0x1a6,0x1a7", 3368 "MSRValue": "0x0800200004", 3369 "Offcore": "1", 3370 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3371 "SampleAfterValue": "100003", 3372 "UMask": "0x1" 3373 }, 3374 { 3375 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3376 "Counter": "0,1,2,3", 3377 "CounterHTOff": "0,1,2,3", 3378 "EventCode": "0xB7, 0xBB", 3379 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3380 "MSRIndex": "0x1a6,0x1a7", 3381 "MSRValue": "0x0400200004", 3382 "Offcore": "1", 3383 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3384 "SampleAfterValue": "100003", 3385 "UMask": "0x1" 3386 }, 3387 { 3388 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", 3389 "Counter": "0,1,2,3", 3390 "CounterHTOff": "0,1,2,3", 3391 "EventCode": "0xB7, 0xBB", 3392 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", 3393 "MSRIndex": "0x1a6,0x1a7", 3394 "MSRValue": "0x0100200004", 3395 "Offcore": "1", 3396 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3397 "SampleAfterValue": "100003", 3398 "UMask": "0x1" 3399 }, 3400 { 3401 "BriefDescription": "Counts all demand code reads", 3402 "Counter": "0,1,2,3", 3403 "CounterHTOff": "0,1,2,3", 3404 "EventCode": "0xB7, 0xBB", 3405 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", 3406 "MSRIndex": "0x1a6,0x1a7", 3407 "MSRValue": "0x0200200004", 3408 "Offcore": "1", 3409 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3410 "SampleAfterValue": "100003", 3411 "UMask": "0x1" 3412 }, 3413 { 3414 "BriefDescription": "Counts all demand code reads", 3415 "Counter": "0,1,2,3", 3416 "CounterHTOff": "0,1,2,3", 3417 "EventCode": "0xB7, 0xBB", 3418 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", 3419 "MSRIndex": "0x1a6,0x1a7", 3420 "MSRValue": "0x0080200004", 3421 "Offcore": "1", 3422 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3423 "SampleAfterValue": "100003", 3424 "UMask": "0x1" 3425 }, 3426 { 3427 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", 3428 "Counter": "0,1,2,3", 3429 "CounterHTOff": "0,1,2,3", 3430 "EventCode": "0xB7, 0xBB", 3431 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", 3432 "MSRIndex": "0x1a6,0x1a7", 3433 "MSRValue": "0x3F80040004", 3434 "Offcore": "1", 3435 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3436 "SampleAfterValue": "100003", 3437 "UMask": "0x1" 3438 }, 3439 { 3440 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", 3441 "Counter": "0,1,2,3", 3442 "CounterHTOff": "0,1,2,3", 3443 "EventCode": "0xB7, 0xBB", 3444 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", 3445 "MSRIndex": "0x1a6,0x1a7", 3446 "MSRValue": "0x1000040004", 3447 "Offcore": "1", 3448 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3449 "SampleAfterValue": "100003", 3450 "UMask": "0x1" 3451 }, 3452 { 3453 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 3454 "Counter": "0,1,2,3", 3455 "CounterHTOff": "0,1,2,3", 3456 "EventCode": "0xB7, 0xBB", 3457 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 3458 "MSRIndex": "0x1a6,0x1a7", 3459 "MSRValue": "0x0800040004", 3460 "Offcore": "1", 3461 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3462 "SampleAfterValue": "100003", 3463 "UMask": "0x1" 3464 }, 3465 { 3466 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 3467 "Counter": "0,1,2,3", 3468 "CounterHTOff": "0,1,2,3", 3469 "EventCode": "0xB7, 0xBB", 3470 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 3471 "MSRIndex": "0x1a6,0x1a7", 3472 "MSRValue": "0x0400040004", 3473 "Offcore": "1", 3474 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3475 "SampleAfterValue": "100003", 3476 "UMask": "0x1" 3477 }, 3478 { 3479 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", 3480 "Counter": "0,1,2,3", 3481 "CounterHTOff": "0,1,2,3", 3482 "EventCode": "0xB7, 0xBB", 3483 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", 3484 "MSRIndex": "0x1a6,0x1a7", 3485 "MSRValue": "0x0100040004", 3486 "Offcore": "1", 3487 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3488 "SampleAfterValue": "100003", 3489 "UMask": "0x1" 3490 }, 3491 { 3492 "BriefDescription": "Counts all demand code reads", 3493 "Counter": "0,1,2,3", 3494 "CounterHTOff": "0,1,2,3", 3495 "EventCode": "0xB7, 0xBB", 3496 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", 3497 "MSRIndex": "0x1a6,0x1a7", 3498 "MSRValue": "0x0200040004", 3499 "Offcore": "1", 3500 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3501 "SampleAfterValue": "100003", 3502 "UMask": "0x1" 3503 }, 3504 { 3505 "BriefDescription": "Counts all demand code reads", 3506 "Counter": "0,1,2,3", 3507 "CounterHTOff": "0,1,2,3", 3508 "EventCode": "0xB7, 0xBB", 3509 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", 3510 "MSRIndex": "0x1a6,0x1a7", 3511 "MSRValue": "0x0080040004", 3512 "Offcore": "1", 3513 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3514 "SampleAfterValue": "100003", 3515 "UMask": "0x1" 3516 }, 3517 { 3518 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", 3519 "Counter": "0,1,2,3", 3520 "CounterHTOff": "0,1,2,3", 3521 "EventCode": "0xB7, 0xBB", 3522 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", 3523 "MSRIndex": "0x1a6,0x1a7", 3524 "MSRValue": "0x3F80100004", 3525 "Offcore": "1", 3526 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3527 "SampleAfterValue": "100003", 3528 "UMask": "0x1" 3529 }, 3530 { 3531 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", 3532 "Counter": "0,1,2,3", 3533 "CounterHTOff": "0,1,2,3", 3534 "EventCode": "0xB7, 0xBB", 3535 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", 3536 "MSRIndex": "0x1a6,0x1a7", 3537 "MSRValue": "0x1000100004", 3538 "Offcore": "1", 3539 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3540 "SampleAfterValue": "100003", 3541 "UMask": "0x1" 3542 }, 3543 { 3544 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 3545 "Counter": "0,1,2,3", 3546 "CounterHTOff": "0,1,2,3", 3547 "EventCode": "0xB7, 0xBB", 3548 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 3549 "MSRIndex": "0x1a6,0x1a7", 3550 "MSRValue": "0x0800100004", 3551 "Offcore": "1", 3552 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3553 "SampleAfterValue": "100003", 3554 "UMask": "0x1" 3555 }, 3556 { 3557 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 3558 "Counter": "0,1,2,3", 3559 "CounterHTOff": "0,1,2,3", 3560 "EventCode": "0xB7, 0xBB", 3561 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 3562 "MSRIndex": "0x1a6,0x1a7", 3563 "MSRValue": "0x0400100004", 3564 "Offcore": "1", 3565 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3566 "SampleAfterValue": "100003", 3567 "UMask": "0x1" 3568 }, 3569 { 3570 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", 3571 "Counter": "0,1,2,3", 3572 "CounterHTOff": "0,1,2,3", 3573 "EventCode": "0xB7, 0xBB", 3574 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", 3575 "MSRIndex": "0x1a6,0x1a7", 3576 "MSRValue": "0x0100100004", 3577 "Offcore": "1", 3578 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3579 "SampleAfterValue": "100003", 3580 "UMask": "0x1" 3581 }, 3582 { 3583 "BriefDescription": "Counts all demand code reads", 3584 "Counter": "0,1,2,3", 3585 "CounterHTOff": "0,1,2,3", 3586 "EventCode": "0xB7, 0xBB", 3587 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", 3588 "MSRIndex": "0x1a6,0x1a7", 3589 "MSRValue": "0x0200100004", 3590 "Offcore": "1", 3591 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3592 "SampleAfterValue": "100003", 3593 "UMask": "0x1" 3594 }, 3595 { 3596 "BriefDescription": "Counts all demand code reads", 3597 "Counter": "0,1,2,3", 3598 "CounterHTOff": "0,1,2,3", 3599 "EventCode": "0xB7, 0xBB", 3600 "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", 3601 "MSRIndex": "0x1a6,0x1a7", 3602 "MSRValue": "0x0080100004", 3603 "Offcore": "1", 3604 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3605 "SampleAfterValue": "100003", 3606 "UMask": "0x1" 3607 }, 3608 { 3609 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 3610 "Counter": "0,1,2,3", 3611 "CounterHTOff": "0,1,2,3", 3612 "EventCode": "0xB7, 0xBB", 3613 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 3614 "MSRIndex": "0x1a6,0x1a7", 3615 "MSRValue": "0x3F80400004", 3616 "Offcore": "1", 3617 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3618 "SampleAfterValue": "100003", 3619 "UMask": "0x1" 3620 }, 3621 { 3622 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3623 "Counter": "0,1,2,3", 3624 "CounterHTOff": "0,1,2,3", 3625 "EventCode": "0xB7, 0xBB", 3626 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 3627 "MSRIndex": "0x1a6,0x1a7", 3628 "MSRValue": "0x0080400004", 3629 "Offcore": "1", 3630 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3631 "SampleAfterValue": "100003", 3632 "UMask": "0x1" 3633 }, 3634 { 3635 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3636 "Counter": "0,1,2,3", 3637 "CounterHTOff": "0,1,2,3", 3638 "EventCode": "0xB7, 0xBB", 3639 "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 3640 "MSRIndex": "0x1a6,0x1a7", 3641 "MSRValue": "0x0100400004", 3642 "Offcore": "1", 3643 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3644 "SampleAfterValue": "100003", 3645 "UMask": "0x1" 3646 }, 3647 { 3648 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", 3649 "Counter": "0,1,2,3", 3650 "CounterHTOff": "0,1,2,3", 3651 "EventCode": "0xB7, 0xBB", 3652 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", 3653 "MSRIndex": "0x1a6,0x1a7", 3654 "MSRValue": "0x3F80020004", 3655 "Offcore": "1", 3656 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3657 "SampleAfterValue": "100003", 3658 "UMask": "0x1" 3659 }, 3660 { 3661 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 3662 "Counter": "0,1,2,3", 3663 "CounterHTOff": "0,1,2,3", 3664 "EventCode": "0xB7, 0xBB", 3665 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 3666 "MSRIndex": "0x1a6,0x1a7", 3667 "MSRValue": "0x1000020004", 3668 "Offcore": "1", 3669 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3670 "SampleAfterValue": "100003", 3671 "UMask": "0x1" 3672 }, 3673 { 3674 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3675 "Counter": "0,1,2,3", 3676 "CounterHTOff": "0,1,2,3", 3677 "EventCode": "0xB7, 0xBB", 3678 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 3679 "MSRIndex": "0x1a6,0x1a7", 3680 "MSRValue": "0x0800020004", 3681 "Offcore": "1", 3682 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3683 "SampleAfterValue": "100003", 3684 "UMask": "0x1" 3685 }, 3686 { 3687 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3688 "Counter": "0,1,2,3", 3689 "CounterHTOff": "0,1,2,3", 3690 "EventCode": "0xB7, 0xBB", 3691 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 3692 "MSRIndex": "0x1a6,0x1a7", 3693 "MSRValue": "0x0400020004", 3694 "Offcore": "1", 3695 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3696 "SampleAfterValue": "100003", 3697 "UMask": "0x1" 3698 }, 3699 { 3700 "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3701 "Counter": "0,1,2,3", 3702 "CounterHTOff": "0,1,2,3", 3703 "EventCode": "0xB7, 0xBB", 3704 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 3705 "MSRIndex": "0x1a6,0x1a7", 3706 "MSRValue": "0x0100020004", 3707 "Offcore": "1", 3708 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3709 "SampleAfterValue": "100003", 3710 "UMask": "0x1" 3711 }, 3712 { 3713 "BriefDescription": "Counts all demand code reads", 3714 "Counter": "0,1,2,3", 3715 "CounterHTOff": "0,1,2,3", 3716 "EventCode": "0xB7, 0xBB", 3717 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", 3718 "MSRIndex": "0x1a6,0x1a7", 3719 "MSRValue": "0x0200020004", 3720 "Offcore": "1", 3721 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3722 "SampleAfterValue": "100003", 3723 "UMask": "0x1" 3724 }, 3725 { 3726 "BriefDescription": "Counts all demand code reads", 3727 "Counter": "0,1,2,3", 3728 "CounterHTOff": "0,1,2,3", 3729 "EventCode": "0xB7, 0xBB", 3730 "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", 3731 "MSRIndex": "0x1a6,0x1a7", 3732 "MSRValue": "0x0080020004", 3733 "Offcore": "1", 3734 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3735 "SampleAfterValue": "100003", 3736 "UMask": "0x1" 3737 }, 3738 { 3739 "BriefDescription": "Counts demand data reads have any response type.", 3740 "Counter": "0,1,2,3", 3741 "CounterHTOff": "0,1,2,3", 3742 "EventCode": "0xB7, 0xBB", 3743 "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 3744 "MSRIndex": "0x1a6,0x1a7", 3745 "MSRValue": "0x0000010001", 3746 "Offcore": "1", 3747 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3748 "SampleAfterValue": "100003", 3749 "UMask": "0x1" 3750 }, 3751 { 3752 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", 3753 "Counter": "0,1,2,3", 3754 "CounterHTOff": "0,1,2,3", 3755 "EventCode": "0xB7, 0xBB", 3756 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", 3757 "MSRIndex": "0x1a6,0x1a7", 3758 "MSRValue": "0x3F803C0001", 3759 "Offcore": "1", 3760 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3761 "SampleAfterValue": "100003", 3762 "UMask": "0x1" 3763 }, 3764 { 3765 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 3766 "Counter": "0,1,2,3", 3767 "CounterHTOff": "0,1,2,3", 3768 "EventCode": "0xB7, 0xBB", 3769 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", 3770 "MSRIndex": "0x1a6,0x1a7", 3771 "MSRValue": "0x10003C0001", 3772 "Offcore": "1", 3773 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3774 "SampleAfterValue": "100003", 3775 "UMask": "0x1" 3776 }, 3777 { 3778 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3779 "Counter": "0,1,2,3", 3780 "CounterHTOff": "0,1,2,3", 3781 "EventCode": "0xB7, 0xBB", 3782 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 3783 "MSRIndex": "0x1a6,0x1a7", 3784 "MSRValue": "0x08003C0001", 3785 "Offcore": "1", 3786 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3787 "SampleAfterValue": "100003", 3788 "UMask": "0x1" 3789 }, 3790 { 3791 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3792 "Counter": "0,1,2,3", 3793 "CounterHTOff": "0,1,2,3", 3794 "EventCode": "0xB7, 0xBB", 3795 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 3796 "MSRIndex": "0x1a6,0x1a7", 3797 "MSRValue": "0x04003C0001", 3798 "Offcore": "1", 3799 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3800 "SampleAfterValue": "100003", 3801 "UMask": "0x1" 3802 }, 3803 { 3804 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 3805 "Counter": "0,1,2,3", 3806 "CounterHTOff": "0,1,2,3", 3807 "EventCode": "0xB7, 0xBB", 3808 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 3809 "MSRIndex": "0x1a6,0x1a7", 3810 "MSRValue": "0x01003C0001", 3811 "Offcore": "1", 3812 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3813 "SampleAfterValue": "100003", 3814 "UMask": "0x1" 3815 }, 3816 { 3817 "BriefDescription": "Counts demand data reads", 3818 "Counter": "0,1,2,3", 3819 "CounterHTOff": "0,1,2,3", 3820 "EventCode": "0xB7, 0xBB", 3821 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 3822 "MSRIndex": "0x1a6,0x1a7", 3823 "MSRValue": "0x08007C0001", 3824 "Offcore": "1", 3825 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3826 "SampleAfterValue": "100003", 3827 "UMask": "0x1" 3828 }, 3829 { 3830 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 3831 "Counter": "0,1,2,3", 3832 "CounterHTOff": "0,1,2,3", 3833 "EventCode": "0xB7, 0xBB", 3834 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 3835 "MSRIndex": "0x1a6,0x1a7", 3836 "MSRValue": "0x02003C0001", 3837 "Offcore": "1", 3838 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3839 "SampleAfterValue": "100003", 3840 "UMask": "0x1" 3841 }, 3842 { 3843 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", 3844 "Counter": "0,1,2,3", 3845 "CounterHTOff": "0,1,2,3", 3846 "EventCode": "0xB7, 0xBB", 3847 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", 3848 "MSRIndex": "0x1a6,0x1a7", 3849 "MSRValue": "0x00803C0001", 3850 "Offcore": "1", 3851 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3852 "SampleAfterValue": "100003", 3853 "UMask": "0x1" 3854 }, 3855 { 3856 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", 3857 "Counter": "0,1,2,3", 3858 "CounterHTOff": "0,1,2,3", 3859 "EventCode": "0xB7, 0xBB", 3860 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", 3861 "MSRIndex": "0x1a6,0x1a7", 3862 "MSRValue": "0x3F80080001", 3863 "Offcore": "1", 3864 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3865 "SampleAfterValue": "100003", 3866 "UMask": "0x1" 3867 }, 3868 { 3869 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 3870 "Counter": "0,1,2,3", 3871 "CounterHTOff": "0,1,2,3", 3872 "EventCode": "0xB7, 0xBB", 3873 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 3874 "MSRIndex": "0x1a6,0x1a7", 3875 "MSRValue": "0x1000080001", 3876 "Offcore": "1", 3877 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3878 "SampleAfterValue": "100003", 3879 "UMask": "0x1" 3880 }, 3881 { 3882 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 3883 "Counter": "0,1,2,3", 3884 "CounterHTOff": "0,1,2,3", 3885 "EventCode": "0xB7, 0xBB", 3886 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 3887 "MSRIndex": "0x1a6,0x1a7", 3888 "MSRValue": "0x0800080001", 3889 "Offcore": "1", 3890 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3891 "SampleAfterValue": "100003", 3892 "UMask": "0x1" 3893 }, 3894 { 3895 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3896 "Counter": "0,1,2,3", 3897 "CounterHTOff": "0,1,2,3", 3898 "EventCode": "0xB7, 0xBB", 3899 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 3900 "MSRIndex": "0x1a6,0x1a7", 3901 "MSRValue": "0x0400080001", 3902 "Offcore": "1", 3903 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3904 "SampleAfterValue": "100003", 3905 "UMask": "0x1" 3906 }, 3907 { 3908 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 3909 "Counter": "0,1,2,3", 3910 "CounterHTOff": "0,1,2,3", 3911 "EventCode": "0xB7, 0xBB", 3912 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 3913 "MSRIndex": "0x1a6,0x1a7", 3914 "MSRValue": "0x0100080001", 3915 "Offcore": "1", 3916 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3917 "SampleAfterValue": "100003", 3918 "UMask": "0x1" 3919 }, 3920 { 3921 "BriefDescription": "Counts demand data reads", 3922 "Counter": "0,1,2,3", 3923 "CounterHTOff": "0,1,2,3", 3924 "EventCode": "0xB7, 0xBB", 3925 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", 3926 "MSRIndex": "0x1a6,0x1a7", 3927 "MSRValue": "0x0200080001", 3928 "Offcore": "1", 3929 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3930 "SampleAfterValue": "100003", 3931 "UMask": "0x1" 3932 }, 3933 { 3934 "BriefDescription": "Counts demand data reads", 3935 "Counter": "0,1,2,3", 3936 "CounterHTOff": "0,1,2,3", 3937 "EventCode": "0xB7, 0xBB", 3938 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", 3939 "MSRIndex": "0x1a6,0x1a7", 3940 "MSRValue": "0x0080080001", 3941 "Offcore": "1", 3942 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3943 "SampleAfterValue": "100003", 3944 "UMask": "0x1" 3945 }, 3946 { 3947 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", 3948 "Counter": "0,1,2,3", 3949 "CounterHTOff": "0,1,2,3", 3950 "EventCode": "0xB7, 0xBB", 3951 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", 3952 "MSRIndex": "0x1a6,0x1a7", 3953 "MSRValue": "0x3F80200001", 3954 "Offcore": "1", 3955 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3956 "SampleAfterValue": "100003", 3957 "UMask": "0x1" 3958 }, 3959 { 3960 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 3961 "Counter": "0,1,2,3", 3962 "CounterHTOff": "0,1,2,3", 3963 "EventCode": "0xB7, 0xBB", 3964 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 3965 "MSRIndex": "0x1a6,0x1a7", 3966 "MSRValue": "0x1000200001", 3967 "Offcore": "1", 3968 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3969 "SampleAfterValue": "100003", 3970 "UMask": "0x1" 3971 }, 3972 { 3973 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3974 "Counter": "0,1,2,3", 3975 "CounterHTOff": "0,1,2,3", 3976 "EventCode": "0xB7, 0xBB", 3977 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 3978 "MSRIndex": "0x1a6,0x1a7", 3979 "MSRValue": "0x0800200001", 3980 "Offcore": "1", 3981 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3982 "SampleAfterValue": "100003", 3983 "UMask": "0x1" 3984 }, 3985 { 3986 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3987 "Counter": "0,1,2,3", 3988 "CounterHTOff": "0,1,2,3", 3989 "EventCode": "0xB7, 0xBB", 3990 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 3991 "MSRIndex": "0x1a6,0x1a7", 3992 "MSRValue": "0x0400200001", 3993 "Offcore": "1", 3994 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 3995 "SampleAfterValue": "100003", 3996 "UMask": "0x1" 3997 }, 3998 { 3999 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 4000 "Counter": "0,1,2,3", 4001 "CounterHTOff": "0,1,2,3", 4002 "EventCode": "0xB7, 0xBB", 4003 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 4004 "MSRIndex": "0x1a6,0x1a7", 4005 "MSRValue": "0x0100200001", 4006 "Offcore": "1", 4007 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4008 "SampleAfterValue": "100003", 4009 "UMask": "0x1" 4010 }, 4011 { 4012 "BriefDescription": "Counts demand data reads", 4013 "Counter": "0,1,2,3", 4014 "CounterHTOff": "0,1,2,3", 4015 "EventCode": "0xB7, 0xBB", 4016 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", 4017 "MSRIndex": "0x1a6,0x1a7", 4018 "MSRValue": "0x0200200001", 4019 "Offcore": "1", 4020 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4021 "SampleAfterValue": "100003", 4022 "UMask": "0x1" 4023 }, 4024 { 4025 "BriefDescription": "Counts demand data reads", 4026 "Counter": "0,1,2,3", 4027 "CounterHTOff": "0,1,2,3", 4028 "EventCode": "0xB7, 0xBB", 4029 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", 4030 "MSRIndex": "0x1a6,0x1a7", 4031 "MSRValue": "0x0080200001", 4032 "Offcore": "1", 4033 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4034 "SampleAfterValue": "100003", 4035 "UMask": "0x1" 4036 }, 4037 { 4038 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", 4039 "Counter": "0,1,2,3", 4040 "CounterHTOff": "0,1,2,3", 4041 "EventCode": "0xB7, 0xBB", 4042 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", 4043 "MSRIndex": "0x1a6,0x1a7", 4044 "MSRValue": "0x3F80040001", 4045 "Offcore": "1", 4046 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4047 "SampleAfterValue": "100003", 4048 "UMask": "0x1" 4049 }, 4050 { 4051 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 4052 "Counter": "0,1,2,3", 4053 "CounterHTOff": "0,1,2,3", 4054 "EventCode": "0xB7, 0xBB", 4055 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 4056 "MSRIndex": "0x1a6,0x1a7", 4057 "MSRValue": "0x1000040001", 4058 "Offcore": "1", 4059 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4060 "SampleAfterValue": "100003", 4061 "UMask": "0x1" 4062 }, 4063 { 4064 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 4065 "Counter": "0,1,2,3", 4066 "CounterHTOff": "0,1,2,3", 4067 "EventCode": "0xB7, 0xBB", 4068 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 4069 "MSRIndex": "0x1a6,0x1a7", 4070 "MSRValue": "0x0800040001", 4071 "Offcore": "1", 4072 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4073 "SampleAfterValue": "100003", 4074 "UMask": "0x1" 4075 }, 4076 { 4077 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4078 "Counter": "0,1,2,3", 4079 "CounterHTOff": "0,1,2,3", 4080 "EventCode": "0xB7, 0xBB", 4081 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4082 "MSRIndex": "0x1a6,0x1a7", 4083 "MSRValue": "0x0400040001", 4084 "Offcore": "1", 4085 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4086 "SampleAfterValue": "100003", 4087 "UMask": "0x1" 4088 }, 4089 { 4090 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 4091 "Counter": "0,1,2,3", 4092 "CounterHTOff": "0,1,2,3", 4093 "EventCode": "0xB7, 0xBB", 4094 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 4095 "MSRIndex": "0x1a6,0x1a7", 4096 "MSRValue": "0x0100040001", 4097 "Offcore": "1", 4098 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4099 "SampleAfterValue": "100003", 4100 "UMask": "0x1" 4101 }, 4102 { 4103 "BriefDescription": "Counts demand data reads", 4104 "Counter": "0,1,2,3", 4105 "CounterHTOff": "0,1,2,3", 4106 "EventCode": "0xB7, 0xBB", 4107 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", 4108 "MSRIndex": "0x1a6,0x1a7", 4109 "MSRValue": "0x0200040001", 4110 "Offcore": "1", 4111 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4112 "SampleAfterValue": "100003", 4113 "UMask": "0x1" 4114 }, 4115 { 4116 "BriefDescription": "Counts demand data reads", 4117 "Counter": "0,1,2,3", 4118 "CounterHTOff": "0,1,2,3", 4119 "EventCode": "0xB7, 0xBB", 4120 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", 4121 "MSRIndex": "0x1a6,0x1a7", 4122 "MSRValue": "0x0080040001", 4123 "Offcore": "1", 4124 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4125 "SampleAfterValue": "100003", 4126 "UMask": "0x1" 4127 }, 4128 { 4129 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", 4130 "Counter": "0,1,2,3", 4131 "CounterHTOff": "0,1,2,3", 4132 "EventCode": "0xB7, 0xBB", 4133 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", 4134 "MSRIndex": "0x1a6,0x1a7", 4135 "MSRValue": "0x3F80100001", 4136 "Offcore": "1", 4137 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4138 "SampleAfterValue": "100003", 4139 "UMask": "0x1" 4140 }, 4141 { 4142 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 4143 "Counter": "0,1,2,3", 4144 "CounterHTOff": "0,1,2,3", 4145 "EventCode": "0xB7, 0xBB", 4146 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 4147 "MSRIndex": "0x1a6,0x1a7", 4148 "MSRValue": "0x1000100001", 4149 "Offcore": "1", 4150 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4151 "SampleAfterValue": "100003", 4152 "UMask": "0x1" 4153 }, 4154 { 4155 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 4156 "Counter": "0,1,2,3", 4157 "CounterHTOff": "0,1,2,3", 4158 "EventCode": "0xB7, 0xBB", 4159 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 4160 "MSRIndex": "0x1a6,0x1a7", 4161 "MSRValue": "0x0800100001", 4162 "Offcore": "1", 4163 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4164 "SampleAfterValue": "100003", 4165 "UMask": "0x1" 4166 }, 4167 { 4168 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4169 "Counter": "0,1,2,3", 4170 "CounterHTOff": "0,1,2,3", 4171 "EventCode": "0xB7, 0xBB", 4172 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4173 "MSRIndex": "0x1a6,0x1a7", 4174 "MSRValue": "0x0400100001", 4175 "Offcore": "1", 4176 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4177 "SampleAfterValue": "100003", 4178 "UMask": "0x1" 4179 }, 4180 { 4181 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 4182 "Counter": "0,1,2,3", 4183 "CounterHTOff": "0,1,2,3", 4184 "EventCode": "0xB7, 0xBB", 4185 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 4186 "MSRIndex": "0x1a6,0x1a7", 4187 "MSRValue": "0x0100100001", 4188 "Offcore": "1", 4189 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4190 "SampleAfterValue": "100003", 4191 "UMask": "0x1" 4192 }, 4193 { 4194 "BriefDescription": "Counts demand data reads", 4195 "Counter": "0,1,2,3", 4196 "CounterHTOff": "0,1,2,3", 4197 "EventCode": "0xB7, 0xBB", 4198 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", 4199 "MSRIndex": "0x1a6,0x1a7", 4200 "MSRValue": "0x0200100001", 4201 "Offcore": "1", 4202 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4203 "SampleAfterValue": "100003", 4204 "UMask": "0x1" 4205 }, 4206 { 4207 "BriefDescription": "Counts demand data reads", 4208 "Counter": "0,1,2,3", 4209 "CounterHTOff": "0,1,2,3", 4210 "EventCode": "0xB7, 0xBB", 4211 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", 4212 "MSRIndex": "0x1a6,0x1a7", 4213 "MSRValue": "0x0080100001", 4214 "Offcore": "1", 4215 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4216 "SampleAfterValue": "100003", 4217 "UMask": "0x1" 4218 }, 4219 { 4220 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 4221 "Counter": "0,1,2,3", 4222 "CounterHTOff": "0,1,2,3", 4223 "EventCode": "0xB7, 0xBB", 4224 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 4225 "MSRIndex": "0x1a6,0x1a7", 4226 "MSRValue": "0x3F80400001", 4227 "Offcore": "1", 4228 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4229 "SampleAfterValue": "100003", 4230 "UMask": "0x1" 4231 }, 4232 { 4233 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4234 "Counter": "0,1,2,3", 4235 "CounterHTOff": "0,1,2,3", 4236 "EventCode": "0xB7, 0xBB", 4237 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4238 "MSRIndex": "0x1a6,0x1a7", 4239 "MSRValue": "0x0080400001", 4240 "Offcore": "1", 4241 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4242 "SampleAfterValue": "100003", 4243 "UMask": "0x1" 4244 }, 4245 { 4246 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4247 "Counter": "0,1,2,3", 4248 "CounterHTOff": "0,1,2,3", 4249 "EventCode": "0xB7, 0xBB", 4250 "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4251 "MSRIndex": "0x1a6,0x1a7", 4252 "MSRValue": "0x0100400001", 4253 "Offcore": "1", 4254 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4255 "SampleAfterValue": "100003", 4256 "UMask": "0x1" 4257 }, 4258 { 4259 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 4260 "Counter": "0,1,2,3", 4261 "CounterHTOff": "0,1,2,3", 4262 "EventCode": "0xB7, 0xBB", 4263 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 4264 "MSRIndex": "0x1a6,0x1a7", 4265 "MSRValue": "0x3F80020001", 4266 "Offcore": "1", 4267 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4268 "SampleAfterValue": "100003", 4269 "UMask": "0x1" 4270 }, 4271 { 4272 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 4273 "Counter": "0,1,2,3", 4274 "CounterHTOff": "0,1,2,3", 4275 "EventCode": "0xB7, 0xBB", 4276 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 4277 "MSRIndex": "0x1a6,0x1a7", 4278 "MSRValue": "0x1000020001", 4279 "Offcore": "1", 4280 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4281 "SampleAfterValue": "100003", 4282 "UMask": "0x1" 4283 }, 4284 { 4285 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4286 "Counter": "0,1,2,3", 4287 "CounterHTOff": "0,1,2,3", 4288 "EventCode": "0xB7, 0xBB", 4289 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4290 "MSRIndex": "0x1a6,0x1a7", 4291 "MSRValue": "0x0800020001", 4292 "Offcore": "1", 4293 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4294 "SampleAfterValue": "100003", 4295 "UMask": "0x1" 4296 }, 4297 { 4298 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4299 "Counter": "0,1,2,3", 4300 "CounterHTOff": "0,1,2,3", 4301 "EventCode": "0xB7, 0xBB", 4302 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4303 "MSRIndex": "0x1a6,0x1a7", 4304 "MSRValue": "0x0400020001", 4305 "Offcore": "1", 4306 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4307 "SampleAfterValue": "100003", 4308 "UMask": "0x1" 4309 }, 4310 { 4311 "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4312 "Counter": "0,1,2,3", 4313 "CounterHTOff": "0,1,2,3", 4314 "EventCode": "0xB7, 0xBB", 4315 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4316 "MSRIndex": "0x1a6,0x1a7", 4317 "MSRValue": "0x0100020001", 4318 "Offcore": "1", 4319 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4320 "SampleAfterValue": "100003", 4321 "UMask": "0x1" 4322 }, 4323 { 4324 "BriefDescription": "Counts demand data reads", 4325 "Counter": "0,1,2,3", 4326 "CounterHTOff": "0,1,2,3", 4327 "EventCode": "0xB7, 0xBB", 4328 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 4329 "MSRIndex": "0x1a6,0x1a7", 4330 "MSRValue": "0x0200020001", 4331 "Offcore": "1", 4332 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4333 "SampleAfterValue": "100003", 4334 "UMask": "0x1" 4335 }, 4336 { 4337 "BriefDescription": "Counts demand data reads", 4338 "Counter": "0,1,2,3", 4339 "CounterHTOff": "0,1,2,3", 4340 "EventCode": "0xB7, 0xBB", 4341 "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 4342 "MSRIndex": "0x1a6,0x1a7", 4343 "MSRValue": "0x0080020001", 4344 "Offcore": "1", 4345 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4346 "SampleAfterValue": "100003", 4347 "UMask": "0x1" 4348 }, 4349 { 4350 "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", 4351 "Counter": "0,1,2,3", 4352 "CounterHTOff": "0,1,2,3", 4353 "EventCode": "0xB7, 0xBB", 4354 "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 4355 "MSRIndex": "0x1a6,0x1a7", 4356 "MSRValue": "0x0000010002", 4357 "Offcore": "1", 4358 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4359 "SampleAfterValue": "100003", 4360 "UMask": "0x1" 4361 }, 4362 { 4363 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", 4364 "Counter": "0,1,2,3", 4365 "CounterHTOff": "0,1,2,3", 4366 "EventCode": "0xB7, 0xBB", 4367 "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", 4368 "MSRIndex": "0x1a6,0x1a7", 4369 "MSRValue": "0x3F803C0002", 4370 "Offcore": "1", 4371 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4372 "SampleAfterValue": "100003", 4373 "UMask": "0x1" 4374 }, 4375 { 4376 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 4377 "Counter": "0,1,2,3", 4378 "CounterHTOff": "0,1,2,3", 4379 "EventCode": "0xB7, 0xBB", 4380 "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", 4381 "MSRIndex": "0x1a6,0x1a7", 4382 "MSRValue": "0x10003C0002", 4383 "Offcore": "1", 4384 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4385 "SampleAfterValue": "100003", 4386 "UMask": "0x1" 4387 }, 4388 { 4389 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 4390 "Counter": "0,1,2,3", 4391 "CounterHTOff": "0,1,2,3", 4392 "EventCode": "0xB7, 0xBB", 4393 "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 4394 "MSRIndex": "0x1a6,0x1a7", 4395 "MSRValue": "0x08003C0002", 4396 "Offcore": "1", 4397 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4398 "SampleAfterValue": "100003", 4399 "UMask": "0x1" 4400 }, 4401 { 4402 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4403 "Counter": "0,1,2,3", 4404 "CounterHTOff": "0,1,2,3", 4405 "EventCode": "0xB7, 0xBB", 4406 "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 4407 "MSRIndex": "0x1a6,0x1a7", 4408 "MSRValue": "0x04003C0002", 4409 "Offcore": "1", 4410 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4411 "SampleAfterValue": "100003", 4412 "UMask": "0x1" 4413 }, 4414 { 4415 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", 4416 "Counter": "0,1,2,3", 4417 "CounterHTOff": "0,1,2,3", 4418 "EventCode": "0xB7, 0xBB", 4419 "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", 4420 "MSRIndex": "0x1a6,0x1a7", 4421 "MSRValue": "0x01003C0002", 4422 "Offcore": "1", 4423 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4424 "SampleAfterValue": "100003", 4425 "UMask": "0x1" 4426 }, 4427 { 4428 "BriefDescription": "Counts all demand data writes (RFOs)", 4429 "Counter": "0,1,2,3", 4430 "CounterHTOff": "0,1,2,3", 4431 "EventCode": "0xB7, 0xBB", 4432 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 4433 "MSRIndex": "0x1a6,0x1a7", 4434 "MSRValue": "0x08007C0002", 4435 "Offcore": "1", 4436 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4437 "SampleAfterValue": "100003", 4438 "UMask": "0x1" 4439 }, 4440 { 4441 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 4442 "Counter": "0,1,2,3", 4443 "CounterHTOff": "0,1,2,3", 4444 "EventCode": "0xB7, 0xBB", 4445 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 4446 "MSRIndex": "0x1a6,0x1a7", 4447 "MSRValue": "0x02003C0002", 4448 "Offcore": "1", 4449 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4450 "SampleAfterValue": "100003", 4451 "UMask": "0x1" 4452 }, 4453 { 4454 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", 4455 "Counter": "0,1,2,3", 4456 "CounterHTOff": "0,1,2,3", 4457 "EventCode": "0xB7, 0xBB", 4458 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", 4459 "MSRIndex": "0x1a6,0x1a7", 4460 "MSRValue": "0x00803C0002", 4461 "Offcore": "1", 4462 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4463 "SampleAfterValue": "100003", 4464 "UMask": "0x1" 4465 }, 4466 { 4467 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", 4468 "Counter": "0,1,2,3", 4469 "CounterHTOff": "0,1,2,3", 4470 "EventCode": "0xB7, 0xBB", 4471 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", 4472 "MSRIndex": "0x1a6,0x1a7", 4473 "MSRValue": "0x3F80080002", 4474 "Offcore": "1", 4475 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4476 "SampleAfterValue": "100003", 4477 "UMask": "0x1" 4478 }, 4479 { 4480 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", 4481 "Counter": "0,1,2,3", 4482 "CounterHTOff": "0,1,2,3", 4483 "EventCode": "0xB7, 0xBB", 4484 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", 4485 "MSRIndex": "0x1a6,0x1a7", 4486 "MSRValue": "0x1000080002", 4487 "Offcore": "1", 4488 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4489 "SampleAfterValue": "100003", 4490 "UMask": "0x1" 4491 }, 4492 { 4493 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 4494 "Counter": "0,1,2,3", 4495 "CounterHTOff": "0,1,2,3", 4496 "EventCode": "0xB7, 0xBB", 4497 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 4498 "MSRIndex": "0x1a6,0x1a7", 4499 "MSRValue": "0x0800080002", 4500 "Offcore": "1", 4501 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4502 "SampleAfterValue": "100003", 4503 "UMask": "0x1" 4504 }, 4505 { 4506 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 4507 "Counter": "0,1,2,3", 4508 "CounterHTOff": "0,1,2,3", 4509 "EventCode": "0xB7, 0xBB", 4510 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 4511 "MSRIndex": "0x1a6,0x1a7", 4512 "MSRValue": "0x0400080002", 4513 "Offcore": "1", 4514 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4515 "SampleAfterValue": "100003", 4516 "UMask": "0x1" 4517 }, 4518 { 4519 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 4520 "Counter": "0,1,2,3", 4521 "CounterHTOff": "0,1,2,3", 4522 "EventCode": "0xB7, 0xBB", 4523 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 4524 "MSRIndex": "0x1a6,0x1a7", 4525 "MSRValue": "0x0100080002", 4526 "Offcore": "1", 4527 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4528 "SampleAfterValue": "100003", 4529 "UMask": "0x1" 4530 }, 4531 { 4532 "BriefDescription": "Counts all demand data writes (RFOs)", 4533 "Counter": "0,1,2,3", 4534 "CounterHTOff": "0,1,2,3", 4535 "EventCode": "0xB7, 0xBB", 4536 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", 4537 "MSRIndex": "0x1a6,0x1a7", 4538 "MSRValue": "0x0200080002", 4539 "Offcore": "1", 4540 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4541 "SampleAfterValue": "100003", 4542 "UMask": "0x1" 4543 }, 4544 { 4545 "BriefDescription": "Counts all demand data writes (RFOs)", 4546 "Counter": "0,1,2,3", 4547 "CounterHTOff": "0,1,2,3", 4548 "EventCode": "0xB7, 0xBB", 4549 "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", 4550 "MSRIndex": "0x1a6,0x1a7", 4551 "MSRValue": "0x0080080002", 4552 "Offcore": "1", 4553 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4554 "SampleAfterValue": "100003", 4555 "UMask": "0x1" 4556 }, 4557 { 4558 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", 4559 "Counter": "0,1,2,3", 4560 "CounterHTOff": "0,1,2,3", 4561 "EventCode": "0xB7, 0xBB", 4562 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", 4563 "MSRIndex": "0x1a6,0x1a7", 4564 "MSRValue": "0x3F80200002", 4565 "Offcore": "1", 4566 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4567 "SampleAfterValue": "100003", 4568 "UMask": "0x1" 4569 }, 4570 { 4571 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", 4572 "Counter": "0,1,2,3", 4573 "CounterHTOff": "0,1,2,3", 4574 "EventCode": "0xB7, 0xBB", 4575 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", 4576 "MSRIndex": "0x1a6,0x1a7", 4577 "MSRValue": "0x1000200002", 4578 "Offcore": "1", 4579 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4580 "SampleAfterValue": "100003", 4581 "UMask": "0x1" 4582 }, 4583 { 4584 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 4585 "Counter": "0,1,2,3", 4586 "CounterHTOff": "0,1,2,3", 4587 "EventCode": "0xB7, 0xBB", 4588 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 4589 "MSRIndex": "0x1a6,0x1a7", 4590 "MSRValue": "0x0800200002", 4591 "Offcore": "1", 4592 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4593 "SampleAfterValue": "100003", 4594 "UMask": "0x1" 4595 }, 4596 { 4597 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 4598 "Counter": "0,1,2,3", 4599 "CounterHTOff": "0,1,2,3", 4600 "EventCode": "0xB7, 0xBB", 4601 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 4602 "MSRIndex": "0x1a6,0x1a7", 4603 "MSRValue": "0x0400200002", 4604 "Offcore": "1", 4605 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4606 "SampleAfterValue": "100003", 4607 "UMask": "0x1" 4608 }, 4609 { 4610 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 4611 "Counter": "0,1,2,3", 4612 "CounterHTOff": "0,1,2,3", 4613 "EventCode": "0xB7, 0xBB", 4614 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 4615 "MSRIndex": "0x1a6,0x1a7", 4616 "MSRValue": "0x0100200002", 4617 "Offcore": "1", 4618 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4619 "SampleAfterValue": "100003", 4620 "UMask": "0x1" 4621 }, 4622 { 4623 "BriefDescription": "Counts all demand data writes (RFOs)", 4624 "Counter": "0,1,2,3", 4625 "CounterHTOff": "0,1,2,3", 4626 "EventCode": "0xB7, 0xBB", 4627 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", 4628 "MSRIndex": "0x1a6,0x1a7", 4629 "MSRValue": "0x0200200002", 4630 "Offcore": "1", 4631 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4632 "SampleAfterValue": "100003", 4633 "UMask": "0x1" 4634 }, 4635 { 4636 "BriefDescription": "Counts all demand data writes (RFOs)", 4637 "Counter": "0,1,2,3", 4638 "CounterHTOff": "0,1,2,3", 4639 "EventCode": "0xB7, 0xBB", 4640 "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", 4641 "MSRIndex": "0x1a6,0x1a7", 4642 "MSRValue": "0x0080200002", 4643 "Offcore": "1", 4644 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4645 "SampleAfterValue": "100003", 4646 "UMask": "0x1" 4647 }, 4648 { 4649 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", 4650 "Counter": "0,1,2,3", 4651 "CounterHTOff": "0,1,2,3", 4652 "EventCode": "0xB7, 0xBB", 4653 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", 4654 "MSRIndex": "0x1a6,0x1a7", 4655 "MSRValue": "0x3F80040002", 4656 "Offcore": "1", 4657 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4658 "SampleAfterValue": "100003", 4659 "UMask": "0x1" 4660 }, 4661 { 4662 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", 4663 "Counter": "0,1,2,3", 4664 "CounterHTOff": "0,1,2,3", 4665 "EventCode": "0xB7, 0xBB", 4666 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", 4667 "MSRIndex": "0x1a6,0x1a7", 4668 "MSRValue": "0x1000040002", 4669 "Offcore": "1", 4670 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4671 "SampleAfterValue": "100003", 4672 "UMask": "0x1" 4673 }, 4674 { 4675 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 4676 "Counter": "0,1,2,3", 4677 "CounterHTOff": "0,1,2,3", 4678 "EventCode": "0xB7, 0xBB", 4679 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 4680 "MSRIndex": "0x1a6,0x1a7", 4681 "MSRValue": "0x0800040002", 4682 "Offcore": "1", 4683 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4684 "SampleAfterValue": "100003", 4685 "UMask": "0x1" 4686 }, 4687 { 4688 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4689 "Counter": "0,1,2,3", 4690 "CounterHTOff": "0,1,2,3", 4691 "EventCode": "0xB7, 0xBB", 4692 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 4693 "MSRIndex": "0x1a6,0x1a7", 4694 "MSRValue": "0x0400040002", 4695 "Offcore": "1", 4696 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4697 "SampleAfterValue": "100003", 4698 "UMask": "0x1" 4699 }, 4700 { 4701 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 4702 "Counter": "0,1,2,3", 4703 "CounterHTOff": "0,1,2,3", 4704 "EventCode": "0xB7, 0xBB", 4705 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 4706 "MSRIndex": "0x1a6,0x1a7", 4707 "MSRValue": "0x0100040002", 4708 "Offcore": "1", 4709 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4710 "SampleAfterValue": "100003", 4711 "UMask": "0x1" 4712 }, 4713 { 4714 "BriefDescription": "Counts all demand data writes (RFOs)", 4715 "Counter": "0,1,2,3", 4716 "CounterHTOff": "0,1,2,3", 4717 "EventCode": "0xB7, 0xBB", 4718 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", 4719 "MSRIndex": "0x1a6,0x1a7", 4720 "MSRValue": "0x0200040002", 4721 "Offcore": "1", 4722 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4723 "SampleAfterValue": "100003", 4724 "UMask": "0x1" 4725 }, 4726 { 4727 "BriefDescription": "Counts all demand data writes (RFOs)", 4728 "Counter": "0,1,2,3", 4729 "CounterHTOff": "0,1,2,3", 4730 "EventCode": "0xB7, 0xBB", 4731 "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", 4732 "MSRIndex": "0x1a6,0x1a7", 4733 "MSRValue": "0x0080040002", 4734 "Offcore": "1", 4735 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4736 "SampleAfterValue": "100003", 4737 "UMask": "0x1" 4738 }, 4739 { 4740 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", 4741 "Counter": "0,1,2,3", 4742 "CounterHTOff": "0,1,2,3", 4743 "EventCode": "0xB7, 0xBB", 4744 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", 4745 "MSRIndex": "0x1a6,0x1a7", 4746 "MSRValue": "0x3F80100002", 4747 "Offcore": "1", 4748 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4749 "SampleAfterValue": "100003", 4750 "UMask": "0x1" 4751 }, 4752 { 4753 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", 4754 "Counter": "0,1,2,3", 4755 "CounterHTOff": "0,1,2,3", 4756 "EventCode": "0xB7, 0xBB", 4757 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", 4758 "MSRIndex": "0x1a6,0x1a7", 4759 "MSRValue": "0x1000100002", 4760 "Offcore": "1", 4761 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4762 "SampleAfterValue": "100003", 4763 "UMask": "0x1" 4764 }, 4765 { 4766 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 4767 "Counter": "0,1,2,3", 4768 "CounterHTOff": "0,1,2,3", 4769 "EventCode": "0xB7, 0xBB", 4770 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 4771 "MSRIndex": "0x1a6,0x1a7", 4772 "MSRValue": "0x0800100002", 4773 "Offcore": "1", 4774 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4775 "SampleAfterValue": "100003", 4776 "UMask": "0x1" 4777 }, 4778 { 4779 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4780 "Counter": "0,1,2,3", 4781 "CounterHTOff": "0,1,2,3", 4782 "EventCode": "0xB7, 0xBB", 4783 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 4784 "MSRIndex": "0x1a6,0x1a7", 4785 "MSRValue": "0x0400100002", 4786 "Offcore": "1", 4787 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4788 "SampleAfterValue": "100003", 4789 "UMask": "0x1" 4790 }, 4791 { 4792 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 4793 "Counter": "0,1,2,3", 4794 "CounterHTOff": "0,1,2,3", 4795 "EventCode": "0xB7, 0xBB", 4796 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 4797 "MSRIndex": "0x1a6,0x1a7", 4798 "MSRValue": "0x0100100002", 4799 "Offcore": "1", 4800 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4801 "SampleAfterValue": "100003", 4802 "UMask": "0x1" 4803 }, 4804 { 4805 "BriefDescription": "Counts all demand data writes (RFOs)", 4806 "Counter": "0,1,2,3", 4807 "CounterHTOff": "0,1,2,3", 4808 "EventCode": "0xB7, 0xBB", 4809 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", 4810 "MSRIndex": "0x1a6,0x1a7", 4811 "MSRValue": "0x0200100002", 4812 "Offcore": "1", 4813 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4814 "SampleAfterValue": "100003", 4815 "UMask": "0x1" 4816 }, 4817 { 4818 "BriefDescription": "Counts all demand data writes (RFOs)", 4819 "Counter": "0,1,2,3", 4820 "CounterHTOff": "0,1,2,3", 4821 "EventCode": "0xB7, 0xBB", 4822 "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", 4823 "MSRIndex": "0x1a6,0x1a7", 4824 "MSRValue": "0x0080100002", 4825 "Offcore": "1", 4826 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4827 "SampleAfterValue": "100003", 4828 "UMask": "0x1" 4829 }, 4830 { 4831 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 4832 "Counter": "0,1,2,3", 4833 "CounterHTOff": "0,1,2,3", 4834 "EventCode": "0xB7, 0xBB", 4835 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 4836 "MSRIndex": "0x1a6,0x1a7", 4837 "MSRValue": "0x3F80400002", 4838 "Offcore": "1", 4839 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4840 "SampleAfterValue": "100003", 4841 "UMask": "0x1" 4842 }, 4843 { 4844 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4845 "Counter": "0,1,2,3", 4846 "CounterHTOff": "0,1,2,3", 4847 "EventCode": "0xB7, 0xBB", 4848 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 4849 "MSRIndex": "0x1a6,0x1a7", 4850 "MSRValue": "0x0080400002", 4851 "Offcore": "1", 4852 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4853 "SampleAfterValue": "100003", 4854 "UMask": "0x1" 4855 }, 4856 { 4857 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4858 "Counter": "0,1,2,3", 4859 "CounterHTOff": "0,1,2,3", 4860 "EventCode": "0xB7, 0xBB", 4861 "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 4862 "MSRIndex": "0x1a6,0x1a7", 4863 "MSRValue": "0x0100400002", 4864 "Offcore": "1", 4865 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4866 "SampleAfterValue": "100003", 4867 "UMask": "0x1" 4868 }, 4869 { 4870 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", 4871 "Counter": "0,1,2,3", 4872 "CounterHTOff": "0,1,2,3", 4873 "EventCode": "0xB7, 0xBB", 4874 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", 4875 "MSRIndex": "0x1a6,0x1a7", 4876 "MSRValue": "0x3F80020002", 4877 "Offcore": "1", 4878 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4879 "SampleAfterValue": "100003", 4880 "UMask": "0x1" 4881 }, 4882 { 4883 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 4884 "Counter": "0,1,2,3", 4885 "CounterHTOff": "0,1,2,3", 4886 "EventCode": "0xB7, 0xBB", 4887 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 4888 "MSRIndex": "0x1a6,0x1a7", 4889 "MSRValue": "0x1000020002", 4890 "Offcore": "1", 4891 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4892 "SampleAfterValue": "100003", 4893 "UMask": "0x1" 4894 }, 4895 { 4896 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4897 "Counter": "0,1,2,3", 4898 "CounterHTOff": "0,1,2,3", 4899 "EventCode": "0xB7, 0xBB", 4900 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 4901 "MSRIndex": "0x1a6,0x1a7", 4902 "MSRValue": "0x0800020002", 4903 "Offcore": "1", 4904 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4905 "SampleAfterValue": "100003", 4906 "UMask": "0x1" 4907 }, 4908 { 4909 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4910 "Counter": "0,1,2,3", 4911 "CounterHTOff": "0,1,2,3", 4912 "EventCode": "0xB7, 0xBB", 4913 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 4914 "MSRIndex": "0x1a6,0x1a7", 4915 "MSRValue": "0x0400020002", 4916 "Offcore": "1", 4917 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4918 "SampleAfterValue": "100003", 4919 "UMask": "0x1" 4920 }, 4921 { 4922 "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4923 "Counter": "0,1,2,3", 4924 "CounterHTOff": "0,1,2,3", 4925 "EventCode": "0xB7, 0xBB", 4926 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 4927 "MSRIndex": "0x1a6,0x1a7", 4928 "MSRValue": "0x0100020002", 4929 "Offcore": "1", 4930 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4931 "SampleAfterValue": "100003", 4932 "UMask": "0x1" 4933 }, 4934 { 4935 "BriefDescription": "Counts all demand data writes (RFOs)", 4936 "Counter": "0,1,2,3", 4937 "CounterHTOff": "0,1,2,3", 4938 "EventCode": "0xB7, 0xBB", 4939 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", 4940 "MSRIndex": "0x1a6,0x1a7", 4941 "MSRValue": "0x0200020002", 4942 "Offcore": "1", 4943 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4944 "SampleAfterValue": "100003", 4945 "UMask": "0x1" 4946 }, 4947 { 4948 "BriefDescription": "Counts all demand data writes (RFOs)", 4949 "Counter": "0,1,2,3", 4950 "CounterHTOff": "0,1,2,3", 4951 "EventCode": "0xB7, 0xBB", 4952 "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", 4953 "MSRIndex": "0x1a6,0x1a7", 4954 "MSRValue": "0x0080020002", 4955 "Offcore": "1", 4956 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4957 "SampleAfterValue": "100003", 4958 "UMask": "0x1" 4959 }, 4960 { 4961 "BriefDescription": "Counts any other requests have any response type.", 4962 "Counter": "0,1,2,3", 4963 "CounterHTOff": "0,1,2,3", 4964 "EventCode": "0xB7, 0xBB", 4965 "EventName": "OCR.OTHER.ANY_RESPONSE", 4966 "MSRIndex": "0x1a6,0x1a7", 4967 "MSRValue": "0x0000018000", 4968 "Offcore": "1", 4969 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4970 "SampleAfterValue": "100003", 4971 "UMask": "0x1" 4972 }, 4973 { 4974 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", 4975 "Counter": "0,1,2,3", 4976 "CounterHTOff": "0,1,2,3", 4977 "EventCode": "0xB7, 0xBB", 4978 "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", 4979 "MSRIndex": "0x1a6,0x1a7", 4980 "MSRValue": "0x3F803C8000", 4981 "Offcore": "1", 4982 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4983 "SampleAfterValue": "100003", 4984 "UMask": "0x1" 4985 }, 4986 { 4987 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", 4988 "Counter": "0,1,2,3", 4989 "CounterHTOff": "0,1,2,3", 4990 "EventCode": "0xB7, 0xBB", 4991 "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", 4992 "MSRIndex": "0x1a6,0x1a7", 4993 "MSRValue": "0x10003C8000", 4994 "Offcore": "1", 4995 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 4996 "SampleAfterValue": "100003", 4997 "UMask": "0x1" 4998 }, 4999 { 5000 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", 5001 "Counter": "0,1,2,3", 5002 "CounterHTOff": "0,1,2,3", 5003 "EventCode": "0xB7, 0xBB", 5004 "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", 5005 "MSRIndex": "0x1a6,0x1a7", 5006 "MSRValue": "0x08003C8000", 5007 "Offcore": "1", 5008 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5009 "SampleAfterValue": "100003", 5010 "UMask": "0x1" 5011 }, 5012 { 5013 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5014 "Counter": "0,1,2,3", 5015 "CounterHTOff": "0,1,2,3", 5016 "EventCode": "0xB7, 0xBB", 5017 "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5018 "MSRIndex": "0x1a6,0x1a7", 5019 "MSRValue": "0x04003C8000", 5020 "Offcore": "1", 5021 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5022 "SampleAfterValue": "100003", 5023 "UMask": "0x1" 5024 }, 5025 { 5026 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", 5027 "Counter": "0,1,2,3", 5028 "CounterHTOff": "0,1,2,3", 5029 "EventCode": "0xB7, 0xBB", 5030 "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", 5031 "MSRIndex": "0x1a6,0x1a7", 5032 "MSRValue": "0x01003C8000", 5033 "Offcore": "1", 5034 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5035 "SampleAfterValue": "100003", 5036 "UMask": "0x1" 5037 }, 5038 { 5039 "BriefDescription": "Counts any other requests", 5040 "Counter": "0,1,2,3", 5041 "CounterHTOff": "0,1,2,3", 5042 "EventCode": "0xB7, 0xBB", 5043 "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", 5044 "MSRIndex": "0x1a6,0x1a7", 5045 "MSRValue": "0x08007C8000", 5046 "Offcore": "1", 5047 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5048 "SampleAfterValue": "100003", 5049 "UMask": "0x1" 5050 }, 5051 { 5052 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", 5053 "Counter": "0,1,2,3", 5054 "CounterHTOff": "0,1,2,3", 5055 "EventCode": "0xB7, 0xBB", 5056 "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", 5057 "MSRIndex": "0x1a6,0x1a7", 5058 "MSRValue": "0x02003C8000", 5059 "Offcore": "1", 5060 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5061 "SampleAfterValue": "100003", 5062 "UMask": "0x1" 5063 }, 5064 { 5065 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", 5066 "Counter": "0,1,2,3", 5067 "CounterHTOff": "0,1,2,3", 5068 "EventCode": "0xB7, 0xBB", 5069 "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", 5070 "MSRIndex": "0x1a6,0x1a7", 5071 "MSRValue": "0x00803C8000", 5072 "Offcore": "1", 5073 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5074 "SampleAfterValue": "100003", 5075 "UMask": "0x1" 5076 }, 5077 { 5078 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", 5079 "Counter": "0,1,2,3", 5080 "CounterHTOff": "0,1,2,3", 5081 "EventCode": "0xB7, 0xBB", 5082 "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", 5083 "MSRIndex": "0x1a6,0x1a7", 5084 "MSRValue": "0x3F80088000", 5085 "Offcore": "1", 5086 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5087 "SampleAfterValue": "100003", 5088 "UMask": "0x1" 5089 }, 5090 { 5091 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", 5092 "Counter": "0,1,2,3", 5093 "CounterHTOff": "0,1,2,3", 5094 "EventCode": "0xB7, 0xBB", 5095 "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", 5096 "MSRIndex": "0x1a6,0x1a7", 5097 "MSRValue": "0x1000088000", 5098 "Offcore": "1", 5099 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5100 "SampleAfterValue": "100003", 5101 "UMask": "0x1" 5102 }, 5103 { 5104 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", 5105 "Counter": "0,1,2,3", 5106 "CounterHTOff": "0,1,2,3", 5107 "EventCode": "0xB7, 0xBB", 5108 "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", 5109 "MSRIndex": "0x1a6,0x1a7", 5110 "MSRValue": "0x0800088000", 5111 "Offcore": "1", 5112 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5113 "SampleAfterValue": "100003", 5114 "UMask": "0x1" 5115 }, 5116 { 5117 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5118 "Counter": "0,1,2,3", 5119 "CounterHTOff": "0,1,2,3", 5120 "EventCode": "0xB7, 0xBB", 5121 "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5122 "MSRIndex": "0x1a6,0x1a7", 5123 "MSRValue": "0x0400088000", 5124 "Offcore": "1", 5125 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5126 "SampleAfterValue": "100003", 5127 "UMask": "0x1" 5128 }, 5129 { 5130 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", 5131 "Counter": "0,1,2,3", 5132 "CounterHTOff": "0,1,2,3", 5133 "EventCode": "0xB7, 0xBB", 5134 "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", 5135 "MSRIndex": "0x1a6,0x1a7", 5136 "MSRValue": "0x0100088000", 5137 "Offcore": "1", 5138 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5139 "SampleAfterValue": "100003", 5140 "UMask": "0x1" 5141 }, 5142 { 5143 "BriefDescription": "Counts any other requests", 5144 "Counter": "0,1,2,3", 5145 "CounterHTOff": "0,1,2,3", 5146 "EventCode": "0xB7, 0xBB", 5147 "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", 5148 "MSRIndex": "0x1a6,0x1a7", 5149 "MSRValue": "0x0200088000", 5150 "Offcore": "1", 5151 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5152 "SampleAfterValue": "100003", 5153 "UMask": "0x1" 5154 }, 5155 { 5156 "BriefDescription": "Counts any other requests", 5157 "Counter": "0,1,2,3", 5158 "CounterHTOff": "0,1,2,3", 5159 "EventCode": "0xB7, 0xBB", 5160 "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", 5161 "MSRIndex": "0x1a6,0x1a7", 5162 "MSRValue": "0x0080088000", 5163 "Offcore": "1", 5164 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5165 "SampleAfterValue": "100003", 5166 "UMask": "0x1" 5167 }, 5168 { 5169 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", 5170 "Counter": "0,1,2,3", 5171 "CounterHTOff": "0,1,2,3", 5172 "EventCode": "0xB7, 0xBB", 5173 "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", 5174 "MSRIndex": "0x1a6,0x1a7", 5175 "MSRValue": "0x3F80208000", 5176 "Offcore": "1", 5177 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5178 "SampleAfterValue": "100003", 5179 "UMask": "0x1" 5180 }, 5181 { 5182 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", 5183 "Counter": "0,1,2,3", 5184 "CounterHTOff": "0,1,2,3", 5185 "EventCode": "0xB7, 0xBB", 5186 "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", 5187 "MSRIndex": "0x1a6,0x1a7", 5188 "MSRValue": "0x1000208000", 5189 "Offcore": "1", 5190 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5191 "SampleAfterValue": "100003", 5192 "UMask": "0x1" 5193 }, 5194 { 5195 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", 5196 "Counter": "0,1,2,3", 5197 "CounterHTOff": "0,1,2,3", 5198 "EventCode": "0xB7, 0xBB", 5199 "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", 5200 "MSRIndex": "0x1a6,0x1a7", 5201 "MSRValue": "0x0800208000", 5202 "Offcore": "1", 5203 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5204 "SampleAfterValue": "100003", 5205 "UMask": "0x1" 5206 }, 5207 { 5208 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5209 "Counter": "0,1,2,3", 5210 "CounterHTOff": "0,1,2,3", 5211 "EventCode": "0xB7, 0xBB", 5212 "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5213 "MSRIndex": "0x1a6,0x1a7", 5214 "MSRValue": "0x0400208000", 5215 "Offcore": "1", 5216 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5217 "SampleAfterValue": "100003", 5218 "UMask": "0x1" 5219 }, 5220 { 5221 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", 5222 "Counter": "0,1,2,3", 5223 "CounterHTOff": "0,1,2,3", 5224 "EventCode": "0xB7, 0xBB", 5225 "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", 5226 "MSRIndex": "0x1a6,0x1a7", 5227 "MSRValue": "0x0100208000", 5228 "Offcore": "1", 5229 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5230 "SampleAfterValue": "100003", 5231 "UMask": "0x1" 5232 }, 5233 { 5234 "BriefDescription": "Counts any other requests", 5235 "Counter": "0,1,2,3", 5236 "CounterHTOff": "0,1,2,3", 5237 "EventCode": "0xB7, 0xBB", 5238 "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", 5239 "MSRIndex": "0x1a6,0x1a7", 5240 "MSRValue": "0x0200208000", 5241 "Offcore": "1", 5242 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5243 "SampleAfterValue": "100003", 5244 "UMask": "0x1" 5245 }, 5246 { 5247 "BriefDescription": "Counts any other requests", 5248 "Counter": "0,1,2,3", 5249 "CounterHTOff": "0,1,2,3", 5250 "EventCode": "0xB7, 0xBB", 5251 "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", 5252 "MSRIndex": "0x1a6,0x1a7", 5253 "MSRValue": "0x0080208000", 5254 "Offcore": "1", 5255 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5256 "SampleAfterValue": "100003", 5257 "UMask": "0x1" 5258 }, 5259 { 5260 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", 5261 "Counter": "0,1,2,3", 5262 "CounterHTOff": "0,1,2,3", 5263 "EventCode": "0xB7, 0xBB", 5264 "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", 5265 "MSRIndex": "0x1a6,0x1a7", 5266 "MSRValue": "0x3F80048000", 5267 "Offcore": "1", 5268 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5269 "SampleAfterValue": "100003", 5270 "UMask": "0x1" 5271 }, 5272 { 5273 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", 5274 "Counter": "0,1,2,3", 5275 "CounterHTOff": "0,1,2,3", 5276 "EventCode": "0xB7, 0xBB", 5277 "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", 5278 "MSRIndex": "0x1a6,0x1a7", 5279 "MSRValue": "0x1000048000", 5280 "Offcore": "1", 5281 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5282 "SampleAfterValue": "100003", 5283 "UMask": "0x1" 5284 }, 5285 { 5286 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", 5287 "Counter": "0,1,2,3", 5288 "CounterHTOff": "0,1,2,3", 5289 "EventCode": "0xB7, 0xBB", 5290 "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", 5291 "MSRIndex": "0x1a6,0x1a7", 5292 "MSRValue": "0x0800048000", 5293 "Offcore": "1", 5294 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5295 "SampleAfterValue": "100003", 5296 "UMask": "0x1" 5297 }, 5298 { 5299 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5300 "Counter": "0,1,2,3", 5301 "CounterHTOff": "0,1,2,3", 5302 "EventCode": "0xB7, 0xBB", 5303 "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5304 "MSRIndex": "0x1a6,0x1a7", 5305 "MSRValue": "0x0400048000", 5306 "Offcore": "1", 5307 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5308 "SampleAfterValue": "100003", 5309 "UMask": "0x1" 5310 }, 5311 { 5312 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", 5313 "Counter": "0,1,2,3", 5314 "CounterHTOff": "0,1,2,3", 5315 "EventCode": "0xB7, 0xBB", 5316 "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", 5317 "MSRIndex": "0x1a6,0x1a7", 5318 "MSRValue": "0x0100048000", 5319 "Offcore": "1", 5320 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5321 "SampleAfterValue": "100003", 5322 "UMask": "0x1" 5323 }, 5324 { 5325 "BriefDescription": "Counts any other requests", 5326 "Counter": "0,1,2,3", 5327 "CounterHTOff": "0,1,2,3", 5328 "EventCode": "0xB7, 0xBB", 5329 "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", 5330 "MSRIndex": "0x1a6,0x1a7", 5331 "MSRValue": "0x0200048000", 5332 "Offcore": "1", 5333 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5334 "SampleAfterValue": "100003", 5335 "UMask": "0x1" 5336 }, 5337 { 5338 "BriefDescription": "Counts any other requests", 5339 "Counter": "0,1,2,3", 5340 "CounterHTOff": "0,1,2,3", 5341 "EventCode": "0xB7, 0xBB", 5342 "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", 5343 "MSRIndex": "0x1a6,0x1a7", 5344 "MSRValue": "0x0080048000", 5345 "Offcore": "1", 5346 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5347 "SampleAfterValue": "100003", 5348 "UMask": "0x1" 5349 }, 5350 { 5351 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", 5352 "Counter": "0,1,2,3", 5353 "CounterHTOff": "0,1,2,3", 5354 "EventCode": "0xB7, 0xBB", 5355 "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", 5356 "MSRIndex": "0x1a6,0x1a7", 5357 "MSRValue": "0x3F80108000", 5358 "Offcore": "1", 5359 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5360 "SampleAfterValue": "100003", 5361 "UMask": "0x1" 5362 }, 5363 { 5364 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", 5365 "Counter": "0,1,2,3", 5366 "CounterHTOff": "0,1,2,3", 5367 "EventCode": "0xB7, 0xBB", 5368 "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", 5369 "MSRIndex": "0x1a6,0x1a7", 5370 "MSRValue": "0x1000108000", 5371 "Offcore": "1", 5372 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5373 "SampleAfterValue": "100003", 5374 "UMask": "0x1" 5375 }, 5376 { 5377 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", 5378 "Counter": "0,1,2,3", 5379 "CounterHTOff": "0,1,2,3", 5380 "EventCode": "0xB7, 0xBB", 5381 "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", 5382 "MSRIndex": "0x1a6,0x1a7", 5383 "MSRValue": "0x0800108000", 5384 "Offcore": "1", 5385 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5386 "SampleAfterValue": "100003", 5387 "UMask": "0x1" 5388 }, 5389 { 5390 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5391 "Counter": "0,1,2,3", 5392 "CounterHTOff": "0,1,2,3", 5393 "EventCode": "0xB7, 0xBB", 5394 "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 5395 "MSRIndex": "0x1a6,0x1a7", 5396 "MSRValue": "0x0400108000", 5397 "Offcore": "1", 5398 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5399 "SampleAfterValue": "100003", 5400 "UMask": "0x1" 5401 }, 5402 { 5403 "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", 5404 "Counter": "0,1,2,3", 5405 "CounterHTOff": "0,1,2,3", 5406 "EventCode": "0xB7, 0xBB", 5407 "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", 5408 "MSRIndex": "0x1a6,0x1a7", 5409 "MSRValue": "0x0100108000", 5410 "Offcore": "1", 5411 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5412 "SampleAfterValue": "100003", 5413 "UMask": "0x1" 5414 }, 5415 { 5416 "BriefDescription": "Counts any other requests", 5417 "Counter": "0,1,2,3", 5418 "CounterHTOff": "0,1,2,3", 5419 "EventCode": "0xB7, 0xBB", 5420 "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", 5421 "MSRIndex": "0x1a6,0x1a7", 5422 "MSRValue": "0x0200108000", 5423 "Offcore": "1", 5424 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5425 "SampleAfterValue": "100003", 5426 "UMask": "0x1" 5427 }, 5428 { 5429 "BriefDescription": "Counts any other requests", 5430 "Counter": "0,1,2,3", 5431 "CounterHTOff": "0,1,2,3", 5432 "EventCode": "0xB7, 0xBB", 5433 "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", 5434 "MSRIndex": "0x1a6,0x1a7", 5435 "MSRValue": "0x0080108000", 5436 "Offcore": "1", 5437 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5438 "SampleAfterValue": "100003", 5439 "UMask": "0x1" 5440 }, 5441 { 5442 "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 5443 "Counter": "0,1,2,3", 5444 "CounterHTOff": "0,1,2,3", 5445 "EventCode": "0xB7, 0xBB", 5446 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 5447 "MSRIndex": "0x1a6,0x1a7", 5448 "MSRValue": "0x3F80408000", 5449 "Offcore": "1", 5450 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5451 "SampleAfterValue": "100003", 5452 "UMask": "0x1" 5453 }, 5454 { 5455 "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 5456 "Counter": "0,1,2,3", 5457 "CounterHTOff": "0,1,2,3", 5458 "EventCode": "0xB7, 0xBB", 5459 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 5460 "MSRIndex": "0x1a6,0x1a7", 5461 "MSRValue": "0x0080408000", 5462 "Offcore": "1", 5463 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5464 "SampleAfterValue": "100003", 5465 "UMask": "0x1" 5466 }, 5467 { 5468 "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 5469 "Counter": "0,1,2,3", 5470 "CounterHTOff": "0,1,2,3", 5471 "EventCode": "0xB7, 0xBB", 5472 "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 5473 "MSRIndex": "0x1a6,0x1a7", 5474 "MSRValue": "0x0100408000", 5475 "Offcore": "1", 5476 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5477 "SampleAfterValue": "100003", 5478 "UMask": "0x1" 5479 }, 5480 { 5481 "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", 5482 "Counter": "0,1,2,3", 5483 "CounterHTOff": "0,1,2,3", 5484 "EventCode": "0xB7, 0xBB", 5485 "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", 5486 "MSRIndex": "0x1a6,0x1a7", 5487 "MSRValue": "0x3F80028000", 5488 "Offcore": "1", 5489 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5490 "SampleAfterValue": "100003", 5491 "UMask": "0x1" 5492 }, 5493 { 5494 "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", 5495 "Counter": "0,1,2,3", 5496 "CounterHTOff": "0,1,2,3", 5497 "EventCode": "0xB7, 0xBB", 5498 "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", 5499 "MSRIndex": "0x1a6,0x1a7", 5500 "MSRValue": "0x1000028000", 5501 "Offcore": "1", 5502 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5503 "SampleAfterValue": "100003", 5504 "UMask": "0x1" 5505 }, 5506 { 5507 "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5508 "Counter": "0,1,2,3", 5509 "CounterHTOff": "0,1,2,3", 5510 "EventCode": "0xB7, 0xBB", 5511 "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 5512 "MSRIndex": "0x1a6,0x1a7", 5513 "MSRValue": "0x0800028000", 5514 "Offcore": "1", 5515 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5516 "SampleAfterValue": "100003", 5517 "UMask": "0x1" 5518 }, 5519 { 5520 "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5521 "Counter": "0,1,2,3", 5522 "CounterHTOff": "0,1,2,3", 5523 "EventCode": "0xB7, 0xBB", 5524 "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 5525 "MSRIndex": "0x1a6,0x1a7", 5526 "MSRValue": "0x0400028000", 5527 "Offcore": "1", 5528 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5529 "SampleAfterValue": "100003", 5530 "UMask": "0x1" 5531 }, 5532 { 5533 "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", 5534 "Counter": "0,1,2,3", 5535 "CounterHTOff": "0,1,2,3", 5536 "EventCode": "0xB7, 0xBB", 5537 "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", 5538 "MSRIndex": "0x1a6,0x1a7", 5539 "MSRValue": "0x0100028000", 5540 "Offcore": "1", 5541 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5542 "SampleAfterValue": "100003", 5543 "UMask": "0x1" 5544 }, 5545 { 5546 "BriefDescription": "Counts any other requests", 5547 "Counter": "0,1,2,3", 5548 "CounterHTOff": "0,1,2,3", 5549 "EventCode": "0xB7, 0xBB", 5550 "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", 5551 "MSRIndex": "0x1a6,0x1a7", 5552 "MSRValue": "0x0200028000", 5553 "Offcore": "1", 5554 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5555 "SampleAfterValue": "100003", 5556 "UMask": "0x1" 5557 }, 5558 { 5559 "BriefDescription": "Counts any other requests", 5560 "Counter": "0,1,2,3", 5561 "CounterHTOff": "0,1,2,3", 5562 "EventCode": "0xB7, 0xBB", 5563 "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", 5564 "MSRIndex": "0x1a6,0x1a7", 5565 "MSRValue": "0x0080028000", 5566 "Offcore": "1", 5567 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5568 "SampleAfterValue": "100003", 5569 "UMask": "0x1" 5570 }, 5571 { 5572 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.", 5573 "Counter": "0,1,2,3", 5574 "CounterHTOff": "0,1,2,3", 5575 "EventCode": "0xB7, 0xBB", 5576 "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", 5577 "MSRIndex": "0x1a6,0x1a7", 5578 "MSRValue": "0x0000010400", 5579 "Offcore": "1", 5580 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5581 "SampleAfterValue": "100003", 5582 "UMask": "0x1" 5583 }, 5584 { 5585 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", 5586 "Counter": "0,1,2,3", 5587 "CounterHTOff": "0,1,2,3", 5588 "EventCode": "0xB7, 0xBB", 5589 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", 5590 "MSRIndex": "0x1a6,0x1a7", 5591 "MSRValue": "0x3F803C0400", 5592 "Offcore": "1", 5593 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5594 "SampleAfterValue": "100003", 5595 "UMask": "0x1" 5596 }, 5597 { 5598 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", 5599 "Counter": "0,1,2,3", 5600 "CounterHTOff": "0,1,2,3", 5601 "EventCode": "0xB7, 0xBB", 5602 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", 5603 "MSRIndex": "0x1a6,0x1a7", 5604 "MSRValue": "0x10003C0400", 5605 "Offcore": "1", 5606 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5607 "SampleAfterValue": "100003", 5608 "UMask": "0x1" 5609 }, 5610 { 5611 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", 5612 "Counter": "0,1,2,3", 5613 "CounterHTOff": "0,1,2,3", 5614 "EventCode": "0xB7, 0xBB", 5615 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", 5616 "MSRIndex": "0x1a6,0x1a7", 5617 "MSRValue": "0x08003C0400", 5618 "Offcore": "1", 5619 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5620 "SampleAfterValue": "100003", 5621 "UMask": "0x1" 5622 }, 5623 { 5624 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5625 "Counter": "0,1,2,3", 5626 "CounterHTOff": "0,1,2,3", 5627 "EventCode": "0xB7, 0xBB", 5628 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", 5629 "MSRIndex": "0x1a6,0x1a7", 5630 "MSRValue": "0x04003C0400", 5631 "Offcore": "1", 5632 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5633 "SampleAfterValue": "100003", 5634 "UMask": "0x1" 5635 }, 5636 { 5637 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", 5638 "Counter": "0,1,2,3", 5639 "CounterHTOff": "0,1,2,3", 5640 "EventCode": "0xB7, 0xBB", 5641 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", 5642 "MSRIndex": "0x1a6,0x1a7", 5643 "MSRValue": "0x01003C0400", 5644 "Offcore": "1", 5645 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5646 "SampleAfterValue": "100003", 5647 "UMask": "0x1" 5648 }, 5649 { 5650 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5651 "Counter": "0,1,2,3", 5652 "CounterHTOff": "0,1,2,3", 5653 "EventCode": "0xB7, 0xBB", 5654 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", 5655 "MSRIndex": "0x1a6,0x1a7", 5656 "MSRValue": "0x08007C0400", 5657 "Offcore": "1", 5658 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5659 "SampleAfterValue": "100003", 5660 "UMask": "0x1" 5661 }, 5662 { 5663 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", 5664 "Counter": "0,1,2,3", 5665 "CounterHTOff": "0,1,2,3", 5666 "EventCode": "0xB7, 0xBB", 5667 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", 5668 "MSRIndex": "0x1a6,0x1a7", 5669 "MSRValue": "0x02003C0400", 5670 "Offcore": "1", 5671 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5672 "SampleAfterValue": "100003", 5673 "UMask": "0x1" 5674 }, 5675 { 5676 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", 5677 "Counter": "0,1,2,3", 5678 "CounterHTOff": "0,1,2,3", 5679 "EventCode": "0xB7, 0xBB", 5680 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", 5681 "MSRIndex": "0x1a6,0x1a7", 5682 "MSRValue": "0x00803C0400", 5683 "Offcore": "1", 5684 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5685 "SampleAfterValue": "100003", 5686 "UMask": "0x1" 5687 }, 5688 { 5689 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", 5690 "Counter": "0,1,2,3", 5691 "CounterHTOff": "0,1,2,3", 5692 "EventCode": "0xB7, 0xBB", 5693 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", 5694 "MSRIndex": "0x1a6,0x1a7", 5695 "MSRValue": "0x3F80080400", 5696 "Offcore": "1", 5697 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5698 "SampleAfterValue": "100003", 5699 "UMask": "0x1" 5700 }, 5701 { 5702 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", 5703 "Counter": "0,1,2,3", 5704 "CounterHTOff": "0,1,2,3", 5705 "EventCode": "0xB7, 0xBB", 5706 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", 5707 "MSRIndex": "0x1a6,0x1a7", 5708 "MSRValue": "0x1000080400", 5709 "Offcore": "1", 5710 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5711 "SampleAfterValue": "100003", 5712 "UMask": "0x1" 5713 }, 5714 { 5715 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", 5716 "Counter": "0,1,2,3", 5717 "CounterHTOff": "0,1,2,3", 5718 "EventCode": "0xB7, 0xBB", 5719 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", 5720 "MSRIndex": "0x1a6,0x1a7", 5721 "MSRValue": "0x0800080400", 5722 "Offcore": "1", 5723 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5724 "SampleAfterValue": "100003", 5725 "UMask": "0x1" 5726 }, 5727 { 5728 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5729 "Counter": "0,1,2,3", 5730 "CounterHTOff": "0,1,2,3", 5731 "EventCode": "0xB7, 0xBB", 5732 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 5733 "MSRIndex": "0x1a6,0x1a7", 5734 "MSRValue": "0x0400080400", 5735 "Offcore": "1", 5736 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5737 "SampleAfterValue": "100003", 5738 "UMask": "0x1" 5739 }, 5740 { 5741 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", 5742 "Counter": "0,1,2,3", 5743 "CounterHTOff": "0,1,2,3", 5744 "EventCode": "0xB7, 0xBB", 5745 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", 5746 "MSRIndex": "0x1a6,0x1a7", 5747 "MSRValue": "0x0100080400", 5748 "Offcore": "1", 5749 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5750 "SampleAfterValue": "100003", 5751 "UMask": "0x1" 5752 }, 5753 { 5754 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5755 "Counter": "0,1,2,3", 5756 "CounterHTOff": "0,1,2,3", 5757 "EventCode": "0xB7, 0xBB", 5758 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", 5759 "MSRIndex": "0x1a6,0x1a7", 5760 "MSRValue": "0x0200080400", 5761 "Offcore": "1", 5762 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5763 "SampleAfterValue": "100003", 5764 "UMask": "0x1" 5765 }, 5766 { 5767 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5768 "Counter": "0,1,2,3", 5769 "CounterHTOff": "0,1,2,3", 5770 "EventCode": "0xB7, 0xBB", 5771 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", 5772 "MSRIndex": "0x1a6,0x1a7", 5773 "MSRValue": "0x0080080400", 5774 "Offcore": "1", 5775 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5776 "SampleAfterValue": "100003", 5777 "UMask": "0x1" 5778 }, 5779 { 5780 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", 5781 "Counter": "0,1,2,3", 5782 "CounterHTOff": "0,1,2,3", 5783 "EventCode": "0xB7, 0xBB", 5784 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", 5785 "MSRIndex": "0x1a6,0x1a7", 5786 "MSRValue": "0x3F80200400", 5787 "Offcore": "1", 5788 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5789 "SampleAfterValue": "100003", 5790 "UMask": "0x1" 5791 }, 5792 { 5793 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", 5794 "Counter": "0,1,2,3", 5795 "CounterHTOff": "0,1,2,3", 5796 "EventCode": "0xB7, 0xBB", 5797 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", 5798 "MSRIndex": "0x1a6,0x1a7", 5799 "MSRValue": "0x1000200400", 5800 "Offcore": "1", 5801 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5802 "SampleAfterValue": "100003", 5803 "UMask": "0x1" 5804 }, 5805 { 5806 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", 5807 "Counter": "0,1,2,3", 5808 "CounterHTOff": "0,1,2,3", 5809 "EventCode": "0xB7, 0xBB", 5810 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", 5811 "MSRIndex": "0x1a6,0x1a7", 5812 "MSRValue": "0x0800200400", 5813 "Offcore": "1", 5814 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5815 "SampleAfterValue": "100003", 5816 "UMask": "0x1" 5817 }, 5818 { 5819 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5820 "Counter": "0,1,2,3", 5821 "CounterHTOff": "0,1,2,3", 5822 "EventCode": "0xB7, 0xBB", 5823 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 5824 "MSRIndex": "0x1a6,0x1a7", 5825 "MSRValue": "0x0400200400", 5826 "Offcore": "1", 5827 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5828 "SampleAfterValue": "100003", 5829 "UMask": "0x1" 5830 }, 5831 { 5832 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", 5833 "Counter": "0,1,2,3", 5834 "CounterHTOff": "0,1,2,3", 5835 "EventCode": "0xB7, 0xBB", 5836 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", 5837 "MSRIndex": "0x1a6,0x1a7", 5838 "MSRValue": "0x0100200400", 5839 "Offcore": "1", 5840 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5841 "SampleAfterValue": "100003", 5842 "UMask": "0x1" 5843 }, 5844 { 5845 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5846 "Counter": "0,1,2,3", 5847 "CounterHTOff": "0,1,2,3", 5848 "EventCode": "0xB7, 0xBB", 5849 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", 5850 "MSRIndex": "0x1a6,0x1a7", 5851 "MSRValue": "0x0200200400", 5852 "Offcore": "1", 5853 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5854 "SampleAfterValue": "100003", 5855 "UMask": "0x1" 5856 }, 5857 { 5858 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5859 "Counter": "0,1,2,3", 5860 "CounterHTOff": "0,1,2,3", 5861 "EventCode": "0xB7, 0xBB", 5862 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", 5863 "MSRIndex": "0x1a6,0x1a7", 5864 "MSRValue": "0x0080200400", 5865 "Offcore": "1", 5866 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5867 "SampleAfterValue": "100003", 5868 "UMask": "0x1" 5869 }, 5870 { 5871 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", 5872 "Counter": "0,1,2,3", 5873 "CounterHTOff": "0,1,2,3", 5874 "EventCode": "0xB7, 0xBB", 5875 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", 5876 "MSRIndex": "0x1a6,0x1a7", 5877 "MSRValue": "0x3F80040400", 5878 "Offcore": "1", 5879 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5880 "SampleAfterValue": "100003", 5881 "UMask": "0x1" 5882 }, 5883 { 5884 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", 5885 "Counter": "0,1,2,3", 5886 "CounterHTOff": "0,1,2,3", 5887 "EventCode": "0xB7, 0xBB", 5888 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", 5889 "MSRIndex": "0x1a6,0x1a7", 5890 "MSRValue": "0x1000040400", 5891 "Offcore": "1", 5892 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5893 "SampleAfterValue": "100003", 5894 "UMask": "0x1" 5895 }, 5896 { 5897 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", 5898 "Counter": "0,1,2,3", 5899 "CounterHTOff": "0,1,2,3", 5900 "EventCode": "0xB7, 0xBB", 5901 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", 5902 "MSRIndex": "0x1a6,0x1a7", 5903 "MSRValue": "0x0800040400", 5904 "Offcore": "1", 5905 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5906 "SampleAfterValue": "100003", 5907 "UMask": "0x1" 5908 }, 5909 { 5910 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5911 "Counter": "0,1,2,3", 5912 "CounterHTOff": "0,1,2,3", 5913 "EventCode": "0xB7, 0xBB", 5914 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 5915 "MSRIndex": "0x1a6,0x1a7", 5916 "MSRValue": "0x0400040400", 5917 "Offcore": "1", 5918 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5919 "SampleAfterValue": "100003", 5920 "UMask": "0x1" 5921 }, 5922 { 5923 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", 5924 "Counter": "0,1,2,3", 5925 "CounterHTOff": "0,1,2,3", 5926 "EventCode": "0xB7, 0xBB", 5927 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", 5928 "MSRIndex": "0x1a6,0x1a7", 5929 "MSRValue": "0x0100040400", 5930 "Offcore": "1", 5931 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5932 "SampleAfterValue": "100003", 5933 "UMask": "0x1" 5934 }, 5935 { 5936 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5937 "Counter": "0,1,2,3", 5938 "CounterHTOff": "0,1,2,3", 5939 "EventCode": "0xB7, 0xBB", 5940 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", 5941 "MSRIndex": "0x1a6,0x1a7", 5942 "MSRValue": "0x0200040400", 5943 "Offcore": "1", 5944 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5945 "SampleAfterValue": "100003", 5946 "UMask": "0x1" 5947 }, 5948 { 5949 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 5950 "Counter": "0,1,2,3", 5951 "CounterHTOff": "0,1,2,3", 5952 "EventCode": "0xB7, 0xBB", 5953 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", 5954 "MSRIndex": "0x1a6,0x1a7", 5955 "MSRValue": "0x0080040400", 5956 "Offcore": "1", 5957 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5958 "SampleAfterValue": "100003", 5959 "UMask": "0x1" 5960 }, 5961 { 5962 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", 5963 "Counter": "0,1,2,3", 5964 "CounterHTOff": "0,1,2,3", 5965 "EventCode": "0xB7, 0xBB", 5966 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", 5967 "MSRIndex": "0x1a6,0x1a7", 5968 "MSRValue": "0x3F80100400", 5969 "Offcore": "1", 5970 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5971 "SampleAfterValue": "100003", 5972 "UMask": "0x1" 5973 }, 5974 { 5975 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", 5976 "Counter": "0,1,2,3", 5977 "CounterHTOff": "0,1,2,3", 5978 "EventCode": "0xB7, 0xBB", 5979 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", 5980 "MSRIndex": "0x1a6,0x1a7", 5981 "MSRValue": "0x1000100400", 5982 "Offcore": "1", 5983 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5984 "SampleAfterValue": "100003", 5985 "UMask": "0x1" 5986 }, 5987 { 5988 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", 5989 "Counter": "0,1,2,3", 5990 "CounterHTOff": "0,1,2,3", 5991 "EventCode": "0xB7, 0xBB", 5992 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", 5993 "MSRIndex": "0x1a6,0x1a7", 5994 "MSRValue": "0x0800100400", 5995 "Offcore": "1", 5996 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 5997 "SampleAfterValue": "100003", 5998 "UMask": "0x1" 5999 }, 6000 { 6001 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6002 "Counter": "0,1,2,3", 6003 "CounterHTOff": "0,1,2,3", 6004 "EventCode": "0xB7, 0xBB", 6005 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6006 "MSRIndex": "0x1a6,0x1a7", 6007 "MSRValue": "0x0400100400", 6008 "Offcore": "1", 6009 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6010 "SampleAfterValue": "100003", 6011 "UMask": "0x1" 6012 }, 6013 { 6014 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", 6015 "Counter": "0,1,2,3", 6016 "CounterHTOff": "0,1,2,3", 6017 "EventCode": "0xB7, 0xBB", 6018 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", 6019 "MSRIndex": "0x1a6,0x1a7", 6020 "MSRValue": "0x0100100400", 6021 "Offcore": "1", 6022 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6023 "SampleAfterValue": "100003", 6024 "UMask": "0x1" 6025 }, 6026 { 6027 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 6028 "Counter": "0,1,2,3", 6029 "CounterHTOff": "0,1,2,3", 6030 "EventCode": "0xB7, 0xBB", 6031 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", 6032 "MSRIndex": "0x1a6,0x1a7", 6033 "MSRValue": "0x0200100400", 6034 "Offcore": "1", 6035 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6036 "SampleAfterValue": "100003", 6037 "UMask": "0x1" 6038 }, 6039 { 6040 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 6041 "Counter": "0,1,2,3", 6042 "CounterHTOff": "0,1,2,3", 6043 "EventCode": "0xB7, 0xBB", 6044 "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", 6045 "MSRIndex": "0x1a6,0x1a7", 6046 "MSRValue": "0x0080100400", 6047 "Offcore": "1", 6048 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6049 "SampleAfterValue": "100003", 6050 "UMask": "0x1" 6051 }, 6052 { 6053 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6054 "Counter": "0,1,2,3", 6055 "CounterHTOff": "0,1,2,3", 6056 "EventCode": "0xB7, 0xBB", 6057 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6058 "MSRIndex": "0x1a6,0x1a7", 6059 "MSRValue": "0x3F80400400", 6060 "Offcore": "1", 6061 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6062 "SampleAfterValue": "100003", 6063 "UMask": "0x1" 6064 }, 6065 { 6066 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 6067 "Counter": "0,1,2,3", 6068 "CounterHTOff": "0,1,2,3", 6069 "EventCode": "0xB7, 0xBB", 6070 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 6071 "MSRIndex": "0x1a6,0x1a7", 6072 "MSRValue": "0x0080400400", 6073 "Offcore": "1", 6074 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6075 "SampleAfterValue": "100003", 6076 "UMask": "0x1" 6077 }, 6078 { 6079 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6080 "Counter": "0,1,2,3", 6081 "CounterHTOff": "0,1,2,3", 6082 "EventCode": "0xB7, 0xBB", 6083 "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6084 "MSRIndex": "0x1a6,0x1a7", 6085 "MSRValue": "0x0100400400", 6086 "Offcore": "1", 6087 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6088 "SampleAfterValue": "100003", 6089 "UMask": "0x1" 6090 }, 6091 { 6092 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", 6093 "Counter": "0,1,2,3", 6094 "CounterHTOff": "0,1,2,3", 6095 "EventCode": "0xB7, 0xBB", 6096 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", 6097 "MSRIndex": "0x1a6,0x1a7", 6098 "MSRValue": "0x3F80020400", 6099 "Offcore": "1", 6100 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6101 "SampleAfterValue": "100003", 6102 "UMask": "0x1" 6103 }, 6104 { 6105 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", 6106 "Counter": "0,1,2,3", 6107 "CounterHTOff": "0,1,2,3", 6108 "EventCode": "0xB7, 0xBB", 6109 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", 6110 "MSRIndex": "0x1a6,0x1a7", 6111 "MSRValue": "0x1000020400", 6112 "Offcore": "1", 6113 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6114 "SampleAfterValue": "100003", 6115 "UMask": "0x1" 6116 }, 6117 { 6118 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6119 "Counter": "0,1,2,3", 6120 "CounterHTOff": "0,1,2,3", 6121 "EventCode": "0xB7, 0xBB", 6122 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6123 "MSRIndex": "0x1a6,0x1a7", 6124 "MSRValue": "0x0800020400", 6125 "Offcore": "1", 6126 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6127 "SampleAfterValue": "100003", 6128 "UMask": "0x1" 6129 }, 6130 { 6131 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6132 "Counter": "0,1,2,3", 6133 "CounterHTOff": "0,1,2,3", 6134 "EventCode": "0xB7, 0xBB", 6135 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6136 "MSRIndex": "0x1a6,0x1a7", 6137 "MSRValue": "0x0400020400", 6138 "Offcore": "1", 6139 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6140 "SampleAfterValue": "100003", 6141 "UMask": "0x1" 6142 }, 6143 { 6144 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6145 "Counter": "0,1,2,3", 6146 "CounterHTOff": "0,1,2,3", 6147 "EventCode": "0xB7, 0xBB", 6148 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6149 "MSRIndex": "0x1a6,0x1a7", 6150 "MSRValue": "0x0100020400", 6151 "Offcore": "1", 6152 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6153 "SampleAfterValue": "100003", 6154 "UMask": "0x1" 6155 }, 6156 { 6157 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 6158 "Counter": "0,1,2,3", 6159 "CounterHTOff": "0,1,2,3", 6160 "EventCode": "0xB7, 0xBB", 6161 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", 6162 "MSRIndex": "0x1a6,0x1a7", 6163 "MSRValue": "0x0200020400", 6164 "Offcore": "1", 6165 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6166 "SampleAfterValue": "100003", 6167 "UMask": "0x1" 6168 }, 6169 { 6170 "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", 6171 "Counter": "0,1,2,3", 6172 "CounterHTOff": "0,1,2,3", 6173 "EventCode": "0xB7, 0xBB", 6174 "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", 6175 "MSRIndex": "0x1a6,0x1a7", 6176 "MSRValue": "0x0080020400", 6177 "Offcore": "1", 6178 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6179 "SampleAfterValue": "100003", 6180 "UMask": "0x1" 6181 }, 6182 { 6183 "BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.", 6184 "Counter": "0,1,2,3", 6185 "CounterHTOff": "0,1,2,3", 6186 "EventCode": "0xB7, 0xBB", 6187 "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", 6188 "MSRIndex": "0x1a6,0x1a7", 6189 "MSRValue": "0x0000010010", 6190 "Offcore": "1", 6191 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6192 "SampleAfterValue": "100003", 6193 "UMask": "0x1" 6194 }, 6195 { 6196 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", 6197 "Counter": "0,1,2,3", 6198 "CounterHTOff": "0,1,2,3", 6199 "EventCode": "0xB7, 0xBB", 6200 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", 6201 "MSRIndex": "0x1a6,0x1a7", 6202 "MSRValue": "0x3F803C0010", 6203 "Offcore": "1", 6204 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6205 "SampleAfterValue": "100003", 6206 "UMask": "0x1" 6207 }, 6208 { 6209 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", 6210 "Counter": "0,1,2,3", 6211 "CounterHTOff": "0,1,2,3", 6212 "EventCode": "0xB7, 0xBB", 6213 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", 6214 "MSRIndex": "0x1a6,0x1a7", 6215 "MSRValue": "0x10003C0010", 6216 "Offcore": "1", 6217 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6218 "SampleAfterValue": "100003", 6219 "UMask": "0x1" 6220 }, 6221 { 6222 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 6223 "Counter": "0,1,2,3", 6224 "CounterHTOff": "0,1,2,3", 6225 "EventCode": "0xB7, 0xBB", 6226 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 6227 "MSRIndex": "0x1a6,0x1a7", 6228 "MSRValue": "0x08003C0010", 6229 "Offcore": "1", 6230 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6231 "SampleAfterValue": "100003", 6232 "UMask": "0x1" 6233 }, 6234 { 6235 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6236 "Counter": "0,1,2,3", 6237 "CounterHTOff": "0,1,2,3", 6238 "EventCode": "0xB7, 0xBB", 6239 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6240 "MSRIndex": "0x1a6,0x1a7", 6241 "MSRValue": "0x04003C0010", 6242 "Offcore": "1", 6243 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6244 "SampleAfterValue": "100003", 6245 "UMask": "0x1" 6246 }, 6247 { 6248 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 6249 "Counter": "0,1,2,3", 6250 "CounterHTOff": "0,1,2,3", 6251 "EventCode": "0xB7, 0xBB", 6252 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 6253 "MSRIndex": "0x1a6,0x1a7", 6254 "MSRValue": "0x01003C0010", 6255 "Offcore": "1", 6256 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6257 "SampleAfterValue": "100003", 6258 "UMask": "0x1" 6259 }, 6260 { 6261 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6262 "Counter": "0,1,2,3", 6263 "CounterHTOff": "0,1,2,3", 6264 "EventCode": "0xB7, 0xBB", 6265 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 6266 "MSRIndex": "0x1a6,0x1a7", 6267 "MSRValue": "0x08007C0010", 6268 "Offcore": "1", 6269 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6270 "SampleAfterValue": "100003", 6271 "UMask": "0x1" 6272 }, 6273 { 6274 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 6275 "Counter": "0,1,2,3", 6276 "CounterHTOff": "0,1,2,3", 6277 "EventCode": "0xB7, 0xBB", 6278 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 6279 "MSRIndex": "0x1a6,0x1a7", 6280 "MSRValue": "0x02003C0010", 6281 "Offcore": "1", 6282 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6283 "SampleAfterValue": "100003", 6284 "UMask": "0x1" 6285 }, 6286 { 6287 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", 6288 "Counter": "0,1,2,3", 6289 "CounterHTOff": "0,1,2,3", 6290 "EventCode": "0xB7, 0xBB", 6291 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", 6292 "MSRIndex": "0x1a6,0x1a7", 6293 "MSRValue": "0x00803C0010", 6294 "Offcore": "1", 6295 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6296 "SampleAfterValue": "100003", 6297 "UMask": "0x1" 6298 }, 6299 { 6300 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", 6301 "Counter": "0,1,2,3", 6302 "CounterHTOff": "0,1,2,3", 6303 "EventCode": "0xB7, 0xBB", 6304 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", 6305 "MSRIndex": "0x1a6,0x1a7", 6306 "MSRValue": "0x3F80080010", 6307 "Offcore": "1", 6308 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6309 "SampleAfterValue": "100003", 6310 "UMask": "0x1" 6311 }, 6312 { 6313 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 6314 "Counter": "0,1,2,3", 6315 "CounterHTOff": "0,1,2,3", 6316 "EventCode": "0xB7, 0xBB", 6317 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 6318 "MSRIndex": "0x1a6,0x1a7", 6319 "MSRValue": "0x1000080010", 6320 "Offcore": "1", 6321 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6322 "SampleAfterValue": "100003", 6323 "UMask": "0x1" 6324 }, 6325 { 6326 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 6327 "Counter": "0,1,2,3", 6328 "CounterHTOff": "0,1,2,3", 6329 "EventCode": "0xB7, 0xBB", 6330 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 6331 "MSRIndex": "0x1a6,0x1a7", 6332 "MSRValue": "0x0800080010", 6333 "Offcore": "1", 6334 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6335 "SampleAfterValue": "100003", 6336 "UMask": "0x1" 6337 }, 6338 { 6339 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6340 "Counter": "0,1,2,3", 6341 "CounterHTOff": "0,1,2,3", 6342 "EventCode": "0xB7, 0xBB", 6343 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6344 "MSRIndex": "0x1a6,0x1a7", 6345 "MSRValue": "0x0400080010", 6346 "Offcore": "1", 6347 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6348 "SampleAfterValue": "100003", 6349 "UMask": "0x1" 6350 }, 6351 { 6352 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 6353 "Counter": "0,1,2,3", 6354 "CounterHTOff": "0,1,2,3", 6355 "EventCode": "0xB7, 0xBB", 6356 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 6357 "MSRIndex": "0x1a6,0x1a7", 6358 "MSRValue": "0x0100080010", 6359 "Offcore": "1", 6360 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6361 "SampleAfterValue": "100003", 6362 "UMask": "0x1" 6363 }, 6364 { 6365 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6366 "Counter": "0,1,2,3", 6367 "CounterHTOff": "0,1,2,3", 6368 "EventCode": "0xB7, 0xBB", 6369 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", 6370 "MSRIndex": "0x1a6,0x1a7", 6371 "MSRValue": "0x0200080010", 6372 "Offcore": "1", 6373 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6374 "SampleAfterValue": "100003", 6375 "UMask": "0x1" 6376 }, 6377 { 6378 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6379 "Counter": "0,1,2,3", 6380 "CounterHTOff": "0,1,2,3", 6381 "EventCode": "0xB7, 0xBB", 6382 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", 6383 "MSRIndex": "0x1a6,0x1a7", 6384 "MSRValue": "0x0080080010", 6385 "Offcore": "1", 6386 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6387 "SampleAfterValue": "100003", 6388 "UMask": "0x1" 6389 }, 6390 { 6391 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", 6392 "Counter": "0,1,2,3", 6393 "CounterHTOff": "0,1,2,3", 6394 "EventCode": "0xB7, 0xBB", 6395 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", 6396 "MSRIndex": "0x1a6,0x1a7", 6397 "MSRValue": "0x3F80200010", 6398 "Offcore": "1", 6399 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6400 "SampleAfterValue": "100003", 6401 "UMask": "0x1" 6402 }, 6403 { 6404 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 6405 "Counter": "0,1,2,3", 6406 "CounterHTOff": "0,1,2,3", 6407 "EventCode": "0xB7, 0xBB", 6408 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 6409 "MSRIndex": "0x1a6,0x1a7", 6410 "MSRValue": "0x1000200010", 6411 "Offcore": "1", 6412 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6413 "SampleAfterValue": "100003", 6414 "UMask": "0x1" 6415 }, 6416 { 6417 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 6418 "Counter": "0,1,2,3", 6419 "CounterHTOff": "0,1,2,3", 6420 "EventCode": "0xB7, 0xBB", 6421 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 6422 "MSRIndex": "0x1a6,0x1a7", 6423 "MSRValue": "0x0800200010", 6424 "Offcore": "1", 6425 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6426 "SampleAfterValue": "100003", 6427 "UMask": "0x1" 6428 }, 6429 { 6430 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 6431 "Counter": "0,1,2,3", 6432 "CounterHTOff": "0,1,2,3", 6433 "EventCode": "0xB7, 0xBB", 6434 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 6435 "MSRIndex": "0x1a6,0x1a7", 6436 "MSRValue": "0x0400200010", 6437 "Offcore": "1", 6438 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6439 "SampleAfterValue": "100003", 6440 "UMask": "0x1" 6441 }, 6442 { 6443 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 6444 "Counter": "0,1,2,3", 6445 "CounterHTOff": "0,1,2,3", 6446 "EventCode": "0xB7, 0xBB", 6447 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 6448 "MSRIndex": "0x1a6,0x1a7", 6449 "MSRValue": "0x0100200010", 6450 "Offcore": "1", 6451 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6452 "SampleAfterValue": "100003", 6453 "UMask": "0x1" 6454 }, 6455 { 6456 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6457 "Counter": "0,1,2,3", 6458 "CounterHTOff": "0,1,2,3", 6459 "EventCode": "0xB7, 0xBB", 6460 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", 6461 "MSRIndex": "0x1a6,0x1a7", 6462 "MSRValue": "0x0200200010", 6463 "Offcore": "1", 6464 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6465 "SampleAfterValue": "100003", 6466 "UMask": "0x1" 6467 }, 6468 { 6469 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6470 "Counter": "0,1,2,3", 6471 "CounterHTOff": "0,1,2,3", 6472 "EventCode": "0xB7, 0xBB", 6473 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", 6474 "MSRIndex": "0x1a6,0x1a7", 6475 "MSRValue": "0x0080200010", 6476 "Offcore": "1", 6477 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6478 "SampleAfterValue": "100003", 6479 "UMask": "0x1" 6480 }, 6481 { 6482 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", 6483 "Counter": "0,1,2,3", 6484 "CounterHTOff": "0,1,2,3", 6485 "EventCode": "0xB7, 0xBB", 6486 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", 6487 "MSRIndex": "0x1a6,0x1a7", 6488 "MSRValue": "0x3F80040010", 6489 "Offcore": "1", 6490 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6491 "SampleAfterValue": "100003", 6492 "UMask": "0x1" 6493 }, 6494 { 6495 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 6496 "Counter": "0,1,2,3", 6497 "CounterHTOff": "0,1,2,3", 6498 "EventCode": "0xB7, 0xBB", 6499 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 6500 "MSRIndex": "0x1a6,0x1a7", 6501 "MSRValue": "0x1000040010", 6502 "Offcore": "1", 6503 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6504 "SampleAfterValue": "100003", 6505 "UMask": "0x1" 6506 }, 6507 { 6508 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 6509 "Counter": "0,1,2,3", 6510 "CounterHTOff": "0,1,2,3", 6511 "EventCode": "0xB7, 0xBB", 6512 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 6513 "MSRIndex": "0x1a6,0x1a7", 6514 "MSRValue": "0x0800040010", 6515 "Offcore": "1", 6516 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6517 "SampleAfterValue": "100003", 6518 "UMask": "0x1" 6519 }, 6520 { 6521 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 6522 "Counter": "0,1,2,3", 6523 "CounterHTOff": "0,1,2,3", 6524 "EventCode": "0xB7, 0xBB", 6525 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 6526 "MSRIndex": "0x1a6,0x1a7", 6527 "MSRValue": "0x0400040010", 6528 "Offcore": "1", 6529 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6530 "SampleAfterValue": "100003", 6531 "UMask": "0x1" 6532 }, 6533 { 6534 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 6535 "Counter": "0,1,2,3", 6536 "CounterHTOff": "0,1,2,3", 6537 "EventCode": "0xB7, 0xBB", 6538 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 6539 "MSRIndex": "0x1a6,0x1a7", 6540 "MSRValue": "0x0100040010", 6541 "Offcore": "1", 6542 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6543 "SampleAfterValue": "100003", 6544 "UMask": "0x1" 6545 }, 6546 { 6547 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6548 "Counter": "0,1,2,3", 6549 "CounterHTOff": "0,1,2,3", 6550 "EventCode": "0xB7, 0xBB", 6551 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", 6552 "MSRIndex": "0x1a6,0x1a7", 6553 "MSRValue": "0x0200040010", 6554 "Offcore": "1", 6555 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6556 "SampleAfterValue": "100003", 6557 "UMask": "0x1" 6558 }, 6559 { 6560 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6561 "Counter": "0,1,2,3", 6562 "CounterHTOff": "0,1,2,3", 6563 "EventCode": "0xB7, 0xBB", 6564 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", 6565 "MSRIndex": "0x1a6,0x1a7", 6566 "MSRValue": "0x0080040010", 6567 "Offcore": "1", 6568 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6569 "SampleAfterValue": "100003", 6570 "UMask": "0x1" 6571 }, 6572 { 6573 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", 6574 "Counter": "0,1,2,3", 6575 "CounterHTOff": "0,1,2,3", 6576 "EventCode": "0xB7, 0xBB", 6577 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", 6578 "MSRIndex": "0x1a6,0x1a7", 6579 "MSRValue": "0x3F80100010", 6580 "Offcore": "1", 6581 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6582 "SampleAfterValue": "100003", 6583 "UMask": "0x1" 6584 }, 6585 { 6586 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 6587 "Counter": "0,1,2,3", 6588 "CounterHTOff": "0,1,2,3", 6589 "EventCode": "0xB7, 0xBB", 6590 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 6591 "MSRIndex": "0x1a6,0x1a7", 6592 "MSRValue": "0x1000100010", 6593 "Offcore": "1", 6594 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6595 "SampleAfterValue": "100003", 6596 "UMask": "0x1" 6597 }, 6598 { 6599 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 6600 "Counter": "0,1,2,3", 6601 "CounterHTOff": "0,1,2,3", 6602 "EventCode": "0xB7, 0xBB", 6603 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 6604 "MSRIndex": "0x1a6,0x1a7", 6605 "MSRValue": "0x0800100010", 6606 "Offcore": "1", 6607 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6608 "SampleAfterValue": "100003", 6609 "UMask": "0x1" 6610 }, 6611 { 6612 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6613 "Counter": "0,1,2,3", 6614 "CounterHTOff": "0,1,2,3", 6615 "EventCode": "0xB7, 0xBB", 6616 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 6617 "MSRIndex": "0x1a6,0x1a7", 6618 "MSRValue": "0x0400100010", 6619 "Offcore": "1", 6620 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6621 "SampleAfterValue": "100003", 6622 "UMask": "0x1" 6623 }, 6624 { 6625 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 6626 "Counter": "0,1,2,3", 6627 "CounterHTOff": "0,1,2,3", 6628 "EventCode": "0xB7, 0xBB", 6629 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 6630 "MSRIndex": "0x1a6,0x1a7", 6631 "MSRValue": "0x0100100010", 6632 "Offcore": "1", 6633 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6634 "SampleAfterValue": "100003", 6635 "UMask": "0x1" 6636 }, 6637 { 6638 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6639 "Counter": "0,1,2,3", 6640 "CounterHTOff": "0,1,2,3", 6641 "EventCode": "0xB7, 0xBB", 6642 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", 6643 "MSRIndex": "0x1a6,0x1a7", 6644 "MSRValue": "0x0200100010", 6645 "Offcore": "1", 6646 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6647 "SampleAfterValue": "100003", 6648 "UMask": "0x1" 6649 }, 6650 { 6651 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6652 "Counter": "0,1,2,3", 6653 "CounterHTOff": "0,1,2,3", 6654 "EventCode": "0xB7, 0xBB", 6655 "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", 6656 "MSRIndex": "0x1a6,0x1a7", 6657 "MSRValue": "0x0080100010", 6658 "Offcore": "1", 6659 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6660 "SampleAfterValue": "100003", 6661 "UMask": "0x1" 6662 }, 6663 { 6664 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6665 "Counter": "0,1,2,3", 6666 "CounterHTOff": "0,1,2,3", 6667 "EventCode": "0xB7, 0xBB", 6668 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 6669 "MSRIndex": "0x1a6,0x1a7", 6670 "MSRValue": "0x3F80400010", 6671 "Offcore": "1", 6672 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6673 "SampleAfterValue": "100003", 6674 "UMask": "0x1" 6675 }, 6676 { 6677 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 6678 "Counter": "0,1,2,3", 6679 "CounterHTOff": "0,1,2,3", 6680 "EventCode": "0xB7, 0xBB", 6681 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 6682 "MSRIndex": "0x1a6,0x1a7", 6683 "MSRValue": "0x0080400010", 6684 "Offcore": "1", 6685 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6686 "SampleAfterValue": "100003", 6687 "UMask": "0x1" 6688 }, 6689 { 6690 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6691 "Counter": "0,1,2,3", 6692 "CounterHTOff": "0,1,2,3", 6693 "EventCode": "0xB7, 0xBB", 6694 "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 6695 "MSRIndex": "0x1a6,0x1a7", 6696 "MSRValue": "0x0100400010", 6697 "Offcore": "1", 6698 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6699 "SampleAfterValue": "100003", 6700 "UMask": "0x1" 6701 }, 6702 { 6703 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 6704 "Counter": "0,1,2,3", 6705 "CounterHTOff": "0,1,2,3", 6706 "EventCode": "0xB7, 0xBB", 6707 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 6708 "MSRIndex": "0x1a6,0x1a7", 6709 "MSRValue": "0x3F80020010", 6710 "Offcore": "1", 6711 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6712 "SampleAfterValue": "100003", 6713 "UMask": "0x1" 6714 }, 6715 { 6716 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 6717 "Counter": "0,1,2,3", 6718 "CounterHTOff": "0,1,2,3", 6719 "EventCode": "0xB7, 0xBB", 6720 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 6721 "MSRIndex": "0x1a6,0x1a7", 6722 "MSRValue": "0x1000020010", 6723 "Offcore": "1", 6724 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6725 "SampleAfterValue": "100003", 6726 "UMask": "0x1" 6727 }, 6728 { 6729 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6730 "Counter": "0,1,2,3", 6731 "CounterHTOff": "0,1,2,3", 6732 "EventCode": "0xB7, 0xBB", 6733 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 6734 "MSRIndex": "0x1a6,0x1a7", 6735 "MSRValue": "0x0800020010", 6736 "Offcore": "1", 6737 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6738 "SampleAfterValue": "100003", 6739 "UMask": "0x1" 6740 }, 6741 { 6742 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6743 "Counter": "0,1,2,3", 6744 "CounterHTOff": "0,1,2,3", 6745 "EventCode": "0xB7, 0xBB", 6746 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 6747 "MSRIndex": "0x1a6,0x1a7", 6748 "MSRValue": "0x0400020010", 6749 "Offcore": "1", 6750 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6751 "SampleAfterValue": "100003", 6752 "UMask": "0x1" 6753 }, 6754 { 6755 "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6756 "Counter": "0,1,2,3", 6757 "CounterHTOff": "0,1,2,3", 6758 "EventCode": "0xB7, 0xBB", 6759 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 6760 "MSRIndex": "0x1a6,0x1a7", 6761 "MSRValue": "0x0100020010", 6762 "Offcore": "1", 6763 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6764 "SampleAfterValue": "100003", 6765 "UMask": "0x1" 6766 }, 6767 { 6768 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6769 "Counter": "0,1,2,3", 6770 "CounterHTOff": "0,1,2,3", 6771 "EventCode": "0xB7, 0xBB", 6772 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 6773 "MSRIndex": "0x1a6,0x1a7", 6774 "MSRValue": "0x0200020010", 6775 "Offcore": "1", 6776 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6777 "SampleAfterValue": "100003", 6778 "UMask": "0x1" 6779 }, 6780 { 6781 "BriefDescription": "Counts prefetch (that bring data to L2) data reads", 6782 "Counter": "0,1,2,3", 6783 "CounterHTOff": "0,1,2,3", 6784 "EventCode": "0xB7, 0xBB", 6785 "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 6786 "MSRIndex": "0x1a6,0x1a7", 6787 "MSRValue": "0x0080020010", 6788 "Offcore": "1", 6789 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6790 "SampleAfterValue": "100003", 6791 "UMask": "0x1" 6792 }, 6793 { 6794 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.", 6795 "Counter": "0,1,2,3", 6796 "CounterHTOff": "0,1,2,3", 6797 "EventCode": "0xB7, 0xBB", 6798 "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", 6799 "MSRIndex": "0x1a6,0x1a7", 6800 "MSRValue": "0x0000010020", 6801 "Offcore": "1", 6802 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6803 "SampleAfterValue": "100003", 6804 "UMask": "0x1" 6805 }, 6806 { 6807 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", 6808 "Counter": "0,1,2,3", 6809 "CounterHTOff": "0,1,2,3", 6810 "EventCode": "0xB7, 0xBB", 6811 "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", 6812 "MSRIndex": "0x1a6,0x1a7", 6813 "MSRValue": "0x3F803C0020", 6814 "Offcore": "1", 6815 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6816 "SampleAfterValue": "100003", 6817 "UMask": "0x1" 6818 }, 6819 { 6820 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", 6821 "Counter": "0,1,2,3", 6822 "CounterHTOff": "0,1,2,3", 6823 "EventCode": "0xB7, 0xBB", 6824 "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", 6825 "MSRIndex": "0x1a6,0x1a7", 6826 "MSRValue": "0x10003C0020", 6827 "Offcore": "1", 6828 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6829 "SampleAfterValue": "100003", 6830 "UMask": "0x1" 6831 }, 6832 { 6833 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 6834 "Counter": "0,1,2,3", 6835 "CounterHTOff": "0,1,2,3", 6836 "EventCode": "0xB7, 0xBB", 6837 "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 6838 "MSRIndex": "0x1a6,0x1a7", 6839 "MSRValue": "0x08003C0020", 6840 "Offcore": "1", 6841 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6842 "SampleAfterValue": "100003", 6843 "UMask": "0x1" 6844 }, 6845 { 6846 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6847 "Counter": "0,1,2,3", 6848 "CounterHTOff": "0,1,2,3", 6849 "EventCode": "0xB7, 0xBB", 6850 "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 6851 "MSRIndex": "0x1a6,0x1a7", 6852 "MSRValue": "0x04003C0020", 6853 "Offcore": "1", 6854 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6855 "SampleAfterValue": "100003", 6856 "UMask": "0x1" 6857 }, 6858 { 6859 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", 6860 "Counter": "0,1,2,3", 6861 "CounterHTOff": "0,1,2,3", 6862 "EventCode": "0xB7, 0xBB", 6863 "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", 6864 "MSRIndex": "0x1a6,0x1a7", 6865 "MSRValue": "0x01003C0020", 6866 "Offcore": "1", 6867 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6868 "SampleAfterValue": "100003", 6869 "UMask": "0x1" 6870 }, 6871 { 6872 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6873 "Counter": "0,1,2,3", 6874 "CounterHTOff": "0,1,2,3", 6875 "EventCode": "0xB7, 0xBB", 6876 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 6877 "MSRIndex": "0x1a6,0x1a7", 6878 "MSRValue": "0x08007C0020", 6879 "Offcore": "1", 6880 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6881 "SampleAfterValue": "100003", 6882 "UMask": "0x1" 6883 }, 6884 { 6885 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", 6886 "Counter": "0,1,2,3", 6887 "CounterHTOff": "0,1,2,3", 6888 "EventCode": "0xB7, 0xBB", 6889 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", 6890 "MSRIndex": "0x1a6,0x1a7", 6891 "MSRValue": "0x02003C0020", 6892 "Offcore": "1", 6893 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6894 "SampleAfterValue": "100003", 6895 "UMask": "0x1" 6896 }, 6897 { 6898 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", 6899 "Counter": "0,1,2,3", 6900 "CounterHTOff": "0,1,2,3", 6901 "EventCode": "0xB7, 0xBB", 6902 "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", 6903 "MSRIndex": "0x1a6,0x1a7", 6904 "MSRValue": "0x00803C0020", 6905 "Offcore": "1", 6906 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6907 "SampleAfterValue": "100003", 6908 "UMask": "0x1" 6909 }, 6910 { 6911 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", 6912 "Counter": "0,1,2,3", 6913 "CounterHTOff": "0,1,2,3", 6914 "EventCode": "0xB7, 0xBB", 6915 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", 6916 "MSRIndex": "0x1a6,0x1a7", 6917 "MSRValue": "0x3F80080020", 6918 "Offcore": "1", 6919 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6920 "SampleAfterValue": "100003", 6921 "UMask": "0x1" 6922 }, 6923 { 6924 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", 6925 "Counter": "0,1,2,3", 6926 "CounterHTOff": "0,1,2,3", 6927 "EventCode": "0xB7, 0xBB", 6928 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", 6929 "MSRIndex": "0x1a6,0x1a7", 6930 "MSRValue": "0x1000080020", 6931 "Offcore": "1", 6932 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6933 "SampleAfterValue": "100003", 6934 "UMask": "0x1" 6935 }, 6936 { 6937 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 6938 "Counter": "0,1,2,3", 6939 "CounterHTOff": "0,1,2,3", 6940 "EventCode": "0xB7, 0xBB", 6941 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 6942 "MSRIndex": "0x1a6,0x1a7", 6943 "MSRValue": "0x0800080020", 6944 "Offcore": "1", 6945 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6946 "SampleAfterValue": "100003", 6947 "UMask": "0x1" 6948 }, 6949 { 6950 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6951 "Counter": "0,1,2,3", 6952 "CounterHTOff": "0,1,2,3", 6953 "EventCode": "0xB7, 0xBB", 6954 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 6955 "MSRIndex": "0x1a6,0x1a7", 6956 "MSRValue": "0x0400080020", 6957 "Offcore": "1", 6958 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6959 "SampleAfterValue": "100003", 6960 "UMask": "0x1" 6961 }, 6962 { 6963 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 6964 "Counter": "0,1,2,3", 6965 "CounterHTOff": "0,1,2,3", 6966 "EventCode": "0xB7, 0xBB", 6967 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 6968 "MSRIndex": "0x1a6,0x1a7", 6969 "MSRValue": "0x0100080020", 6970 "Offcore": "1", 6971 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6972 "SampleAfterValue": "100003", 6973 "UMask": "0x1" 6974 }, 6975 { 6976 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6977 "Counter": "0,1,2,3", 6978 "CounterHTOff": "0,1,2,3", 6979 "EventCode": "0xB7, 0xBB", 6980 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", 6981 "MSRIndex": "0x1a6,0x1a7", 6982 "MSRValue": "0x0200080020", 6983 "Offcore": "1", 6984 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6985 "SampleAfterValue": "100003", 6986 "UMask": "0x1" 6987 }, 6988 { 6989 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 6990 "Counter": "0,1,2,3", 6991 "CounterHTOff": "0,1,2,3", 6992 "EventCode": "0xB7, 0xBB", 6993 "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", 6994 "MSRIndex": "0x1a6,0x1a7", 6995 "MSRValue": "0x0080080020", 6996 "Offcore": "1", 6997 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 6998 "SampleAfterValue": "100003", 6999 "UMask": "0x1" 7000 }, 7001 { 7002 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", 7003 "Counter": "0,1,2,3", 7004 "CounterHTOff": "0,1,2,3", 7005 "EventCode": "0xB7, 0xBB", 7006 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", 7007 "MSRIndex": "0x1a6,0x1a7", 7008 "MSRValue": "0x3F80200020", 7009 "Offcore": "1", 7010 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7011 "SampleAfterValue": "100003", 7012 "UMask": "0x1" 7013 }, 7014 { 7015 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", 7016 "Counter": "0,1,2,3", 7017 "CounterHTOff": "0,1,2,3", 7018 "EventCode": "0xB7, 0xBB", 7019 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", 7020 "MSRIndex": "0x1a6,0x1a7", 7021 "MSRValue": "0x1000200020", 7022 "Offcore": "1", 7023 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7024 "SampleAfterValue": "100003", 7025 "UMask": "0x1" 7026 }, 7027 { 7028 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 7029 "Counter": "0,1,2,3", 7030 "CounterHTOff": "0,1,2,3", 7031 "EventCode": "0xB7, 0xBB", 7032 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 7033 "MSRIndex": "0x1a6,0x1a7", 7034 "MSRValue": "0x0800200020", 7035 "Offcore": "1", 7036 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7037 "SampleAfterValue": "100003", 7038 "UMask": "0x1" 7039 }, 7040 { 7041 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7042 "Counter": "0,1,2,3", 7043 "CounterHTOff": "0,1,2,3", 7044 "EventCode": "0xB7, 0xBB", 7045 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7046 "MSRIndex": "0x1a6,0x1a7", 7047 "MSRValue": "0x0400200020", 7048 "Offcore": "1", 7049 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7050 "SampleAfterValue": "100003", 7051 "UMask": "0x1" 7052 }, 7053 { 7054 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 7055 "Counter": "0,1,2,3", 7056 "CounterHTOff": "0,1,2,3", 7057 "EventCode": "0xB7, 0xBB", 7058 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 7059 "MSRIndex": "0x1a6,0x1a7", 7060 "MSRValue": "0x0100200020", 7061 "Offcore": "1", 7062 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7063 "SampleAfterValue": "100003", 7064 "UMask": "0x1" 7065 }, 7066 { 7067 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7068 "Counter": "0,1,2,3", 7069 "CounterHTOff": "0,1,2,3", 7070 "EventCode": "0xB7, 0xBB", 7071 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", 7072 "MSRIndex": "0x1a6,0x1a7", 7073 "MSRValue": "0x0200200020", 7074 "Offcore": "1", 7075 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7076 "SampleAfterValue": "100003", 7077 "UMask": "0x1" 7078 }, 7079 { 7080 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7081 "Counter": "0,1,2,3", 7082 "CounterHTOff": "0,1,2,3", 7083 "EventCode": "0xB7, 0xBB", 7084 "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", 7085 "MSRIndex": "0x1a6,0x1a7", 7086 "MSRValue": "0x0080200020", 7087 "Offcore": "1", 7088 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7089 "SampleAfterValue": "100003", 7090 "UMask": "0x1" 7091 }, 7092 { 7093 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", 7094 "Counter": "0,1,2,3", 7095 "CounterHTOff": "0,1,2,3", 7096 "EventCode": "0xB7, 0xBB", 7097 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", 7098 "MSRIndex": "0x1a6,0x1a7", 7099 "MSRValue": "0x3F80040020", 7100 "Offcore": "1", 7101 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7102 "SampleAfterValue": "100003", 7103 "UMask": "0x1" 7104 }, 7105 { 7106 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", 7107 "Counter": "0,1,2,3", 7108 "CounterHTOff": "0,1,2,3", 7109 "EventCode": "0xB7, 0xBB", 7110 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", 7111 "MSRIndex": "0x1a6,0x1a7", 7112 "MSRValue": "0x1000040020", 7113 "Offcore": "1", 7114 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7115 "SampleAfterValue": "100003", 7116 "UMask": "0x1" 7117 }, 7118 { 7119 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 7120 "Counter": "0,1,2,3", 7121 "CounterHTOff": "0,1,2,3", 7122 "EventCode": "0xB7, 0xBB", 7123 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 7124 "MSRIndex": "0x1a6,0x1a7", 7125 "MSRValue": "0x0800040020", 7126 "Offcore": "1", 7127 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7128 "SampleAfterValue": "100003", 7129 "UMask": "0x1" 7130 }, 7131 { 7132 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7133 "Counter": "0,1,2,3", 7134 "CounterHTOff": "0,1,2,3", 7135 "EventCode": "0xB7, 0xBB", 7136 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7137 "MSRIndex": "0x1a6,0x1a7", 7138 "MSRValue": "0x0400040020", 7139 "Offcore": "1", 7140 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7141 "SampleAfterValue": "100003", 7142 "UMask": "0x1" 7143 }, 7144 { 7145 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 7146 "Counter": "0,1,2,3", 7147 "CounterHTOff": "0,1,2,3", 7148 "EventCode": "0xB7, 0xBB", 7149 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 7150 "MSRIndex": "0x1a6,0x1a7", 7151 "MSRValue": "0x0100040020", 7152 "Offcore": "1", 7153 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7154 "SampleAfterValue": "100003", 7155 "UMask": "0x1" 7156 }, 7157 { 7158 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7159 "Counter": "0,1,2,3", 7160 "CounterHTOff": "0,1,2,3", 7161 "EventCode": "0xB7, 0xBB", 7162 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", 7163 "MSRIndex": "0x1a6,0x1a7", 7164 "MSRValue": "0x0200040020", 7165 "Offcore": "1", 7166 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7167 "SampleAfterValue": "100003", 7168 "UMask": "0x1" 7169 }, 7170 { 7171 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7172 "Counter": "0,1,2,3", 7173 "CounterHTOff": "0,1,2,3", 7174 "EventCode": "0xB7, 0xBB", 7175 "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", 7176 "MSRIndex": "0x1a6,0x1a7", 7177 "MSRValue": "0x0080040020", 7178 "Offcore": "1", 7179 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7180 "SampleAfterValue": "100003", 7181 "UMask": "0x1" 7182 }, 7183 { 7184 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", 7185 "Counter": "0,1,2,3", 7186 "CounterHTOff": "0,1,2,3", 7187 "EventCode": "0xB7, 0xBB", 7188 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", 7189 "MSRIndex": "0x1a6,0x1a7", 7190 "MSRValue": "0x3F80100020", 7191 "Offcore": "1", 7192 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7193 "SampleAfterValue": "100003", 7194 "UMask": "0x1" 7195 }, 7196 { 7197 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", 7198 "Counter": "0,1,2,3", 7199 "CounterHTOff": "0,1,2,3", 7200 "EventCode": "0xB7, 0xBB", 7201 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", 7202 "MSRIndex": "0x1a6,0x1a7", 7203 "MSRValue": "0x1000100020", 7204 "Offcore": "1", 7205 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7206 "SampleAfterValue": "100003", 7207 "UMask": "0x1" 7208 }, 7209 { 7210 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7211 "Counter": "0,1,2,3", 7212 "CounterHTOff": "0,1,2,3", 7213 "EventCode": "0xB7, 0xBB", 7214 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 7215 "MSRIndex": "0x1a6,0x1a7", 7216 "MSRValue": "0x0800100020", 7217 "Offcore": "1", 7218 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7219 "SampleAfterValue": "100003", 7220 "UMask": "0x1" 7221 }, 7222 { 7223 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7224 "Counter": "0,1,2,3", 7225 "CounterHTOff": "0,1,2,3", 7226 "EventCode": "0xB7, 0xBB", 7227 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7228 "MSRIndex": "0x1a6,0x1a7", 7229 "MSRValue": "0x0400100020", 7230 "Offcore": "1", 7231 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7232 "SampleAfterValue": "100003", 7233 "UMask": "0x1" 7234 }, 7235 { 7236 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 7237 "Counter": "0,1,2,3", 7238 "CounterHTOff": "0,1,2,3", 7239 "EventCode": "0xB7, 0xBB", 7240 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 7241 "MSRIndex": "0x1a6,0x1a7", 7242 "MSRValue": "0x0100100020", 7243 "Offcore": "1", 7244 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7245 "SampleAfterValue": "100003", 7246 "UMask": "0x1" 7247 }, 7248 { 7249 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7250 "Counter": "0,1,2,3", 7251 "CounterHTOff": "0,1,2,3", 7252 "EventCode": "0xB7, 0xBB", 7253 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", 7254 "MSRIndex": "0x1a6,0x1a7", 7255 "MSRValue": "0x0200100020", 7256 "Offcore": "1", 7257 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7258 "SampleAfterValue": "100003", 7259 "UMask": "0x1" 7260 }, 7261 { 7262 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7263 "Counter": "0,1,2,3", 7264 "CounterHTOff": "0,1,2,3", 7265 "EventCode": "0xB7, 0xBB", 7266 "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", 7267 "MSRIndex": "0x1a6,0x1a7", 7268 "MSRValue": "0x0080100020", 7269 "Offcore": "1", 7270 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7271 "SampleAfterValue": "100003", 7272 "UMask": "0x1" 7273 }, 7274 { 7275 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 7276 "Counter": "0,1,2,3", 7277 "CounterHTOff": "0,1,2,3", 7278 "EventCode": "0xB7, 0xBB", 7279 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 7280 "MSRIndex": "0x1a6,0x1a7", 7281 "MSRValue": "0x3F80400020", 7282 "Offcore": "1", 7283 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7284 "SampleAfterValue": "100003", 7285 "UMask": "0x1" 7286 }, 7287 { 7288 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 7289 "Counter": "0,1,2,3", 7290 "CounterHTOff": "0,1,2,3", 7291 "EventCode": "0xB7, 0xBB", 7292 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 7293 "MSRIndex": "0x1a6,0x1a7", 7294 "MSRValue": "0x0080400020", 7295 "Offcore": "1", 7296 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7297 "SampleAfterValue": "100003", 7298 "UMask": "0x1" 7299 }, 7300 { 7301 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 7302 "Counter": "0,1,2,3", 7303 "CounterHTOff": "0,1,2,3", 7304 "EventCode": "0xB7, 0xBB", 7305 "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 7306 "MSRIndex": "0x1a6,0x1a7", 7307 "MSRValue": "0x0100400020", 7308 "Offcore": "1", 7309 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7310 "SampleAfterValue": "100003", 7311 "UMask": "0x1" 7312 }, 7313 { 7314 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", 7315 "Counter": "0,1,2,3", 7316 "CounterHTOff": "0,1,2,3", 7317 "EventCode": "0xB7, 0xBB", 7318 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", 7319 "MSRIndex": "0x1a6,0x1a7", 7320 "MSRValue": "0x3F80020020", 7321 "Offcore": "1", 7322 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7323 "SampleAfterValue": "100003", 7324 "UMask": "0x1" 7325 }, 7326 { 7327 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 7328 "Counter": "0,1,2,3", 7329 "CounterHTOff": "0,1,2,3", 7330 "EventCode": "0xB7, 0xBB", 7331 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 7332 "MSRIndex": "0x1a6,0x1a7", 7333 "MSRValue": "0x1000020020", 7334 "Offcore": "1", 7335 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7336 "SampleAfterValue": "100003", 7337 "UMask": "0x1" 7338 }, 7339 { 7340 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7341 "Counter": "0,1,2,3", 7342 "CounterHTOff": "0,1,2,3", 7343 "EventCode": "0xB7, 0xBB", 7344 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7345 "MSRIndex": "0x1a6,0x1a7", 7346 "MSRValue": "0x0800020020", 7347 "Offcore": "1", 7348 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7349 "SampleAfterValue": "100003", 7350 "UMask": "0x1" 7351 }, 7352 { 7353 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7354 "Counter": "0,1,2,3", 7355 "CounterHTOff": "0,1,2,3", 7356 "EventCode": "0xB7, 0xBB", 7357 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7358 "MSRIndex": "0x1a6,0x1a7", 7359 "MSRValue": "0x0400020020", 7360 "Offcore": "1", 7361 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7362 "SampleAfterValue": "100003", 7363 "UMask": "0x1" 7364 }, 7365 { 7366 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7367 "Counter": "0,1,2,3", 7368 "CounterHTOff": "0,1,2,3", 7369 "EventCode": "0xB7, 0xBB", 7370 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7371 "MSRIndex": "0x1a6,0x1a7", 7372 "MSRValue": "0x0100020020", 7373 "Offcore": "1", 7374 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7375 "SampleAfterValue": "100003", 7376 "UMask": "0x1" 7377 }, 7378 { 7379 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7380 "Counter": "0,1,2,3", 7381 "CounterHTOff": "0,1,2,3", 7382 "EventCode": "0xB7, 0xBB", 7383 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", 7384 "MSRIndex": "0x1a6,0x1a7", 7385 "MSRValue": "0x0200020020", 7386 "Offcore": "1", 7387 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7388 "SampleAfterValue": "100003", 7389 "UMask": "0x1" 7390 }, 7391 { 7392 "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", 7393 "Counter": "0,1,2,3", 7394 "CounterHTOff": "0,1,2,3", 7395 "EventCode": "0xB7, 0xBB", 7396 "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", 7397 "MSRIndex": "0x1a6,0x1a7", 7398 "MSRValue": "0x0080020020", 7399 "Offcore": "1", 7400 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7401 "SampleAfterValue": "100003", 7402 "UMask": "0x1" 7403 }, 7404 { 7405 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", 7406 "Counter": "0,1,2,3", 7407 "CounterHTOff": "0,1,2,3", 7408 "EventCode": "0xB7, 0xBB", 7409 "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", 7410 "MSRIndex": "0x1a6,0x1a7", 7411 "MSRValue": "0x0000010080", 7412 "Offcore": "1", 7413 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7414 "SampleAfterValue": "100003", 7415 "UMask": "0x1" 7416 }, 7417 { 7418 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", 7419 "Counter": "0,1,2,3", 7420 "CounterHTOff": "0,1,2,3", 7421 "EventCode": "0xB7, 0xBB", 7422 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", 7423 "MSRIndex": "0x1a6,0x1a7", 7424 "MSRValue": "0x3F803C0080", 7425 "Offcore": "1", 7426 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7427 "SampleAfterValue": "100003", 7428 "UMask": "0x1" 7429 }, 7430 { 7431 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", 7432 "Counter": "0,1,2,3", 7433 "CounterHTOff": "0,1,2,3", 7434 "EventCode": "0xB7, 0xBB", 7435 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", 7436 "MSRIndex": "0x1a6,0x1a7", 7437 "MSRValue": "0x10003C0080", 7438 "Offcore": "1", 7439 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7440 "SampleAfterValue": "100003", 7441 "UMask": "0x1" 7442 }, 7443 { 7444 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 7445 "Counter": "0,1,2,3", 7446 "CounterHTOff": "0,1,2,3", 7447 "EventCode": "0xB7, 0xBB", 7448 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", 7449 "MSRIndex": "0x1a6,0x1a7", 7450 "MSRValue": "0x08003C0080", 7451 "Offcore": "1", 7452 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7453 "SampleAfterValue": "100003", 7454 "UMask": "0x1" 7455 }, 7456 { 7457 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 7458 "Counter": "0,1,2,3", 7459 "CounterHTOff": "0,1,2,3", 7460 "EventCode": "0xB7, 0xBB", 7461 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", 7462 "MSRIndex": "0x1a6,0x1a7", 7463 "MSRValue": "0x04003C0080", 7464 "Offcore": "1", 7465 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7466 "SampleAfterValue": "100003", 7467 "UMask": "0x1" 7468 }, 7469 { 7470 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7471 "Counter": "0,1,2,3", 7472 "CounterHTOff": "0,1,2,3", 7473 "EventCode": "0xB7, 0xBB", 7474 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", 7475 "MSRIndex": "0x1a6,0x1a7", 7476 "MSRValue": "0x01003C0080", 7477 "Offcore": "1", 7478 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7479 "SampleAfterValue": "100003", 7480 "UMask": "0x1" 7481 }, 7482 { 7483 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7484 "Counter": "0,1,2,3", 7485 "CounterHTOff": "0,1,2,3", 7486 "EventCode": "0xB7, 0xBB", 7487 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 7488 "MSRIndex": "0x1a6,0x1a7", 7489 "MSRValue": "0x08007C0080", 7490 "Offcore": "1", 7491 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7492 "SampleAfterValue": "100003", 7493 "UMask": "0x1" 7494 }, 7495 { 7496 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", 7497 "Counter": "0,1,2,3", 7498 "CounterHTOff": "0,1,2,3", 7499 "EventCode": "0xB7, 0xBB", 7500 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", 7501 "MSRIndex": "0x1a6,0x1a7", 7502 "MSRValue": "0x02003C0080", 7503 "Offcore": "1", 7504 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7505 "SampleAfterValue": "100003", 7506 "UMask": "0x1" 7507 }, 7508 { 7509 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", 7510 "Counter": "0,1,2,3", 7511 "CounterHTOff": "0,1,2,3", 7512 "EventCode": "0xB7, 0xBB", 7513 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", 7514 "MSRIndex": "0x1a6,0x1a7", 7515 "MSRValue": "0x00803C0080", 7516 "Offcore": "1", 7517 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7518 "SampleAfterValue": "100003", 7519 "UMask": "0x1" 7520 }, 7521 { 7522 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", 7523 "Counter": "0,1,2,3", 7524 "CounterHTOff": "0,1,2,3", 7525 "EventCode": "0xB7, 0xBB", 7526 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", 7527 "MSRIndex": "0x1a6,0x1a7", 7528 "MSRValue": "0x3F80080080", 7529 "Offcore": "1", 7530 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7531 "SampleAfterValue": "100003", 7532 "UMask": "0x1" 7533 }, 7534 { 7535 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 7536 "Counter": "0,1,2,3", 7537 "CounterHTOff": "0,1,2,3", 7538 "EventCode": "0xB7, 0xBB", 7539 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", 7540 "MSRIndex": "0x1a6,0x1a7", 7541 "MSRValue": "0x1000080080", 7542 "Offcore": "1", 7543 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7544 "SampleAfterValue": "100003", 7545 "UMask": "0x1" 7546 }, 7547 { 7548 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 7549 "Counter": "0,1,2,3", 7550 "CounterHTOff": "0,1,2,3", 7551 "EventCode": "0xB7, 0xBB", 7552 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", 7553 "MSRIndex": "0x1a6,0x1a7", 7554 "MSRValue": "0x0800080080", 7555 "Offcore": "1", 7556 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7557 "SampleAfterValue": "100003", 7558 "UMask": "0x1" 7559 }, 7560 { 7561 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7562 "Counter": "0,1,2,3", 7563 "CounterHTOff": "0,1,2,3", 7564 "EventCode": "0xB7, 0xBB", 7565 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 7566 "MSRIndex": "0x1a6,0x1a7", 7567 "MSRValue": "0x0400080080", 7568 "Offcore": "1", 7569 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7570 "SampleAfterValue": "100003", 7571 "UMask": "0x1" 7572 }, 7573 { 7574 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 7575 "Counter": "0,1,2,3", 7576 "CounterHTOff": "0,1,2,3", 7577 "EventCode": "0xB7, 0xBB", 7578 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", 7579 "MSRIndex": "0x1a6,0x1a7", 7580 "MSRValue": "0x0100080080", 7581 "Offcore": "1", 7582 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7583 "SampleAfterValue": "100003", 7584 "UMask": "0x1" 7585 }, 7586 { 7587 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7588 "Counter": "0,1,2,3", 7589 "CounterHTOff": "0,1,2,3", 7590 "EventCode": "0xB7, 0xBB", 7591 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", 7592 "MSRIndex": "0x1a6,0x1a7", 7593 "MSRValue": "0x0200080080", 7594 "Offcore": "1", 7595 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7596 "SampleAfterValue": "100003", 7597 "UMask": "0x1" 7598 }, 7599 { 7600 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7601 "Counter": "0,1,2,3", 7602 "CounterHTOff": "0,1,2,3", 7603 "EventCode": "0xB7, 0xBB", 7604 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", 7605 "MSRIndex": "0x1a6,0x1a7", 7606 "MSRValue": "0x0080080080", 7607 "Offcore": "1", 7608 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7609 "SampleAfterValue": "100003", 7610 "UMask": "0x1" 7611 }, 7612 { 7613 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", 7614 "Counter": "0,1,2,3", 7615 "CounterHTOff": "0,1,2,3", 7616 "EventCode": "0xB7, 0xBB", 7617 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", 7618 "MSRIndex": "0x1a6,0x1a7", 7619 "MSRValue": "0x3F80200080", 7620 "Offcore": "1", 7621 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7622 "SampleAfterValue": "100003", 7623 "UMask": "0x1" 7624 }, 7625 { 7626 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 7627 "Counter": "0,1,2,3", 7628 "CounterHTOff": "0,1,2,3", 7629 "EventCode": "0xB7, 0xBB", 7630 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", 7631 "MSRIndex": "0x1a6,0x1a7", 7632 "MSRValue": "0x1000200080", 7633 "Offcore": "1", 7634 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7635 "SampleAfterValue": "100003", 7636 "UMask": "0x1" 7637 }, 7638 { 7639 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 7640 "Counter": "0,1,2,3", 7641 "CounterHTOff": "0,1,2,3", 7642 "EventCode": "0xB7, 0xBB", 7643 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", 7644 "MSRIndex": "0x1a6,0x1a7", 7645 "MSRValue": "0x0800200080", 7646 "Offcore": "1", 7647 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7648 "SampleAfterValue": "100003", 7649 "UMask": "0x1" 7650 }, 7651 { 7652 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7653 "Counter": "0,1,2,3", 7654 "CounterHTOff": "0,1,2,3", 7655 "EventCode": "0xB7, 0xBB", 7656 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 7657 "MSRIndex": "0x1a6,0x1a7", 7658 "MSRValue": "0x0400200080", 7659 "Offcore": "1", 7660 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7661 "SampleAfterValue": "100003", 7662 "UMask": "0x1" 7663 }, 7664 { 7665 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 7666 "Counter": "0,1,2,3", 7667 "CounterHTOff": "0,1,2,3", 7668 "EventCode": "0xB7, 0xBB", 7669 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", 7670 "MSRIndex": "0x1a6,0x1a7", 7671 "MSRValue": "0x0100200080", 7672 "Offcore": "1", 7673 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7674 "SampleAfterValue": "100003", 7675 "UMask": "0x1" 7676 }, 7677 { 7678 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7679 "Counter": "0,1,2,3", 7680 "CounterHTOff": "0,1,2,3", 7681 "EventCode": "0xB7, 0xBB", 7682 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", 7683 "MSRIndex": "0x1a6,0x1a7", 7684 "MSRValue": "0x0200200080", 7685 "Offcore": "1", 7686 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7687 "SampleAfterValue": "100003", 7688 "UMask": "0x1" 7689 }, 7690 { 7691 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7692 "Counter": "0,1,2,3", 7693 "CounterHTOff": "0,1,2,3", 7694 "EventCode": "0xB7, 0xBB", 7695 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", 7696 "MSRIndex": "0x1a6,0x1a7", 7697 "MSRValue": "0x0080200080", 7698 "Offcore": "1", 7699 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7700 "SampleAfterValue": "100003", 7701 "UMask": "0x1" 7702 }, 7703 { 7704 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", 7705 "Counter": "0,1,2,3", 7706 "CounterHTOff": "0,1,2,3", 7707 "EventCode": "0xB7, 0xBB", 7708 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", 7709 "MSRIndex": "0x1a6,0x1a7", 7710 "MSRValue": "0x3F80040080", 7711 "Offcore": "1", 7712 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7713 "SampleAfterValue": "100003", 7714 "UMask": "0x1" 7715 }, 7716 { 7717 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 7718 "Counter": "0,1,2,3", 7719 "CounterHTOff": "0,1,2,3", 7720 "EventCode": "0xB7, 0xBB", 7721 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", 7722 "MSRIndex": "0x1a6,0x1a7", 7723 "MSRValue": "0x1000040080", 7724 "Offcore": "1", 7725 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7726 "SampleAfterValue": "100003", 7727 "UMask": "0x1" 7728 }, 7729 { 7730 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 7731 "Counter": "0,1,2,3", 7732 "CounterHTOff": "0,1,2,3", 7733 "EventCode": "0xB7, 0xBB", 7734 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", 7735 "MSRIndex": "0x1a6,0x1a7", 7736 "MSRValue": "0x0800040080", 7737 "Offcore": "1", 7738 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7739 "SampleAfterValue": "100003", 7740 "UMask": "0x1" 7741 }, 7742 { 7743 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7744 "Counter": "0,1,2,3", 7745 "CounterHTOff": "0,1,2,3", 7746 "EventCode": "0xB7, 0xBB", 7747 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 7748 "MSRIndex": "0x1a6,0x1a7", 7749 "MSRValue": "0x0400040080", 7750 "Offcore": "1", 7751 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7752 "SampleAfterValue": "100003", 7753 "UMask": "0x1" 7754 }, 7755 { 7756 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 7757 "Counter": "0,1,2,3", 7758 "CounterHTOff": "0,1,2,3", 7759 "EventCode": "0xB7, 0xBB", 7760 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", 7761 "MSRIndex": "0x1a6,0x1a7", 7762 "MSRValue": "0x0100040080", 7763 "Offcore": "1", 7764 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7765 "SampleAfterValue": "100003", 7766 "UMask": "0x1" 7767 }, 7768 { 7769 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7770 "Counter": "0,1,2,3", 7771 "CounterHTOff": "0,1,2,3", 7772 "EventCode": "0xB7, 0xBB", 7773 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", 7774 "MSRIndex": "0x1a6,0x1a7", 7775 "MSRValue": "0x0200040080", 7776 "Offcore": "1", 7777 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7778 "SampleAfterValue": "100003", 7779 "UMask": "0x1" 7780 }, 7781 { 7782 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7783 "Counter": "0,1,2,3", 7784 "CounterHTOff": "0,1,2,3", 7785 "EventCode": "0xB7, 0xBB", 7786 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", 7787 "MSRIndex": "0x1a6,0x1a7", 7788 "MSRValue": "0x0080040080", 7789 "Offcore": "1", 7790 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7791 "SampleAfterValue": "100003", 7792 "UMask": "0x1" 7793 }, 7794 { 7795 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", 7796 "Counter": "0,1,2,3", 7797 "CounterHTOff": "0,1,2,3", 7798 "EventCode": "0xB7, 0xBB", 7799 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", 7800 "MSRIndex": "0x1a6,0x1a7", 7801 "MSRValue": "0x3F80100080", 7802 "Offcore": "1", 7803 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7804 "SampleAfterValue": "100003", 7805 "UMask": "0x1" 7806 }, 7807 { 7808 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 7809 "Counter": "0,1,2,3", 7810 "CounterHTOff": "0,1,2,3", 7811 "EventCode": "0xB7, 0xBB", 7812 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", 7813 "MSRIndex": "0x1a6,0x1a7", 7814 "MSRValue": "0x1000100080", 7815 "Offcore": "1", 7816 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7817 "SampleAfterValue": "100003", 7818 "UMask": "0x1" 7819 }, 7820 { 7821 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 7822 "Counter": "0,1,2,3", 7823 "CounterHTOff": "0,1,2,3", 7824 "EventCode": "0xB7, 0xBB", 7825 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", 7826 "MSRIndex": "0x1a6,0x1a7", 7827 "MSRValue": "0x0800100080", 7828 "Offcore": "1", 7829 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7830 "SampleAfterValue": "100003", 7831 "UMask": "0x1" 7832 }, 7833 { 7834 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7835 "Counter": "0,1,2,3", 7836 "CounterHTOff": "0,1,2,3", 7837 "EventCode": "0xB7, 0xBB", 7838 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 7839 "MSRIndex": "0x1a6,0x1a7", 7840 "MSRValue": "0x0400100080", 7841 "Offcore": "1", 7842 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7843 "SampleAfterValue": "100003", 7844 "UMask": "0x1" 7845 }, 7846 { 7847 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 7848 "Counter": "0,1,2,3", 7849 "CounterHTOff": "0,1,2,3", 7850 "EventCode": "0xB7, 0xBB", 7851 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", 7852 "MSRIndex": "0x1a6,0x1a7", 7853 "MSRValue": "0x0100100080", 7854 "Offcore": "1", 7855 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7856 "SampleAfterValue": "100003", 7857 "UMask": "0x1" 7858 }, 7859 { 7860 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7861 "Counter": "0,1,2,3", 7862 "CounterHTOff": "0,1,2,3", 7863 "EventCode": "0xB7, 0xBB", 7864 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", 7865 "MSRIndex": "0x1a6,0x1a7", 7866 "MSRValue": "0x0200100080", 7867 "Offcore": "1", 7868 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7869 "SampleAfterValue": "100003", 7870 "UMask": "0x1" 7871 }, 7872 { 7873 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7874 "Counter": "0,1,2,3", 7875 "CounterHTOff": "0,1,2,3", 7876 "EventCode": "0xB7, 0xBB", 7877 "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", 7878 "MSRIndex": "0x1a6,0x1a7", 7879 "MSRValue": "0x0080100080", 7880 "Offcore": "1", 7881 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7882 "SampleAfterValue": "100003", 7883 "UMask": "0x1" 7884 }, 7885 { 7886 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 7887 "Counter": "0,1,2,3", 7888 "CounterHTOff": "0,1,2,3", 7889 "EventCode": "0xB7, 0xBB", 7890 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 7891 "MSRIndex": "0x1a6,0x1a7", 7892 "MSRValue": "0x3F80400080", 7893 "Offcore": "1", 7894 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7895 "SampleAfterValue": "100003", 7896 "UMask": "0x1" 7897 }, 7898 { 7899 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 7900 "Counter": "0,1,2,3", 7901 "CounterHTOff": "0,1,2,3", 7902 "EventCode": "0xB7, 0xBB", 7903 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 7904 "MSRIndex": "0x1a6,0x1a7", 7905 "MSRValue": "0x0080400080", 7906 "Offcore": "1", 7907 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7908 "SampleAfterValue": "100003", 7909 "UMask": "0x1" 7910 }, 7911 { 7912 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 7913 "Counter": "0,1,2,3", 7914 "CounterHTOff": "0,1,2,3", 7915 "EventCode": "0xB7, 0xBB", 7916 "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 7917 "MSRIndex": "0x1a6,0x1a7", 7918 "MSRValue": "0x0100400080", 7919 "Offcore": "1", 7920 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7921 "SampleAfterValue": "100003", 7922 "UMask": "0x1" 7923 }, 7924 { 7925 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 7926 "Counter": "0,1,2,3", 7927 "CounterHTOff": "0,1,2,3", 7928 "EventCode": "0xB7, 0xBB", 7929 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", 7930 "MSRIndex": "0x1a6,0x1a7", 7931 "MSRValue": "0x3F80020080", 7932 "Offcore": "1", 7933 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7934 "SampleAfterValue": "100003", 7935 "UMask": "0x1" 7936 }, 7937 { 7938 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 7939 "Counter": "0,1,2,3", 7940 "CounterHTOff": "0,1,2,3", 7941 "EventCode": "0xB7, 0xBB", 7942 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", 7943 "MSRIndex": "0x1a6,0x1a7", 7944 "MSRValue": "0x1000020080", 7945 "Offcore": "1", 7946 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7947 "SampleAfterValue": "100003", 7948 "UMask": "0x1" 7949 }, 7950 { 7951 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7952 "Counter": "0,1,2,3", 7953 "CounterHTOff": "0,1,2,3", 7954 "EventCode": "0xB7, 0xBB", 7955 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 7956 "MSRIndex": "0x1a6,0x1a7", 7957 "MSRValue": "0x0800020080", 7958 "Offcore": "1", 7959 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7960 "SampleAfterValue": "100003", 7961 "UMask": "0x1" 7962 }, 7963 { 7964 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7965 "Counter": "0,1,2,3", 7966 "CounterHTOff": "0,1,2,3", 7967 "EventCode": "0xB7, 0xBB", 7968 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 7969 "MSRIndex": "0x1a6,0x1a7", 7970 "MSRValue": "0x0400020080", 7971 "Offcore": "1", 7972 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7973 "SampleAfterValue": "100003", 7974 "UMask": "0x1" 7975 }, 7976 { 7977 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7978 "Counter": "0,1,2,3", 7979 "CounterHTOff": "0,1,2,3", 7980 "EventCode": "0xB7, 0xBB", 7981 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", 7982 "MSRIndex": "0x1a6,0x1a7", 7983 "MSRValue": "0x0100020080", 7984 "Offcore": "1", 7985 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7986 "SampleAfterValue": "100003", 7987 "UMask": "0x1" 7988 }, 7989 { 7990 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 7991 "Counter": "0,1,2,3", 7992 "CounterHTOff": "0,1,2,3", 7993 "EventCode": "0xB7, 0xBB", 7994 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", 7995 "MSRIndex": "0x1a6,0x1a7", 7996 "MSRValue": "0x0200020080", 7997 "Offcore": "1", 7998 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 7999 "SampleAfterValue": "100003", 8000 "UMask": "0x1" 8001 }, 8002 { 8003 "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", 8004 "Counter": "0,1,2,3", 8005 "CounterHTOff": "0,1,2,3", 8006 "EventCode": "0xB7, 0xBB", 8007 "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", 8008 "MSRIndex": "0x1a6,0x1a7", 8009 "MSRValue": "0x0080020080", 8010 "Offcore": "1", 8011 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8012 "SampleAfterValue": "100003", 8013 "UMask": "0x1" 8014 }, 8015 { 8016 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", 8017 "Counter": "0,1,2,3", 8018 "CounterHTOff": "0,1,2,3", 8019 "EventCode": "0xB7, 0xBB", 8020 "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", 8021 "MSRIndex": "0x1a6,0x1a7", 8022 "MSRValue": "0x0000010100", 8023 "Offcore": "1", 8024 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8025 "SampleAfterValue": "100003", 8026 "UMask": "0x1" 8027 }, 8028 { 8029 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", 8030 "Counter": "0,1,2,3", 8031 "CounterHTOff": "0,1,2,3", 8032 "EventCode": "0xB7, 0xBB", 8033 "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", 8034 "MSRIndex": "0x1a6,0x1a7", 8035 "MSRValue": "0x3F803C0100", 8036 "Offcore": "1", 8037 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8038 "SampleAfterValue": "100003", 8039 "UMask": "0x1" 8040 }, 8041 { 8042 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", 8043 "Counter": "0,1,2,3", 8044 "CounterHTOff": "0,1,2,3", 8045 "EventCode": "0xB7, 0xBB", 8046 "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", 8047 "MSRIndex": "0x1a6,0x1a7", 8048 "MSRValue": "0x10003C0100", 8049 "Offcore": "1", 8050 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8051 "SampleAfterValue": "100003", 8052 "UMask": "0x1" 8053 }, 8054 { 8055 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 8056 "Counter": "0,1,2,3", 8057 "CounterHTOff": "0,1,2,3", 8058 "EventCode": "0xB7, 0xBB", 8059 "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", 8060 "MSRIndex": "0x1a6,0x1a7", 8061 "MSRValue": "0x08003C0100", 8062 "Offcore": "1", 8063 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8064 "SampleAfterValue": "100003", 8065 "UMask": "0x1" 8066 }, 8067 { 8068 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 8069 "Counter": "0,1,2,3", 8070 "CounterHTOff": "0,1,2,3", 8071 "EventCode": "0xB7, 0xBB", 8072 "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", 8073 "MSRIndex": "0x1a6,0x1a7", 8074 "MSRValue": "0x04003C0100", 8075 "Offcore": "1", 8076 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8077 "SampleAfterValue": "100003", 8078 "UMask": "0x1" 8079 }, 8080 { 8081 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", 8082 "Counter": "0,1,2,3", 8083 "CounterHTOff": "0,1,2,3", 8084 "EventCode": "0xB7, 0xBB", 8085 "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", 8086 "MSRIndex": "0x1a6,0x1a7", 8087 "MSRValue": "0x01003C0100", 8088 "Offcore": "1", 8089 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8090 "SampleAfterValue": "100003", 8091 "UMask": "0x1" 8092 }, 8093 { 8094 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8095 "Counter": "0,1,2,3", 8096 "CounterHTOff": "0,1,2,3", 8097 "EventCode": "0xB7, 0xBB", 8098 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", 8099 "MSRIndex": "0x1a6,0x1a7", 8100 "MSRValue": "0x08007C0100", 8101 "Offcore": "1", 8102 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8103 "SampleAfterValue": "100003", 8104 "UMask": "0x1" 8105 }, 8106 { 8107 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", 8108 "Counter": "0,1,2,3", 8109 "CounterHTOff": "0,1,2,3", 8110 "EventCode": "0xB7, 0xBB", 8111 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", 8112 "MSRIndex": "0x1a6,0x1a7", 8113 "MSRValue": "0x02003C0100", 8114 "Offcore": "1", 8115 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8116 "SampleAfterValue": "100003", 8117 "UMask": "0x1" 8118 }, 8119 { 8120 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", 8121 "Counter": "0,1,2,3", 8122 "CounterHTOff": "0,1,2,3", 8123 "EventCode": "0xB7, 0xBB", 8124 "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", 8125 "MSRIndex": "0x1a6,0x1a7", 8126 "MSRValue": "0x00803C0100", 8127 "Offcore": "1", 8128 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8129 "SampleAfterValue": "100003", 8130 "UMask": "0x1" 8131 }, 8132 { 8133 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", 8134 "Counter": "0,1,2,3", 8135 "CounterHTOff": "0,1,2,3", 8136 "EventCode": "0xB7, 0xBB", 8137 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", 8138 "MSRIndex": "0x1a6,0x1a7", 8139 "MSRValue": "0x3F80080100", 8140 "Offcore": "1", 8141 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8142 "SampleAfterValue": "100003", 8143 "UMask": "0x1" 8144 }, 8145 { 8146 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", 8147 "Counter": "0,1,2,3", 8148 "CounterHTOff": "0,1,2,3", 8149 "EventCode": "0xB7, 0xBB", 8150 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", 8151 "MSRIndex": "0x1a6,0x1a7", 8152 "MSRValue": "0x1000080100", 8153 "Offcore": "1", 8154 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8155 "SampleAfterValue": "100003", 8156 "UMask": "0x1" 8157 }, 8158 { 8159 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 8160 "Counter": "0,1,2,3", 8161 "CounterHTOff": "0,1,2,3", 8162 "EventCode": "0xB7, 0xBB", 8163 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", 8164 "MSRIndex": "0x1a6,0x1a7", 8165 "MSRValue": "0x0800080100", 8166 "Offcore": "1", 8167 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8168 "SampleAfterValue": "100003", 8169 "UMask": "0x1" 8170 }, 8171 { 8172 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 8173 "Counter": "0,1,2,3", 8174 "CounterHTOff": "0,1,2,3", 8175 "EventCode": "0xB7, 0xBB", 8176 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", 8177 "MSRIndex": "0x1a6,0x1a7", 8178 "MSRValue": "0x0400080100", 8179 "Offcore": "1", 8180 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8181 "SampleAfterValue": "100003", 8182 "UMask": "0x1" 8183 }, 8184 { 8185 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 8186 "Counter": "0,1,2,3", 8187 "CounterHTOff": "0,1,2,3", 8188 "EventCode": "0xB7, 0xBB", 8189 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", 8190 "MSRIndex": "0x1a6,0x1a7", 8191 "MSRValue": "0x0100080100", 8192 "Offcore": "1", 8193 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8194 "SampleAfterValue": "100003", 8195 "UMask": "0x1" 8196 }, 8197 { 8198 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8199 "Counter": "0,1,2,3", 8200 "CounterHTOff": "0,1,2,3", 8201 "EventCode": "0xB7, 0xBB", 8202 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", 8203 "MSRIndex": "0x1a6,0x1a7", 8204 "MSRValue": "0x0200080100", 8205 "Offcore": "1", 8206 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8207 "SampleAfterValue": "100003", 8208 "UMask": "0x1" 8209 }, 8210 { 8211 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8212 "Counter": "0,1,2,3", 8213 "CounterHTOff": "0,1,2,3", 8214 "EventCode": "0xB7, 0xBB", 8215 "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", 8216 "MSRIndex": "0x1a6,0x1a7", 8217 "MSRValue": "0x0080080100", 8218 "Offcore": "1", 8219 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8220 "SampleAfterValue": "100003", 8221 "UMask": "0x1" 8222 }, 8223 { 8224 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", 8225 "Counter": "0,1,2,3", 8226 "CounterHTOff": "0,1,2,3", 8227 "EventCode": "0xB7, 0xBB", 8228 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", 8229 "MSRIndex": "0x1a6,0x1a7", 8230 "MSRValue": "0x3F80200100", 8231 "Offcore": "1", 8232 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8233 "SampleAfterValue": "100003", 8234 "UMask": "0x1" 8235 }, 8236 { 8237 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", 8238 "Counter": "0,1,2,3", 8239 "CounterHTOff": "0,1,2,3", 8240 "EventCode": "0xB7, 0xBB", 8241 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", 8242 "MSRIndex": "0x1a6,0x1a7", 8243 "MSRValue": "0x1000200100", 8244 "Offcore": "1", 8245 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8246 "SampleAfterValue": "100003", 8247 "UMask": "0x1" 8248 }, 8249 { 8250 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 8251 "Counter": "0,1,2,3", 8252 "CounterHTOff": "0,1,2,3", 8253 "EventCode": "0xB7, 0xBB", 8254 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", 8255 "MSRIndex": "0x1a6,0x1a7", 8256 "MSRValue": "0x0800200100", 8257 "Offcore": "1", 8258 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8259 "SampleAfterValue": "100003", 8260 "UMask": "0x1" 8261 }, 8262 { 8263 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 8264 "Counter": "0,1,2,3", 8265 "CounterHTOff": "0,1,2,3", 8266 "EventCode": "0xB7, 0xBB", 8267 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", 8268 "MSRIndex": "0x1a6,0x1a7", 8269 "MSRValue": "0x0400200100", 8270 "Offcore": "1", 8271 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8272 "SampleAfterValue": "100003", 8273 "UMask": "0x1" 8274 }, 8275 { 8276 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 8277 "Counter": "0,1,2,3", 8278 "CounterHTOff": "0,1,2,3", 8279 "EventCode": "0xB7, 0xBB", 8280 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", 8281 "MSRIndex": "0x1a6,0x1a7", 8282 "MSRValue": "0x0100200100", 8283 "Offcore": "1", 8284 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8285 "SampleAfterValue": "100003", 8286 "UMask": "0x1" 8287 }, 8288 { 8289 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8290 "Counter": "0,1,2,3", 8291 "CounterHTOff": "0,1,2,3", 8292 "EventCode": "0xB7, 0xBB", 8293 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", 8294 "MSRIndex": "0x1a6,0x1a7", 8295 "MSRValue": "0x0200200100", 8296 "Offcore": "1", 8297 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8298 "SampleAfterValue": "100003", 8299 "UMask": "0x1" 8300 }, 8301 { 8302 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8303 "Counter": "0,1,2,3", 8304 "CounterHTOff": "0,1,2,3", 8305 "EventCode": "0xB7, 0xBB", 8306 "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", 8307 "MSRIndex": "0x1a6,0x1a7", 8308 "MSRValue": "0x0080200100", 8309 "Offcore": "1", 8310 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8311 "SampleAfterValue": "100003", 8312 "UMask": "0x1" 8313 }, 8314 { 8315 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", 8316 "Counter": "0,1,2,3", 8317 "CounterHTOff": "0,1,2,3", 8318 "EventCode": "0xB7, 0xBB", 8319 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", 8320 "MSRIndex": "0x1a6,0x1a7", 8321 "MSRValue": "0x3F80040100", 8322 "Offcore": "1", 8323 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8324 "SampleAfterValue": "100003", 8325 "UMask": "0x1" 8326 }, 8327 { 8328 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", 8329 "Counter": "0,1,2,3", 8330 "CounterHTOff": "0,1,2,3", 8331 "EventCode": "0xB7, 0xBB", 8332 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", 8333 "MSRIndex": "0x1a6,0x1a7", 8334 "MSRValue": "0x1000040100", 8335 "Offcore": "1", 8336 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8337 "SampleAfterValue": "100003", 8338 "UMask": "0x1" 8339 }, 8340 { 8341 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 8342 "Counter": "0,1,2,3", 8343 "CounterHTOff": "0,1,2,3", 8344 "EventCode": "0xB7, 0xBB", 8345 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", 8346 "MSRIndex": "0x1a6,0x1a7", 8347 "MSRValue": "0x0800040100", 8348 "Offcore": "1", 8349 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8350 "SampleAfterValue": "100003", 8351 "UMask": "0x1" 8352 }, 8353 { 8354 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 8355 "Counter": "0,1,2,3", 8356 "CounterHTOff": "0,1,2,3", 8357 "EventCode": "0xB7, 0xBB", 8358 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", 8359 "MSRIndex": "0x1a6,0x1a7", 8360 "MSRValue": "0x0400040100", 8361 "Offcore": "1", 8362 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8363 "SampleAfterValue": "100003", 8364 "UMask": "0x1" 8365 }, 8366 { 8367 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 8368 "Counter": "0,1,2,3", 8369 "CounterHTOff": "0,1,2,3", 8370 "EventCode": "0xB7, 0xBB", 8371 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", 8372 "MSRIndex": "0x1a6,0x1a7", 8373 "MSRValue": "0x0100040100", 8374 "Offcore": "1", 8375 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8376 "SampleAfterValue": "100003", 8377 "UMask": "0x1" 8378 }, 8379 { 8380 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8381 "Counter": "0,1,2,3", 8382 "CounterHTOff": "0,1,2,3", 8383 "EventCode": "0xB7, 0xBB", 8384 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", 8385 "MSRIndex": "0x1a6,0x1a7", 8386 "MSRValue": "0x0200040100", 8387 "Offcore": "1", 8388 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8389 "SampleAfterValue": "100003", 8390 "UMask": "0x1" 8391 }, 8392 { 8393 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8394 "Counter": "0,1,2,3", 8395 "CounterHTOff": "0,1,2,3", 8396 "EventCode": "0xB7, 0xBB", 8397 "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", 8398 "MSRIndex": "0x1a6,0x1a7", 8399 "MSRValue": "0x0080040100", 8400 "Offcore": "1", 8401 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8402 "SampleAfterValue": "100003", 8403 "UMask": "0x1" 8404 }, 8405 { 8406 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", 8407 "Counter": "0,1,2,3", 8408 "CounterHTOff": "0,1,2,3", 8409 "EventCode": "0xB7, 0xBB", 8410 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", 8411 "MSRIndex": "0x1a6,0x1a7", 8412 "MSRValue": "0x3F80100100", 8413 "Offcore": "1", 8414 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8415 "SampleAfterValue": "100003", 8416 "UMask": "0x1" 8417 }, 8418 { 8419 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", 8420 "Counter": "0,1,2,3", 8421 "CounterHTOff": "0,1,2,3", 8422 "EventCode": "0xB7, 0xBB", 8423 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", 8424 "MSRIndex": "0x1a6,0x1a7", 8425 "MSRValue": "0x1000100100", 8426 "Offcore": "1", 8427 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8428 "SampleAfterValue": "100003", 8429 "UMask": "0x1" 8430 }, 8431 { 8432 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 8433 "Counter": "0,1,2,3", 8434 "CounterHTOff": "0,1,2,3", 8435 "EventCode": "0xB7, 0xBB", 8436 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", 8437 "MSRIndex": "0x1a6,0x1a7", 8438 "MSRValue": "0x0800100100", 8439 "Offcore": "1", 8440 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8441 "SampleAfterValue": "100003", 8442 "UMask": "0x1" 8443 }, 8444 { 8445 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 8446 "Counter": "0,1,2,3", 8447 "CounterHTOff": "0,1,2,3", 8448 "EventCode": "0xB7, 0xBB", 8449 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", 8450 "MSRIndex": "0x1a6,0x1a7", 8451 "MSRValue": "0x0400100100", 8452 "Offcore": "1", 8453 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8454 "SampleAfterValue": "100003", 8455 "UMask": "0x1" 8456 }, 8457 { 8458 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 8459 "Counter": "0,1,2,3", 8460 "CounterHTOff": "0,1,2,3", 8461 "EventCode": "0xB7, 0xBB", 8462 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", 8463 "MSRIndex": "0x1a6,0x1a7", 8464 "MSRValue": "0x0100100100", 8465 "Offcore": "1", 8466 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8467 "SampleAfterValue": "100003", 8468 "UMask": "0x1" 8469 }, 8470 { 8471 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8472 "Counter": "0,1,2,3", 8473 "CounterHTOff": "0,1,2,3", 8474 "EventCode": "0xB7, 0xBB", 8475 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", 8476 "MSRIndex": "0x1a6,0x1a7", 8477 "MSRValue": "0x0200100100", 8478 "Offcore": "1", 8479 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8480 "SampleAfterValue": "100003", 8481 "UMask": "0x1" 8482 }, 8483 { 8484 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8485 "Counter": "0,1,2,3", 8486 "CounterHTOff": "0,1,2,3", 8487 "EventCode": "0xB7, 0xBB", 8488 "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", 8489 "MSRIndex": "0x1a6,0x1a7", 8490 "MSRValue": "0x0080100100", 8491 "Offcore": "1", 8492 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8493 "SampleAfterValue": "100003", 8494 "UMask": "0x1" 8495 }, 8496 { 8497 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8498 "Counter": "0,1,2,3", 8499 "CounterHTOff": "0,1,2,3", 8500 "EventCode": "0xB7, 0xBB", 8501 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", 8502 "MSRIndex": "0x1a6,0x1a7", 8503 "MSRValue": "0x3F80400100", 8504 "Offcore": "1", 8505 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8506 "SampleAfterValue": "100003", 8507 "UMask": "0x1" 8508 }, 8509 { 8510 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8511 "Counter": "0,1,2,3", 8512 "CounterHTOff": "0,1,2,3", 8513 "EventCode": "0xB7, 0xBB", 8514 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", 8515 "MSRIndex": "0x1a6,0x1a7", 8516 "MSRValue": "0x0080400100", 8517 "Offcore": "1", 8518 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8519 "SampleAfterValue": "100003", 8520 "UMask": "0x1" 8521 }, 8522 { 8523 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8524 "Counter": "0,1,2,3", 8525 "CounterHTOff": "0,1,2,3", 8526 "EventCode": "0xB7, 0xBB", 8527 "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", 8528 "MSRIndex": "0x1a6,0x1a7", 8529 "MSRValue": "0x0100400100", 8530 "Offcore": "1", 8531 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8532 "SampleAfterValue": "100003", 8533 "UMask": "0x1" 8534 }, 8535 { 8536 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", 8537 "Counter": "0,1,2,3", 8538 "CounterHTOff": "0,1,2,3", 8539 "EventCode": "0xB7, 0xBB", 8540 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", 8541 "MSRIndex": "0x1a6,0x1a7", 8542 "MSRValue": "0x3F80020100", 8543 "Offcore": "1", 8544 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8545 "SampleAfterValue": "100003", 8546 "UMask": "0x1" 8547 }, 8548 { 8549 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 8550 "Counter": "0,1,2,3", 8551 "CounterHTOff": "0,1,2,3", 8552 "EventCode": "0xB7, 0xBB", 8553 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", 8554 "MSRIndex": "0x1a6,0x1a7", 8555 "MSRValue": "0x1000020100", 8556 "Offcore": "1", 8557 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8558 "SampleAfterValue": "100003", 8559 "UMask": "0x1" 8560 }, 8561 { 8562 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 8563 "Counter": "0,1,2,3", 8564 "CounterHTOff": "0,1,2,3", 8565 "EventCode": "0xB7, 0xBB", 8566 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", 8567 "MSRIndex": "0x1a6,0x1a7", 8568 "MSRValue": "0x0800020100", 8569 "Offcore": "1", 8570 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8571 "SampleAfterValue": "100003", 8572 "UMask": "0x1" 8573 }, 8574 { 8575 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 8576 "Counter": "0,1,2,3", 8577 "CounterHTOff": "0,1,2,3", 8578 "EventCode": "0xB7, 0xBB", 8579 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", 8580 "MSRIndex": "0x1a6,0x1a7", 8581 "MSRValue": "0x0400020100", 8582 "Offcore": "1", 8583 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8584 "SampleAfterValue": "100003", 8585 "UMask": "0x1" 8586 }, 8587 { 8588 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 8589 "Counter": "0,1,2,3", 8590 "CounterHTOff": "0,1,2,3", 8591 "EventCode": "0xB7, 0xBB", 8592 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", 8593 "MSRIndex": "0x1a6,0x1a7", 8594 "MSRValue": "0x0100020100", 8595 "Offcore": "1", 8596 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8597 "SampleAfterValue": "100003", 8598 "UMask": "0x1" 8599 }, 8600 { 8601 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8602 "Counter": "0,1,2,3", 8603 "CounterHTOff": "0,1,2,3", 8604 "EventCode": "0xB7, 0xBB", 8605 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", 8606 "MSRIndex": "0x1a6,0x1a7", 8607 "MSRValue": "0x0200020100", 8608 "Offcore": "1", 8609 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8610 "SampleAfterValue": "100003", 8611 "UMask": "0x1" 8612 }, 8613 { 8614 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", 8615 "Counter": "0,1,2,3", 8616 "CounterHTOff": "0,1,2,3", 8617 "EventCode": "0xB7, 0xBB", 8618 "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", 8619 "MSRIndex": "0x1a6,0x1a7", 8620 "MSRValue": "0x0080020100", 8621 "Offcore": "1", 8622 "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", 8623 "SampleAfterValue": "100003", 8624 "UMask": "0x1" 8625 }, 8626 { 8627 "BriefDescription": "Number of PREFETCHNTA instructions executed.", 8628 "Counter": "0,1,2,3", 8629 "CounterHTOff": "0,1,2,3,4,5,6,7", 8630 "EventCode": "0x32", 8631 "EventName": "SW_PREFETCH_ACCESS.NTA", 8632 "SampleAfterValue": "2000003", 8633 "UMask": "0x1" 8634 }, 8635 { 8636 "BriefDescription": "Number of PREFETCHW instructions executed.", 8637 "Counter": "0,1,2,3", 8638 "CounterHTOff": "0,1,2,3,4,5,6,7", 8639 "EventCode": "0x32", 8640 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 8641 "SampleAfterValue": "2000003", 8642 "UMask": "0x8" 8643 }, 8644 { 8645 "BriefDescription": "Number of PREFETCHT0 instructions executed.", 8646 "Counter": "0,1,2,3", 8647 "CounterHTOff": "0,1,2,3,4,5,6,7", 8648 "EventCode": "0x32", 8649 "EventName": "SW_PREFETCH_ACCESS.T0", 8650 "SampleAfterValue": "2000003", 8651 "UMask": "0x2" 8652 }, 8653 { 8654 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 8655 "Counter": "0,1,2,3", 8656 "CounterHTOff": "0,1,2,3,4,5,6,7", 8657 "EventCode": "0x32", 8658 "EventName": "SW_PREFETCH_ACCESS.T1_T2", 8659 "SampleAfterValue": "2000003", 8660 "UMask": "0x4" 8661 } 8662]