1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "Counter": "0,1,2,3", 5 "EventCode": "0xc8", 6 "EventName": "HLE_RETIRED.ABORTED", 7 "PEBS": "1", 8 "PublicDescription": "Number of times HLE abort was triggered.", 9 "SampleAfterValue": "2000003", 10 "UMask": "0x4" 11 }, 12 { 13 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 14 "Counter": "0,1,2,3", 15 "EventCode": "0xc8", 16 "EventName": "HLE_RETIRED.ABORTED_MISC1", 17 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 18 "SampleAfterValue": "2000003", 19 "UMask": "0x8" 20 }, 21 { 22 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 23 "Counter": "0,1,2,3", 24 "EventCode": "0xc8", 25 "EventName": "HLE_RETIRED.ABORTED_MISC2", 26 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 27 "SampleAfterValue": "2000003", 28 "UMask": "0x10" 29 }, 30 { 31 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 32 "Counter": "0,1,2,3", 33 "EventCode": "0xc8", 34 "EventName": "HLE_RETIRED.ABORTED_MISC3", 35 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 36 "SampleAfterValue": "2000003", 37 "UMask": "0x20" 38 }, 39 { 40 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 41 "Counter": "0,1,2,3", 42 "EventCode": "0xc8", 43 "EventName": "HLE_RETIRED.ABORTED_MISC4", 44 "PublicDescription": "Number of times HLE caused a fault.", 45 "SampleAfterValue": "2000003", 46 "UMask": "0x40" 47 }, 48 { 49 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 50 "Counter": "0,1,2,3", 51 "EventCode": "0xc8", 52 "EventName": "HLE_RETIRED.ABORTED_MISC5", 53 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 54 "SampleAfterValue": "2000003", 55 "UMask": "0x80" 56 }, 57 { 58 "BriefDescription": "Number of times HLE commit succeeded", 59 "Counter": "0,1,2,3", 60 "EventCode": "0xc8", 61 "EventName": "HLE_RETIRED.COMMIT", 62 "PublicDescription": "Number of times HLE commit succeeded.", 63 "SampleAfterValue": "2000003", 64 "UMask": "0x2" 65 }, 66 { 67 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 68 "Counter": "0,1,2,3", 69 "EventCode": "0xc8", 70 "EventName": "HLE_RETIRED.START", 71 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 72 "SampleAfterValue": "2000003", 73 "UMask": "0x1" 74 }, 75 { 76 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 77 "Counter": "0,1,2,3", 78 "EventCode": "0xC3", 79 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 80 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 81 "SampleAfterValue": "100003", 82 "UMask": "0x2" 83 }, 84 { 85 "BriefDescription": "Randomly selected loads with latency value being above 128", 86 "Counter": "3", 87 "Data_LA": "1", 88 "Errata": "BDM100, BDM35", 89 "EventCode": "0xcd", 90 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 91 "MSRIndex": "0x3F6", 92 "MSRValue": "0x80", 93 "PEBS": "2", 94 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 95 "SampleAfterValue": "1009", 96 "UMask": "0x1" 97 }, 98 { 99 "BriefDescription": "Randomly selected loads with latency value being above 16", 100 "Counter": "3", 101 "Data_LA": "1", 102 "Errata": "BDM100, BDM35", 103 "EventCode": "0xcd", 104 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 105 "MSRIndex": "0x3F6", 106 "MSRValue": "0x10", 107 "PEBS": "2", 108 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 109 "SampleAfterValue": "20011", 110 "UMask": "0x1" 111 }, 112 { 113 "BriefDescription": "Randomly selected loads with latency value being above 256", 114 "Counter": "3", 115 "Data_LA": "1", 116 "Errata": "BDM100, BDM35", 117 "EventCode": "0xcd", 118 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 119 "MSRIndex": "0x3F6", 120 "MSRValue": "0x100", 121 "PEBS": "2", 122 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 123 "SampleAfterValue": "503", 124 "UMask": "0x1" 125 }, 126 { 127 "BriefDescription": "Randomly selected loads with latency value being above 32", 128 "Counter": "3", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x20", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 137 "SampleAfterValue": "100007", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Randomly selected loads with latency value being above 4", 142 "Counter": "3", 143 "Data_LA": "1", 144 "Errata": "BDM100, BDM35", 145 "EventCode": "0xcd", 146 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 147 "MSRIndex": "0x3F6", 148 "MSRValue": "0x4", 149 "PEBS": "2", 150 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 151 "SampleAfterValue": "100003", 152 "UMask": "0x1" 153 }, 154 { 155 "BriefDescription": "Randomly selected loads with latency value being above 512", 156 "Counter": "3", 157 "Data_LA": "1", 158 "Errata": "BDM100, BDM35", 159 "EventCode": "0xcd", 160 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 161 "MSRIndex": "0x3F6", 162 "MSRValue": "0x200", 163 "PEBS": "2", 164 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 165 "SampleAfterValue": "101", 166 "UMask": "0x1" 167 }, 168 { 169 "BriefDescription": "Randomly selected loads with latency value being above 64", 170 "Counter": "3", 171 "Data_LA": "1", 172 "Errata": "BDM100, BDM35", 173 "EventCode": "0xcd", 174 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 175 "MSRIndex": "0x3F6", 176 "MSRValue": "0x40", 177 "PEBS": "2", 178 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 179 "SampleAfterValue": "2003", 180 "UMask": "0x1" 181 }, 182 { 183 "BriefDescription": "Randomly selected loads with latency value being above 8", 184 "Counter": "3", 185 "Data_LA": "1", 186 "Errata": "BDM100, BDM35", 187 "EventCode": "0xcd", 188 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 189 "MSRIndex": "0x3F6", 190 "MSRValue": "0x8", 191 "PEBS": "2", 192 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 193 "SampleAfterValue": "50021", 194 "UMask": "0x1" 195 }, 196 { 197 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 198 "Counter": "0,1,2,3", 199 "EventCode": "0x05", 200 "EventName": "MISALIGN_MEM_REF.LOADS", 201 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 202 "SampleAfterValue": "2000003", 203 "UMask": "0x1" 204 }, 205 { 206 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 207 "Counter": "0,1,2,3", 208 "EventCode": "0x05", 209 "EventName": "MISALIGN_MEM_REF.STORES", 210 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 211 "SampleAfterValue": "2000003", 212 "UMask": "0x2" 213 }, 214 { 215 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 216 "Counter": "0,1,2,3", 217 "EventCode": "0xB7, 0xBB", 218 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 219 "MSRIndex": "0x1a6,0x1a7", 220 "MSRValue": "0x3FBFC00244", 221 "SampleAfterValue": "100003", 222 "UMask": "0x1" 223 }, 224 { 225 "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 226 "Counter": "0,1,2,3", 227 "EventCode": "0xB7, 0xBB", 228 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", 229 "MSRIndex": "0x1a6,0x1a7", 230 "MSRValue": "0x604000244", 231 "SampleAfterValue": "100003", 232 "UMask": "0x1" 233 }, 234 { 235 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 236 "Counter": "0,1,2,3", 237 "EventCode": "0xB7, 0xBB", 238 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", 239 "MSRIndex": "0x1a6,0x1a7", 240 "MSRValue": "0x3FBFC00091", 241 "SampleAfterValue": "100003", 242 "UMask": "0x1" 243 }, 244 { 245 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 246 "Counter": "0,1,2,3", 247 "EventCode": "0xB7, 0xBB", 248 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", 249 "MSRIndex": "0x1a6,0x1a7", 250 "MSRValue": "0x604000091", 251 "SampleAfterValue": "100003", 252 "UMask": "0x1" 253 }, 254 { 255 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 256 "Counter": "0,1,2,3", 257 "EventCode": "0xB7, 0xBB", 258 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", 259 "MSRIndex": "0x1a6,0x1a7", 260 "MSRValue": "0x63BC00091", 261 "SampleAfterValue": "100003", 262 "UMask": "0x1" 263 }, 264 { 265 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 266 "Counter": "0,1,2,3", 267 "EventCode": "0xB7, 0xBB", 268 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", 269 "MSRIndex": "0x1a6,0x1a7", 270 "MSRValue": "0x103FC00091", 271 "SampleAfterValue": "100003", 272 "UMask": "0x1" 273 }, 274 { 275 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 276 "Counter": "0,1,2,3", 277 "EventCode": "0xB7, 0xBB", 278 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 279 "MSRIndex": "0x1a6,0x1a7", 280 "MSRValue": "0x87FC00091", 281 "SampleAfterValue": "100003", 282 "UMask": "0x1" 283 }, 284 { 285 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 286 "Counter": "0,1,2,3", 287 "EventCode": "0xB7, 0xBB", 288 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", 289 "MSRIndex": "0x1a6,0x1a7", 290 "MSRValue": "0x3FBFC007F7", 291 "SampleAfterValue": "100003", 292 "UMask": "0x1" 293 }, 294 { 295 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", 296 "Counter": "0,1,2,3", 297 "EventCode": "0xB7, 0xBB", 298 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", 299 "MSRIndex": "0x1a6,0x1a7", 300 "MSRValue": "0x6040007F7", 301 "SampleAfterValue": "100003", 302 "UMask": "0x1" 303 }, 304 { 305 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 306 "Counter": "0,1,2,3", 307 "EventCode": "0xB7, 0xBB", 308 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", 309 "MSRIndex": "0x1a6,0x1a7", 310 "MSRValue": "0x63BC007F7", 311 "SampleAfterValue": "100003", 312 "UMask": "0x1" 313 }, 314 { 315 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 316 "Counter": "0,1,2,3", 317 "EventCode": "0xB7, 0xBB", 318 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", 319 "MSRIndex": "0x1a6,0x1a7", 320 "MSRValue": "0x103FC007F7", 321 "SampleAfterValue": "100003", 322 "UMask": "0x1" 323 }, 324 { 325 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 326 "Counter": "0,1,2,3", 327 "EventCode": "0xB7, 0xBB", 328 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", 329 "MSRIndex": "0x1a6,0x1a7", 330 "MSRValue": "0x87FC007F7", 331 "SampleAfterValue": "100003", 332 "UMask": "0x1" 333 }, 334 { 335 "BriefDescription": "Counts all requests miss in the L3", 336 "Counter": "0,1,2,3", 337 "EventCode": "0xB7, 0xBB", 338 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", 339 "MSRIndex": "0x1a6,0x1a7", 340 "MSRValue": "0x3FBFC08FFF", 341 "SampleAfterValue": "100003", 342 "UMask": "0x1" 343 }, 344 { 345 "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", 346 "Counter": "0,1,2,3", 347 "EventCode": "0xB7, 0xBB", 348 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", 349 "MSRIndex": "0x1a6,0x1a7", 350 "MSRValue": "0x3FBFC00122", 351 "SampleAfterValue": "100003", 352 "UMask": "0x1" 353 }, 354 { 355 "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 356 "Counter": "0,1,2,3", 357 "EventCode": "0xB7, 0xBB", 358 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", 359 "MSRIndex": "0x1a6,0x1a7", 360 "MSRValue": "0x604000122", 361 "SampleAfterValue": "100003", 362 "UMask": "0x1" 363 }, 364 { 365 "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", 366 "Counter": "0,1,2,3", 367 "EventCode": "0xB7, 0xBB", 368 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", 369 "MSRIndex": "0x1a6,0x1a7", 370 "MSRValue": "0x3FBFC00002", 371 "SampleAfterValue": "100003", 372 "UMask": "0x1" 373 }, 374 { 375 "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 376 "Counter": "0,1,2,3", 377 "EventCode": "0xB7, 0xBB", 378 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", 379 "MSRIndex": "0x1a6,0x1a7", 380 "MSRValue": "0x103FC00002", 381 "SampleAfterValue": "100003", 382 "UMask": "0x1" 383 }, 384 { 385 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 386 "Counter": "0,1,2,3", 387 "EventCode": "0xB7, 0xBB", 388 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 389 "MSRIndex": "0x1a6,0x1a7", 390 "MSRValue": "0x3FBFC00200", 391 "SampleAfterValue": "100003", 392 "UMask": "0x1" 393 }, 394 { 395 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 396 "Counter": "0,1,2,3", 397 "EventCode": "0xB7, 0xBB", 398 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", 399 "MSRIndex": "0x1a6,0x1a7", 400 "MSRValue": "0x3FBFC00100", 401 "SampleAfterValue": "100003", 402 "UMask": "0x1" 403 }, 404 { 405 "BriefDescription": "Number of times RTM abort was triggered", 406 "Counter": "0,1,2,3", 407 "EventCode": "0xc9", 408 "EventName": "RTM_RETIRED.ABORTED", 409 "PEBS": "1", 410 "PublicDescription": "Number of times RTM abort was triggered .", 411 "SampleAfterValue": "2000003", 412 "UMask": "0x4" 413 }, 414 { 415 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 416 "Counter": "0,1,2,3", 417 "EventCode": "0xc9", 418 "EventName": "RTM_RETIRED.ABORTED_MISC1", 419 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 420 "SampleAfterValue": "2000003", 421 "UMask": "0x8" 422 }, 423 { 424 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 425 "Counter": "0,1,2,3", 426 "EventCode": "0xc9", 427 "EventName": "RTM_RETIRED.ABORTED_MISC2", 428 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 429 "SampleAfterValue": "2000003", 430 "UMask": "0x10" 431 }, 432 { 433 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 434 "Counter": "0,1,2,3", 435 "EventCode": "0xc9", 436 "EventName": "RTM_RETIRED.ABORTED_MISC3", 437 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 438 "SampleAfterValue": "2000003", 439 "UMask": "0x20" 440 }, 441 { 442 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 443 "Counter": "0,1,2,3", 444 "EventCode": "0xc9", 445 "EventName": "RTM_RETIRED.ABORTED_MISC4", 446 "PublicDescription": "Number of times a RTM caused a fault.", 447 "SampleAfterValue": "2000003", 448 "UMask": "0x40" 449 }, 450 { 451 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 452 "Counter": "0,1,2,3", 453 "EventCode": "0xc9", 454 "EventName": "RTM_RETIRED.ABORTED_MISC5", 455 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 456 "SampleAfterValue": "2000003", 457 "UMask": "0x80" 458 }, 459 { 460 "BriefDescription": "Number of times RTM commit succeeded", 461 "Counter": "0,1,2,3", 462 "EventCode": "0xc9", 463 "EventName": "RTM_RETIRED.COMMIT", 464 "PublicDescription": "Number of times RTM commit succeeded.", 465 "SampleAfterValue": "2000003", 466 "UMask": "0x2" 467 }, 468 { 469 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 470 "Counter": "0,1,2,3", 471 "EventCode": "0xc9", 472 "EventName": "RTM_RETIRED.START", 473 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 474 "SampleAfterValue": "2000003", 475 "UMask": "0x1" 476 }, 477 { 478 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 479 "Counter": "0,1,2,3", 480 "EventCode": "0x5d", 481 "EventName": "TX_EXEC.MISC1", 482 "SampleAfterValue": "2000003", 483 "UMask": "0x1" 484 }, 485 { 486 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 487 "Counter": "0,1,2,3", 488 "EventCode": "0x5d", 489 "EventName": "TX_EXEC.MISC2", 490 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 491 "SampleAfterValue": "2000003", 492 "UMask": "0x2" 493 }, 494 { 495 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 496 "Counter": "0,1,2,3", 497 "EventCode": "0x5d", 498 "EventName": "TX_EXEC.MISC3", 499 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 500 "SampleAfterValue": "2000003", 501 "UMask": "0x4" 502 }, 503 { 504 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 505 "Counter": "0,1,2,3", 506 "EventCode": "0x5d", 507 "EventName": "TX_EXEC.MISC4", 508 "PublicDescription": "RTM region detected inside HLE.", 509 "SampleAfterValue": "2000003", 510 "UMask": "0x8" 511 }, 512 { 513 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 514 "Counter": "0,1,2,3", 515 "EventCode": "0x5d", 516 "EventName": "TX_EXEC.MISC5", 517 "SampleAfterValue": "2000003", 518 "UMask": "0x10" 519 }, 520 { 521 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 522 "Counter": "0,1,2,3", 523 "EventCode": "0x54", 524 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 525 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 526 "SampleAfterValue": "2000003", 527 "UMask": "0x2" 528 }, 529 { 530 "BriefDescription": "Number of times a TSX line had a cache conflict", 531 "Counter": "0,1,2,3", 532 "EventCode": "0x54", 533 "EventName": "TX_MEM.ABORT_CONFLICT", 534 "PublicDescription": "Number of times a TSX line had a cache conflict.", 535 "SampleAfterValue": "2000003", 536 "UMask": "0x1" 537 }, 538 { 539 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 540 "Counter": "0,1,2,3", 541 "EventCode": "0x54", 542 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 543 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 544 "SampleAfterValue": "2000003", 545 "UMask": "0x10" 546 }, 547 { 548 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 549 "Counter": "0,1,2,3", 550 "EventCode": "0x54", 551 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 552 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 553 "SampleAfterValue": "2000003", 554 "UMask": "0x8" 555 }, 556 { 557 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 558 "Counter": "0,1,2,3", 559 "EventCode": "0x54", 560 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 561 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 562 "SampleAfterValue": "2000003", 563 "UMask": "0x20" 564 }, 565 { 566 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 567 "Counter": "0,1,2,3", 568 "EventCode": "0x54", 569 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 570 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 571 "SampleAfterValue": "2000003", 572 "UMask": "0x4" 573 }, 574 { 575 "BriefDescription": "Number of times we could not allocate Lock Buffer", 576 "Counter": "0,1,2,3", 577 "EventCode": "0x54", 578 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 579 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 580 "SampleAfterValue": "2000003", 581 "UMask": "0x40" 582 } 583] 584