1[ 2 { 3 "BriefDescription": "Number of times HLE abort was triggered", 4 "EventCode": "0xc8", 5 "EventName": "HLE_RETIRED.ABORTED", 6 "PEBS": "1", 7 "PublicDescription": "Number of times HLE abort was triggered.", 8 "SampleAfterValue": "2000003", 9 "UMask": "0x4" 10 }, 11 { 12 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 13 "EventCode": "0xc8", 14 "EventName": "HLE_RETIRED.ABORTED_MISC1", 15 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 16 "SampleAfterValue": "2000003", 17 "UMask": "0x8" 18 }, 19 { 20 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", 21 "EventCode": "0xc8", 22 "EventName": "HLE_RETIRED.ABORTED_MISC2", 23 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", 24 "SampleAfterValue": "2000003", 25 "UMask": "0x10" 26 }, 27 { 28 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", 29 "EventCode": "0xc8", 30 "EventName": "HLE_RETIRED.ABORTED_MISC3", 31 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", 32 "SampleAfterValue": "2000003", 33 "UMask": "0x20" 34 }, 35 { 36 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", 37 "EventCode": "0xc8", 38 "EventName": "HLE_RETIRED.ABORTED_MISC4", 39 "PublicDescription": "Number of times HLE caused a fault.", 40 "SampleAfterValue": "2000003", 41 "UMask": "0x40" 42 }, 43 { 44 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", 45 "EventCode": "0xc8", 46 "EventName": "HLE_RETIRED.ABORTED_MISC5", 47 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", 48 "SampleAfterValue": "2000003", 49 "UMask": "0x80" 50 }, 51 { 52 "BriefDescription": "Number of times HLE commit succeeded", 53 "EventCode": "0xc8", 54 "EventName": "HLE_RETIRED.COMMIT", 55 "PublicDescription": "Number of times HLE commit succeeded.", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x2" 58 }, 59 { 60 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", 61 "EventCode": "0xc8", 62 "EventName": "HLE_RETIRED.START", 63 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", 64 "SampleAfterValue": "2000003", 65 "UMask": "0x1" 66 }, 67 { 68 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", 69 "EventCode": "0xC3", 70 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 71 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", 72 "SampleAfterValue": "100003", 73 "UMask": "0x2" 74 }, 75 { 76 "BriefDescription": "Randomly selected loads with latency value being above 128", 77 "Data_LA": "1", 78 "Errata": "BDM100, BDM35", 79 "EventCode": "0xcd", 80 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 81 "MSRIndex": "0x3F6", 82 "MSRValue": "0x80", 83 "PEBS": "2", 84 "PublicDescription": "Counts randomly selected loads with latency value being above 128.", 85 "SampleAfterValue": "1009", 86 "UMask": "0x1" 87 }, 88 { 89 "BriefDescription": "Randomly selected loads with latency value being above 16", 90 "Data_LA": "1", 91 "Errata": "BDM100, BDM35", 92 "EventCode": "0xcd", 93 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 94 "MSRIndex": "0x3F6", 95 "MSRValue": "0x10", 96 "PEBS": "2", 97 "PublicDescription": "Counts randomly selected loads with latency value being above 16.", 98 "SampleAfterValue": "20011", 99 "UMask": "0x1" 100 }, 101 { 102 "BriefDescription": "Randomly selected loads with latency value being above 256", 103 "Data_LA": "1", 104 "Errata": "BDM100, BDM35", 105 "EventCode": "0xcd", 106 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 107 "MSRIndex": "0x3F6", 108 "MSRValue": "0x100", 109 "PEBS": "2", 110 "PublicDescription": "Counts randomly selected loads with latency value being above 256.", 111 "SampleAfterValue": "503", 112 "UMask": "0x1" 113 }, 114 { 115 "BriefDescription": "Randomly selected loads with latency value being above 32", 116 "Data_LA": "1", 117 "Errata": "BDM100, BDM35", 118 "EventCode": "0xcd", 119 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 120 "MSRIndex": "0x3F6", 121 "MSRValue": "0x20", 122 "PEBS": "2", 123 "PublicDescription": "Counts randomly selected loads with latency value being above 32.", 124 "SampleAfterValue": "100007", 125 "UMask": "0x1" 126 }, 127 { 128 "BriefDescription": "Randomly selected loads with latency value being above 4", 129 "Data_LA": "1", 130 "Errata": "BDM100, BDM35", 131 "EventCode": "0xcd", 132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 133 "MSRIndex": "0x3F6", 134 "MSRValue": "0x4", 135 "PEBS": "2", 136 "PublicDescription": "Counts randomly selected loads with latency value being above four.", 137 "SampleAfterValue": "100003", 138 "UMask": "0x1" 139 }, 140 { 141 "BriefDescription": "Randomly selected loads with latency value being above 512", 142 "Data_LA": "1", 143 "Errata": "BDM100, BDM35", 144 "EventCode": "0xcd", 145 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 146 "MSRIndex": "0x3F6", 147 "MSRValue": "0x200", 148 "PEBS": "2", 149 "PublicDescription": "Counts randomly selected loads with latency value being above 512.", 150 "SampleAfterValue": "101", 151 "UMask": "0x1" 152 }, 153 { 154 "BriefDescription": "Randomly selected loads with latency value being above 64", 155 "Data_LA": "1", 156 "Errata": "BDM100, BDM35", 157 "EventCode": "0xcd", 158 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 159 "MSRIndex": "0x3F6", 160 "MSRValue": "0x40", 161 "PEBS": "2", 162 "PublicDescription": "Counts randomly selected loads with latency value being above 64.", 163 "SampleAfterValue": "2003", 164 "UMask": "0x1" 165 }, 166 { 167 "BriefDescription": "Randomly selected loads with latency value being above 8", 168 "Data_LA": "1", 169 "Errata": "BDM100, BDM35", 170 "EventCode": "0xcd", 171 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 172 "MSRIndex": "0x3F6", 173 "MSRValue": "0x8", 174 "PEBS": "2", 175 "PublicDescription": "Counts randomly selected loads with latency value being above eight.", 176 "SampleAfterValue": "50021", 177 "UMask": "0x1" 178 }, 179 { 180 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", 181 "EventCode": "0x05", 182 "EventName": "MISALIGN_MEM_REF.LOADS", 183 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", 184 "SampleAfterValue": "2000003", 185 "UMask": "0x1" 186 }, 187 { 188 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", 189 "EventCode": "0x05", 190 "EventName": "MISALIGN_MEM_REF.STORES", 191 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", 192 "SampleAfterValue": "2000003", 193 "UMask": "0x2" 194 }, 195 { 196 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", 197 "EventCode": "0xB7, 0xBB", 198 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", 199 "MSRIndex": "0x1a6,0x1a7", 200 "MSRValue": "0x3FBFC00244", 201 "SampleAfterValue": "100003", 202 "UMask": "0x1" 203 }, 204 { 205 "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", 206 "EventCode": "0xB7, 0xBB", 207 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", 208 "MSRIndex": "0x1a6,0x1a7", 209 "MSRValue": "0x604000244", 210 "SampleAfterValue": "100003", 211 "UMask": "0x1" 212 }, 213 { 214 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", 215 "EventCode": "0xB7, 0xBB", 216 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", 217 "MSRIndex": "0x1a6,0x1a7", 218 "MSRValue": "0x3FBFC00091", 219 "SampleAfterValue": "100003", 220 "UMask": "0x1" 221 }, 222 { 223 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", 224 "EventCode": "0xB7, 0xBB", 225 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", 226 "MSRIndex": "0x1a6,0x1a7", 227 "MSRValue": "0x604000091", 228 "SampleAfterValue": "100003", 229 "UMask": "0x1" 230 }, 231 { 232 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", 233 "EventCode": "0xB7, 0xBB", 234 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", 235 "MSRIndex": "0x1a6,0x1a7", 236 "MSRValue": "0x63BC00091", 237 "SampleAfterValue": "100003", 238 "UMask": "0x1" 239 }, 240 { 241 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", 242 "EventCode": "0xB7, 0xBB", 243 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", 244 "MSRIndex": "0x1a6,0x1a7", 245 "MSRValue": "0x103FC00091", 246 "SampleAfterValue": "100003", 247 "UMask": "0x1" 248 }, 249 { 250 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", 251 "EventCode": "0xB7, 0xBB", 252 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", 253 "MSRIndex": "0x1a6,0x1a7", 254 "MSRValue": "0x87FC00091", 255 "SampleAfterValue": "100003", 256 "UMask": "0x1" 257 }, 258 { 259 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", 260 "EventCode": "0xB7, 0xBB", 261 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", 262 "MSRIndex": "0x1a6,0x1a7", 263 "MSRValue": "0x3FBFC007F7", 264 "SampleAfterValue": "100003", 265 "UMask": "0x1" 266 }, 267 { 268 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", 269 "EventCode": "0xB7, 0xBB", 270 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", 271 "MSRIndex": "0x1a6,0x1a7", 272 "MSRValue": "0x6040007F7", 273 "SampleAfterValue": "100003", 274 "UMask": "0x1" 275 }, 276 { 277 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", 278 "EventCode": "0xB7, 0xBB", 279 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", 280 "MSRIndex": "0x1a6,0x1a7", 281 "MSRValue": "0x63BC007F7", 282 "SampleAfterValue": "100003", 283 "UMask": "0x1" 284 }, 285 { 286 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", 287 "EventCode": "0xB7, 0xBB", 288 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", 289 "MSRIndex": "0x1a6,0x1a7", 290 "MSRValue": "0x103FC007F7", 291 "SampleAfterValue": "100003", 292 "UMask": "0x1" 293 }, 294 { 295 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", 296 "EventCode": "0xB7, 0xBB", 297 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", 298 "MSRIndex": "0x1a6,0x1a7", 299 "MSRValue": "0x87FC007F7", 300 "SampleAfterValue": "100003", 301 "UMask": "0x1" 302 }, 303 { 304 "BriefDescription": "Counts all requests miss in the L3", 305 "EventCode": "0xB7, 0xBB", 306 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", 307 "MSRIndex": "0x1a6,0x1a7", 308 "MSRValue": "0x3FBFC08FFF", 309 "SampleAfterValue": "100003", 310 "UMask": "0x1" 311 }, 312 { 313 "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", 314 "EventCode": "0xB7, 0xBB", 315 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", 316 "MSRIndex": "0x1a6,0x1a7", 317 "MSRValue": "0x3FBFC00122", 318 "SampleAfterValue": "100003", 319 "UMask": "0x1" 320 }, 321 { 322 "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", 323 "EventCode": "0xB7, 0xBB", 324 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", 325 "MSRIndex": "0x1a6,0x1a7", 326 "MSRValue": "0x604000122", 327 "SampleAfterValue": "100003", 328 "UMask": "0x1" 329 }, 330 { 331 "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", 332 "EventCode": "0xB7, 0xBB", 333 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", 334 "MSRIndex": "0x1a6,0x1a7", 335 "MSRValue": "0x3FBFC00002", 336 "SampleAfterValue": "100003", 337 "UMask": "0x1" 338 }, 339 { 340 "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", 341 "EventCode": "0xB7, 0xBB", 342 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", 343 "MSRIndex": "0x1a6,0x1a7", 344 "MSRValue": "0x103FC00002", 345 "SampleAfterValue": "100003", 346 "UMask": "0x1" 347 }, 348 { 349 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", 350 "EventCode": "0xB7, 0xBB", 351 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", 352 "MSRIndex": "0x1a6,0x1a7", 353 "MSRValue": "0x3FBFC00200", 354 "SampleAfterValue": "100003", 355 "UMask": "0x1" 356 }, 357 { 358 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", 359 "EventCode": "0xB7, 0xBB", 360 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", 361 "MSRIndex": "0x1a6,0x1a7", 362 "MSRValue": "0x3FBFC00100", 363 "SampleAfterValue": "100003", 364 "UMask": "0x1" 365 }, 366 { 367 "BriefDescription": "Number of times RTM abort was triggered", 368 "EventCode": "0xc9", 369 "EventName": "RTM_RETIRED.ABORTED", 370 "PEBS": "1", 371 "PublicDescription": "Number of times RTM abort was triggered .", 372 "SampleAfterValue": "2000003", 373 "UMask": "0x4" 374 }, 375 { 376 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 377 "EventCode": "0xc9", 378 "EventName": "RTM_RETIRED.ABORTED_MISC1", 379 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", 380 "SampleAfterValue": "2000003", 381 "UMask": "0x8" 382 }, 383 { 384 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 385 "EventCode": "0xc9", 386 "EventName": "RTM_RETIRED.ABORTED_MISC2", 387 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", 388 "SampleAfterValue": "2000003", 389 "UMask": "0x10" 390 }, 391 { 392 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 393 "EventCode": "0xc9", 394 "EventName": "RTM_RETIRED.ABORTED_MISC3", 395 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", 396 "SampleAfterValue": "2000003", 397 "UMask": "0x20" 398 }, 399 { 400 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 401 "EventCode": "0xc9", 402 "EventName": "RTM_RETIRED.ABORTED_MISC4", 403 "PublicDescription": "Number of times a RTM caused a fault.", 404 "SampleAfterValue": "2000003", 405 "UMask": "0x40" 406 }, 407 { 408 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 409 "EventCode": "0xc9", 410 "EventName": "RTM_RETIRED.ABORTED_MISC5", 411 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", 412 "SampleAfterValue": "2000003", 413 "UMask": "0x80" 414 }, 415 { 416 "BriefDescription": "Number of times RTM commit succeeded", 417 "EventCode": "0xc9", 418 "EventName": "RTM_RETIRED.COMMIT", 419 "PublicDescription": "Number of times RTM commit succeeded.", 420 "SampleAfterValue": "2000003", 421 "UMask": "0x2" 422 }, 423 { 424 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", 425 "EventCode": "0xc9", 426 "EventName": "RTM_RETIRED.START", 427 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", 428 "SampleAfterValue": "2000003", 429 "UMask": "0x1" 430 }, 431 { 432 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", 433 "EventCode": "0x5d", 434 "EventName": "TX_EXEC.MISC1", 435 "SampleAfterValue": "2000003", 436 "UMask": "0x1" 437 }, 438 { 439 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", 440 "EventCode": "0x5d", 441 "EventName": "TX_EXEC.MISC2", 442 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", 443 "SampleAfterValue": "2000003", 444 "UMask": "0x2" 445 }, 446 { 447 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", 448 "EventCode": "0x5d", 449 "EventName": "TX_EXEC.MISC3", 450 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", 451 "SampleAfterValue": "2000003", 452 "UMask": "0x4" 453 }, 454 { 455 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", 456 "EventCode": "0x5d", 457 "EventName": "TX_EXEC.MISC4", 458 "PublicDescription": "RTM region detected inside HLE.", 459 "SampleAfterValue": "2000003", 460 "UMask": "0x8" 461 }, 462 { 463 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", 464 "EventCode": "0x5d", 465 "EventName": "TX_EXEC.MISC5", 466 "SampleAfterValue": "2000003", 467 "UMask": "0x10" 468 }, 469 { 470 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", 471 "EventCode": "0x54", 472 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 473 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", 474 "SampleAfterValue": "2000003", 475 "UMask": "0x2" 476 }, 477 { 478 "BriefDescription": "Number of times a TSX line had a cache conflict", 479 "EventCode": "0x54", 480 "EventName": "TX_MEM.ABORT_CONFLICT", 481 "PublicDescription": "Number of times a TSX line had a cache conflict.", 482 "SampleAfterValue": "2000003", 483 "UMask": "0x1" 484 }, 485 { 486 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 487 "EventCode": "0x54", 488 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 489 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 490 "SampleAfterValue": "2000003", 491 "UMask": "0x10" 492 }, 493 { 494 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", 495 "EventCode": "0x54", 496 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 497 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 498 "SampleAfterValue": "2000003", 499 "UMask": "0x8" 500 }, 501 { 502 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", 503 "EventCode": "0x54", 504 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 505 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 506 "SampleAfterValue": "2000003", 507 "UMask": "0x20" 508 }, 509 { 510 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", 511 "EventCode": "0x54", 512 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 513 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 514 "SampleAfterValue": "2000003", 515 "UMask": "0x4" 516 }, 517 { 518 "BriefDescription": "Number of times we could not allocate Lock Buffer", 519 "EventCode": "0x54", 520 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 521 "PublicDescription": "Number of times we could not allocate Lock Buffer.", 522 "SampleAfterValue": "2000003", 523 "UMask": "0x40" 524 } 525] 526