1[ 2 { 3 "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 4 "EventCode": "0x5C", 5 "Counter": "0,1,2,3", 6 "UMask": "0x1", 7 "EventName": "CPL_CYCLES.RING0", 8 "SampleAfterValue": "2000003", 9 "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 10 "CounterHTOff": "0,1,2,3,4,5,6,7" 11 }, 12 { 13 "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 14 "EventCode": "0x5C", 15 "Counter": "0,1,2,3", 16 "UMask": "0x2", 17 "EventName": "CPL_CYCLES.RING123", 18 "SampleAfterValue": "2000003", 19 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 20 "CounterHTOff": "0,1,2,3,4,5,6,7" 21 }, 22 { 23 "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 24 "EventCode": "0x5C", 25 "Counter": "0,1,2,3", 26 "UMask": "0x1", 27 "EdgeDetect": "1", 28 "EventName": "CPL_CYCLES.RING0_TRANS", 29 "SampleAfterValue": "100007", 30 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 31 "CounterMask": "1", 32 "CounterHTOff": "0,1,2,3,4,5,6,7" 33 }, 34 { 35 "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 36 "EventCode": "0x63", 37 "Counter": "0,1,2,3", 38 "UMask": "0x1", 39 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40 "SampleAfterValue": "2000003", 41 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 42 "CounterHTOff": "0,1,2,3,4,5,6,7" 43 } 44]