xref: /linux/tools/perf/pmu-events/arch/x86/bonnell/frontend.json (revision 5e0266f0e5f57617472d5aac4013f58a3ef264ac) 
1[
2    {
3        "BriefDescription": "BACLEARS asserted.",
4        "EventCode": "0xE6",
5        "EventName": "BACLEARS.ANY",
6        "SampleAfterValue": "2000000",
7        "UMask": "0x1"
8    },
9    {
10        "BriefDescription": "Cycles during which instruction fetches are  stalled.",
11        "EventCode": "0x86",
12        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
13        "SampleAfterValue": "2000000",
14        "UMask": "0x1"
15    },
16    {
17        "BriefDescription": "Decode stall due to IQ full",
18        "EventCode": "0x87",
19        "EventName": "DECODE_STALL.IQ_FULL",
20        "SampleAfterValue": "2000000",
21        "UMask": "0x2"
22    },
23    {
24        "BriefDescription": "Decode stall due to PFB empty",
25        "EventCode": "0x87",
26        "EventName": "DECODE_STALL.PFB_EMPTY",
27        "SampleAfterValue": "2000000",
28        "UMask": "0x1"
29    },
30    {
31        "BriefDescription": "Instruction fetches.",
32        "EventCode": "0x80",
33        "EventName": "ICACHE.ACCESSES",
34        "SampleAfterValue": "200000",
35        "UMask": "0x3"
36    },
37    {
38        "BriefDescription": "Icache hit",
39        "EventCode": "0x80",
40        "EventName": "ICACHE.HIT",
41        "SampleAfterValue": "200000",
42        "UMask": "0x1"
43    },
44    {
45        "BriefDescription": "Icache miss",
46        "EventCode": "0x80",
47        "EventName": "ICACHE.MISSES",
48        "SampleAfterValue": "200000",
49        "UMask": "0x2"
50    },
51    {
52        "BriefDescription": "All Instructions decoded",
53        "EventCode": "0xAA",
54        "EventName": "MACRO_INSTS.ALL_DECODED",
55        "SampleAfterValue": "2000000",
56        "UMask": "0x3"
57    },
58    {
59        "BriefDescription": "CISC macro instructions decoded",
60        "EventCode": "0xAA",
61        "EventName": "MACRO_INSTS.CISC_DECODED",
62        "SampleAfterValue": "2000000",
63        "UMask": "0x2"
64    },
65    {
66        "BriefDescription": "Non-CISC nacro instructions decoded",
67        "EventCode": "0xAA",
68        "EventName": "MACRO_INSTS.NON_CISC_DECODED",
69        "SampleAfterValue": "2000000",
70        "UMask": "0x1"
71    },
72    {
73        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
74        "CounterMask": "1",
75        "EventCode": "0xA9",
76        "EventName": "UOPS.MS_CYCLES",
77        "SampleAfterValue": "2000000",
78        "UMask": "0x1"
79    }
80]
81